TWI868983B - Pixel circuit - Google Patents

Abstract

A pixel circuit is provided. The pixel circuit includes a light emitting diode, a pulse width control circuit, a pulse amplitude control circuit and a voltage control circuit. The light emitting diode receives a system low voltage. The pulse width control circuit provides a pulse width control voltage based on a data voltage and a swing voltage. The pulse amplitude control circuit is coupled to the light emitting diode and has a control node. The voltage control circuit receives a system high voltage and the pulse width control voltage, and is coupled to the control node. The voltage control circuit provides the system high voltage to the control node based on the pulse width control voltage. The pulse amplitude control circuit provides a driving current to the light emitting diode in response to the control node receiving the system high voltage.

Description

Pixel circuit

The present invention relates to a pixel circuit, and in particular to a light emitting diode pixel circuit.

As environmental awareness rises, energy saving, lifespan, color saturation, and power quality are gradually becoming factors that consumers consider when purchasing. At the same time, the rapid development of semiconductor technology and the reduction of costs have driven light-emitting components to become the mainstream of the future lighting and display market. Among them, organic light-emitting diodes (OLEDs) and micro-light-emitting diodes (uLEDs) are the main components currently used in self-luminous display panels.

However, the luminance curves of micro-LEDs (uLEDs) and organic LEDs (OLEDs) are different, that is, when operating at the same brightness, the luminous efficiency of the LEDs is very low. In addition, since the current range operated by the voltage regulation circuit of the organic LED falls within the low luminous efficiency range of the micro-LED, the driving circuit of the organic LED developed earlier cannot be directly applied to the micro-LED. Therefore, in order to drive the micro-LED, the existing driving circuit needs to be modified or redesigned accordingly.

The present invention provides a pixel circuit that can provide a current path for driving current to a light-emitting diode by conducting a system high voltage, thereby reducing the time required to turn on the light-emitting diode.

The pixel circuit of the present invention includes a light-emitting diode, a pulse width control circuit, a pulse amplitude control circuit and a voltage control circuit. The light-emitting diode has an anode and a cathode receiving a system low voltage. The pulse width control circuit receives a data voltage and a swing voltage to provide a pulse width control voltage based on the data voltage and the swing voltage. The pulse amplitude control circuit receives a system high voltage, a high voltage and a first reference voltage, is coupled to the cathode of the light-emitting diode, and has a control node. The voltage control circuit receives a system high voltage and a pulse width control voltage, and is coupled to the control node. The voltage control circuit provides the system high voltage to the control node based on the pulse width control voltage. The pulse amplitude control circuit provides a driving current to the cathode in response to the control node receiving the system high voltage, and the driving current is related to the high voltage and the first reference voltage.

Based on the above, the pixel circuit of the embodiment of the present invention provides a current path for driving current to the LED through the system high voltage conduction. Since the system high voltage has a larger current (i.e., a higher driving capability), the conduction time of the current path can be accelerated, which can reduce the time required to turn on the LED.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless expressly defined as such herein.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and/or "include" specify the presence and/or parts of the features, regions, wholes, steps, operations, elements, components and/or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and/or combinations thereof.

FIG1 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. Referring to FIG1 , in this embodiment, the pixel circuit 100 includes a light emitting diode XLD1, a pulse width control circuit CT _PWM , a voltage control circuit CT _vdd , and a pulse amplitude control circuit CT _pam , wherein the light emitting diode XLD1 includes, for example, a micro light emitting diode XLD1.

The light-emitting diode XLD1 has an anode and a cathode receiving a system low voltage V _SS . The pulse width control circuit CT _PWM receives a data voltage V _DATA and a swing voltage V _sweep to provide a pulse width control voltage V _PWM based on the data voltage V _DATA and the swing voltage V _sweep . The pulse amplitude control circuit CT _pam receives a system high voltage V _DD , a high voltage V _H and a first reference voltage V _REF , is coupled to the cathode of the light-emitting diode XLD1 , and has a node B (corresponding to a control node). The voltage control circuit CT _vdd receives the system high voltage V _DD and the pulse width control voltage V _PWM and is coupled to the node B, wherein the voltage control circuit CT _vdd provides the system high voltage V _DD to the control node B based on the pulse width control voltage V _PWM . The pulse amplitude control circuit CT _pam reacts to the node B receiving the system high voltage V _DD and turns on (or opens) a current path between the system high voltage V _DD and the system low voltage V _SS to provide a driving current I _dr to the cathode of the light-emitting diode XLD1, and the driving current I _dr is related to the high voltage V _H and the first reference voltage V _REF .

According to the above, the pixel circuit 100 provides a current path for driving the current I _dr to the light-emitting diode XLD1 through the system high voltage V _DD . Since the system high voltage V _DD has a larger current (i.e., a higher driving capability), the conduction time of the current path can be accelerated, which can reduce the time required to turn on the light-emitting diode XLD1.

In this embodiment, the pulse width control circuit CT _PWM includes transistors T1-T7 (corresponding to the first transistor to the seventh transistor) and capacitors C1-C3 (corresponding to the first capacitor to the third capacitor), wherein the transistors T1-T7 are, for example, P-type transistors.

The transistor T1 has a first end for receiving the second reference voltage V _REF2 , a control end for receiving the first light emitting signal mEM, and a second end. The transistor T2 has a first end coupled to the second end of the transistor T1, a control end, and a second end. The transistor T3 has a first end coupled to the second end of the transistor T2, a control end for receiving the first light emitting signal mEM, and a second end. The transistor T4 has a first end coupled to the second end of the transistor T1, a control end for receiving the control signal _SN (corresponding to the first control signal), and a second end for receiving the data voltage _VDATA , wherein N can be a positive integer greater than or equal to 1.

The transistor T5 has a first end coupled to the second end of the transistor T3, a control end receiving the second light emitting signal mEMB, and a second end receiving the low voltage V _L. The transistor T6 has a first end receiving the low voltage V _L , a control end receiving the control signal SN _-1 (corresponding to the second control signal), and a second end coupled to the control end of the transistor T2. The transistor T7 has a first end coupled to the control end of the transistor T2, a control end receiving the control signal _SN , and a second end coupled to the second end of the second transistor T2.

Capacitor C1 is coupled between the swing voltage V _sweep and the control terminal of transistor T2. Capacitor C2 is coupled between the low voltage V _L and the second terminal of transistor T3. Capacitor C3 is coupled between the second terminal of transistor T3 and the voltage control circuit CT _vdd to provide a pulse width control voltage V _PWM .

In this embodiment, the voltage control circuit CT _vdd includes eight transistors T8 ˜ T11 (corresponding to the eighth transistor to the eleventh transistor), wherein the transistors T9 and T10 are, for example, P-type transistors, and the transistors T8 and T11 are, for example, N-type transistors.

The eighth transistor T8 has a first end receiving the second reference voltage V _REF2 , a control end receiving the second reference voltage V _REF2 , and a second end. The transistor T9 has a first end coupled to the second end of the transistor T6, a control end receiving the control signal _SN , and a second end receiving the pulse width control voltage V _PWM . The transistor T10 has a first end coupled to the second end of the transistor T9, a control end receiving the control signal SN _-1 , and a second end receiving the first reference voltage V _REF . The transistor T11 has a first end coupled to the node B, a control end coupled to the second end of the transistor T9, and a second end receiving the system high voltage V _DD .

In this embodiment, the pulse amplitude control circuit CT _pam includes transistors T12 - T18 (corresponding to the twelfth to eighteenth transistors) and capacitors C4 - C5 (corresponding to the fourth capacitor and the fifth capacitor), wherein the transistors T12 - T18 are, for example, P-type transistors.

The transistor T12 has a first end receiving the system high voltage V _DD , a control end receiving the first light-emitting signal mEM, and a second end. The transistor T13 has a first end coupled to the second end of the transistor T12, a control end, and a second end. The transistor T14 has a first end coupled to the second end of the transistor T13, a control end receiving the first light-emitting signal mEM, and a second end providing a driving current I _dr . The transistor T15 has a first end coupled to the second end of the transistor T12, a control end receiving the control signal _SN , and a second end.

The transistor T16 has a first end coupled to the control end of the transistor T13, a control end receiving the control signal _SN , and a second end coupled to the second end of the transistor T13. The transistor T17 has a first end receiving the high voltage _VH , a control end receiving the second light emitting signal mEMB, and a second end coupled to the node B. The transistor T18 has a first end receiving the low voltage _VL , a control end receiving the control signal SN _-1 , and a second end coupled to the control end of the transistor T13. The fourth capacitor C4 is coupled between the low voltage _VL and the node B. The capacitor C5 is coupled between the control node B and the control end of the transistor T13.

In this embodiment, the driving current _Idr is provided to the cathode of the light emitting diode XLD1 only through the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14.

According to the above, the embodiment of the present invention proposes a circuit structure of 18 transistors and 5 capacitors (18T5C) for the driving circuit in the LED pixel circuit, which can be applied to the micro-LED spliced display. The purpose of the circuit structure of the embodiment of the present invention is to compensate for the critical voltage of transistors T2, T11 and T13, and the variation of the current resistance voltage drop (IR drop) of the system high voltage V _DD , and use the node F to perform fast charging to make the pulse width control voltage V _PWM rise quickly, thereby reducing the rise time of the driving current I _dr generated by the pulse width modulation (PWM) driving method and increasing the grayscale control accuracy.

FIG2 is a schematic diagram of a driving waveform of a pixel circuit according to an embodiment of the present invention. Referring to FIG1 and FIG2, in this embodiment, a single frame period may have at least an initial period Pini, a compensation writing period Pcdi, a light-emitting period Pemi, a stabilization period Pstb, and a shut-down period Poff, wherein the light-emitting period Pemi and the stabilization period Pstb are repeated to perform multiple light-emitting functions.

In this embodiment, the control signal _SN-1 may be a control signal _SN provided to a pixel circuit (such as 100) of a previous stage or a previous row, that is, the phase of the control signal _SN-1 leads the control signal _SN , wherein the control signal SN _-1 and _SN are switched between, for example, a gate high voltage _VGH and a gate low voltage _VGL . In addition, the second light-emitting signal mEMB may be an inverted signal of the first light-emitting signal mEM, that is, the second light-emitting signal mEMB is inverted to the first light-emitting signal mEM, wherein the first light-emitting signal mEM and the second light-emitting signal mEMB are switched between, for example, a gate high voltage _VGH and a gate low voltage _VGL . Moreover, the swing voltage V _sweep switches between the swing high voltage V _SWH and the swing low voltage V _SWL , for example. In an embodiment of the present invention, the system high voltage V _DD , the high voltage V _H , the first reference voltage V _REF , the second reference voltage V _REF2 , the system low voltage V _SS , and the low voltage V _L can be as follows: V _H ＞ V _DD = V _REF ＞ V _REF2 ＞ V _SS ＞ V _L .

In the initial period Pini, the control signal _SN and the first light-emitting signal mEM are gate high voltage _VGH , the control signal SN _-1 and the second light-emitting signal mEMB are gate low voltage _VGL , and the swing voltage _Vsweep is swing high voltage _VSWH . At this time, transistors T5, T6, T10, T17, and T18 are turned on, and transistors T1, T3, T4, T7, T8, T9, T12, T14, T15, and T16 are turned off (or cut off). Furthermore, the voltage level of node A is a low voltage V _L , the voltage level of node B is a high voltage V _H , the voltage level of node C is a first reference voltage V _REF , the voltage level of node D is a floating voltage, the voltage level of node E is a low voltage V _L , and the voltage level of node F is a low voltage V _L . Among them, transistor T2 is turned on in response to the voltage level of node E, transistor T11 is turned off in response to the voltage level of node C (i.e., the pulse width control voltage V _PWM ), and transistor T13 is turned off in response to the voltage level of node A. In this way, the state of the pixel circuit 100 can be initialized.

During the compensation writing period Pcdi, the control signal SN _-1 and the first light emission signal mEM are gate high voltage _VGH , the control signal _SN and the second light emission signal mEMB are gate low voltage _VGL , and the swing voltage _Vsweep is swing high voltage _VSWH . At this time, transistors T4, T5, T7, T8, T9, T15, T16, and T17 are turned on, and transistors T1, T3, T6, T10, T12, T14, and T18 are turned off (or cut off). Furthermore, the voltage level of node A is the first reference voltage V _REF minus the critical voltage of transistor T13, the voltage level of node B is the high voltage V _H , the voltage level of node C is the second reference voltage V _REF2 plus the critical voltage of transistor T8 , the voltage level of node D is the data voltage V _DATA minus the critical voltage of transistor T2 , the voltage level of node E is the data voltage V _DATA minus the critical voltage of transistor T2 , and the voltage level of node F is the low voltage V _L . The transistor T2 is turned on in response to the voltage level of the node E, the transistor T11 is turned off in response to the voltage level of the node C (i.e., the pulse width control voltage V _PWM ), and the transistor T13 is turned on in response to the voltage level of the node A. Thus, the data voltage V _DATA can be written into the pixel circuit 100, and the critical voltages of the transistors T2 , T11 , and T13 can be compensated.

During the luminescence period Pemi, the control signals _SN and SN _-1 and the second luminescence signal mEMB are gate high voltage _VGH , the first luminescence signal mEM is gate low voltage _VGL , and the swing voltage _Vsweep decreases from the swing high voltage _VSWH to the swing low voltage _VSWL over time. At this time, transistors T1, T3, T12, and T14 are turned on, and transistors T4, T5, T6, T7, T8, T9, T10, T15, T16, T17, and T18 are not turned on (or cut off). Furthermore, the voltage level of node A is the first reference voltage V _REF minus the critical voltage of transistor T13, the voltage level of node B is the high voltage V _H , the voltage level of node C is the second reference voltage V _REF2 plus the critical voltage of transistor T8 , the voltage level of node D is the low voltage V _L , the voltage level of node E is the data voltage V _DATA - the critical voltage of transistor T2 - ΔV _sweep , and the voltage level of node F is the low voltage V _L , where ΔV _sweep is the voltage difference of the swing voltage V _sweep decreasing. Furthermore, the transistor T2 is turned off in response to the voltage level of the node E, the transistor T11 is turned off in response to the voltage level of the node C (ie, the pulse width control voltage V _PWM ), and the transistor T13 is turned off in response to the voltage level of the node A.

Then, when the voltage level of node E drops to turn on transistor T2, the voltage level of node C (i.e., the pulse width control voltage V _PWM ) is raised by the second reference voltage V _REF2 , thereby turning on transistor T11. After transistor T11 is turned on, the system high voltage V _DD is provided to node B, thereby lowering the voltage level of node A to turn on transistor T13. At this time, the turned-on transistors T12~T14 will provide a driving current I _dr to the light-emitting diode XLD1. Furthermore, the voltage level of node A is the first reference voltage V _REF −critical voltage of transistor T13 + system high voltage V _DD −high voltage V _H , the voltage level of node B is the system high voltage V _DD , the voltage level of node C is 2×second reference voltage V _REF2 +critical voltage of transistor T8 −low voltage V _L , the voltage level of node D is the second reference voltage V _REF2 , the voltage level of node E is the data voltage V _DATA −critical voltage of transistor T2 −ΔV _sweep , and the voltage level of node F is the second reference voltage V _REF2 . Thereby, the turn-on time of the transistor T13 can be controlled in response to the data voltage V _DATA , and the amplitude of the driving current I _dr can be set in response to the voltage difference between the high voltage V _H and the second reference voltage V _REF2 .

During the stable period Pstb and the off period Poff, the control signals _SN and SN _-1 and the first light-emitting signal mEM are gate high voltage _VGH , the second light-emitting signal mEMB is gate low voltage _VGL , and the swing voltage _Vsweep is swing high voltage _VSWH . At this time, transistors T5 and T17 are turned on, and transistors T1, T3, T4, T6, T7, T8, T9, T10, T12, T14, T15, T16, and T18 are not turned on (or turned off). Furthermore, the voltage level of node A is the first reference voltage _VREF minus the critical voltage of transistor T13, the voltage level of node B is the high voltage _VH , the voltage level of node C is the second reference voltage _VREF2 plus the critical voltage of transistor T8, the voltage level of node D is the low voltage _VL , the voltage level of node E is the data voltage _VDATA minus the critical voltage of transistor T2, and the voltage level of node F is the low voltage _VL . Furthermore, the transistor T2 is turned off in response to the voltage level of the node E, the transistor T11 is turned off in response to the voltage level of the node C (ie, the pulse width control voltage V _PWM ), and the transistor T13 is turned off in response to the voltage level of the node A.

According to the above, the circuit structure of the embodiment of the present invention can have the function of PWM multi-emission, by compensating the critical voltage variation of transistor T2 (i.e., the control transistor) and transistor T13 (i.e., the control transistor) and the variation of the current-resistance voltage drop (IR drop) of the system high voltage V _DD by itself, and by matching the transistor T11 written by the control system high voltage V _DD , the control accuracy of low grayscale is improved, and the brightness uniformity is improved.

In summary, the pixel circuit of the embodiment of the present invention provides a current path for driving current to the LED through a system high voltage conduction. Since the system high voltage has a larger current (i.e., a higher driving capability), the conduction time of the current path can be accelerated, which can reduce the time required to turn on the LED.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100: Pixel circuit

A~F: Node

C1~C5: Capacitor

CT _pam : Pulse amplitude control circuit

CT _PWM : Pulse Width Control Circuit

CT _vdd : voltage control circuit

I _dr : driving current

mEM: first luminescence signal

mEMB: Second light signal

Pcdi: Compensation write period

Pemi: Glowing period

Pini: Initial period

Poff: Off period

Pstb: Stable period

_SN , SN _-1 : control signal

T1~T18: Transistor

V _DATA : Data voltage

V _DD : System high voltage

V _GH : Gate high voltage

V _GL : Gate Low Voltage

V _H : High Voltage

V _L : Low voltage

V _PWM : Pulse width control voltage

V _REF : First reference voltage

V _REF2 : Second reference voltage

V _SS : System low voltage

V _sweep : swing voltage

V _SWH : Swing High Voltage

V _SWL : Swing Low Voltage

XLD1: Light Emitting Diode

FIG1 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. FIG2 is a driving waveform diagram of a pixel circuit according to an embodiment of the present invention.

100: Pixel circuit

A~F: Node

C1~C5: Capacitor

CT _pam : Pulse amplitude control circuit

CT _PWM : Pulse Width Control Circuit

CT _vdd : voltage control circuit

I _dr : driving current

mEM: first luminescence signal

mEMB: Second light signal

_SN , SN _-1 : control signal

T1~T18: Transistor

V _DATA : Data voltage

V _DD : System high voltage

V _H : High Voltage

V _L : Low voltage

V _PWM : Pulse width control voltage

V _REF : First reference voltage

V _REF2 : Second reference voltage

V _SS : System low voltage

V _sweep : swing voltage

XLD1: Light Emitting Diode

Claims (9)

A pixel circuit includes: a light-emitting diode having an anode and a cathode receiving a system low voltage; a pulse width control circuit receiving a data voltage and a swing voltage to provide a pulse width control voltage based on the data voltage and the swing voltage; a pulse amplitude control circuit receiving a system high voltage, a high voltage and a first reference voltage, coupled to the cathode of the light-emitting diode and having a control node; a voltage A control circuit receives the system high voltage and the pulse width control voltage and is coupled to the control node, wherein the voltage control circuit provides the system high voltage to the control node based on the pulse width control voltage, wherein the pulse amplitude control circuit provides a driving current to the cathode in response to the control node receiving the system high voltage, and an amplitude of the driving current is related to a voltage difference between the high voltage and the first reference voltage. The pixel circuit as described in claim 1, wherein the pulse width control circuit comprises: a first transistor having a first end receiving a second reference voltage, a control end receiving a first light-emitting signal, and a second end; a second transistor having a first end coupled to the second end of the first transistor, a control end, and a second end; a third transistor having a first end coupled to the second end of the second transistor, a control end receiving the first light-emitting signal, and a second end; a fourth transistor having a first end coupled to the second end of the first transistor, a control end receiving a first control signal, and a second end receiving the data voltage; a fifth transistor having a first end coupled to the second end of the third transistor, a control end receiving the first light-emitting signal, and a second end receiving the data voltage; a control end for a second light-emitting signal, and a second end for receiving a low voltage; a sixth transistor having a first end for receiving the low voltage, a control end for receiving a second control signal, and a second end coupled to the control end of the second transistor; a seventh transistor having a first end coupled to the control end of the second transistor, a control end for receiving the first control signal, and a second end coupled to the second end of the second transistor; a first capacitor coupled between the swing voltage and the control end of the second transistor; a second capacitor coupled between the low voltage and the second end of the third transistor; and a third capacitor coupled between the second end of the third transistor and the voltage control circuit to provide the pulse width control voltage. A pixel circuit as described in claim 2, wherein the voltage control circuit comprises: an eighth transistor having a first end receiving the second reference voltage, a control end receiving the second reference voltage, and a second end; a ninth transistor having a first end coupled to the second end of the sixth transistor, a control end receiving the first control signal, and a second end receiving the pulse width control voltage; a tenth transistor having a first end coupled to the second end of the ninth transistor, a control end receiving the second control signal, and a second end receiving the first reference voltage; and an eleventh transistor having a first end coupled to the control node, a control end coupled to the second end of the ninth transistor, and a second end receiving the system high voltage. The pixel circuit as described in claim 3, wherein the pulse amplitude control circuit includes: a twelfth transistor having a first end receiving the system high voltage, a control end receiving the first light-emitting signal, and a second end; a thirteenth transistor having a first end coupled to the second end of the twelfth transistor, a control end, and a second end; a fourteenth transistor having a first end coupled to the second end of the thirteenth transistor, a control end receiving the first light-emitting signal, and a second end providing the driving current; a fifteenth transistor having a first end coupled to the second end of the twelfth transistor, a control end receiving the first control signal, and a second end; A sixteenth transistor having a first end coupled to the control end of the thirteenth transistor, a control end receiving the first control signal, and a second end coupled to the second end of the thirteenth transistor; a seventeenth transistor having a first end receiving the high voltage, a control end receiving the second light-emitting signal, and a second end coupled to the control node; an eighteenth transistor having a first end receiving the low voltage, a control end receiving the second control signal, and a second end coupled to the control end of the thirteenth transistor; a fourth capacitor coupled between the low voltage and the control node; and a fifth capacitor coupled between the control node and the control end of the thirteenth transistor. The pixel circuit as described in claim 4, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the ninth transistor, the tenth transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor and the sixteenth transistor are each a P-type transistor, and the eighth transistor and the eleventh transistor are each an N-type transistor. A pixel circuit as described in claim 4, wherein the driving current is provided to the cathode of the light-emitting diode only through the twelfth transistor, the thirteenth transistor and the fourteenth transistor. A pixel circuit as described in claim 2, wherein the phase of the second control signal leads the first control signal. A pixel circuit as described in claim 2, wherein the second light-emitting signal is inverted to the first light-emitting signal. A pixel circuit as described in claim 1, wherein the light-emitting diode comprises a micro light-emitting diode.

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