TWI849805B - Method of setting material property of heterogeneous materials and electronic device - Google Patents
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- 239000000463 material Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000010949 copper Substances 0.000 claims abstract description 20
- 229910052802 copper Inorganic materials 0.000 claims abstract description 20
- 238000010586 diagram Methods 0.000 claims description 21
- 239000004033 plastic Substances 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 238000004458 analytical method Methods 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 238000011960 computer-aided design Methods 0.000 description 2
- 238000012938 design process Methods 0.000 description 2
- 125000000174 L-prolyl group Chemical group [H]N1C([H])([H])C([H])([H])C([H])([H])[C@@]1([H])C(*)=O 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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Abstract
Description
本發明係關於一種非均質材料性質的設定方法及電子裝置，尤指一種可有效提昇分析效率及準確性之非均質材料性質的設定方法及電子裝置。The present invention relates to a method and an electronic device for setting properties of heterogeneous materials, and in particular to a method and an electronic device for setting properties of heterogeneous materials that can effectively improve analysis efficiency and accuracy.
目前大多數的電子產品都會使用到印刷電路板（Printed Circuit Board，PCB）來嵌載各種電子零組件，因此印刷電路板已經成為電子產品的一個重要組成部分。隨著電子產品走向小型化與輕量化的發展，印刷電路板亦走向高密度、小孔、細線、薄型、多層的趨勢。一般來說，印刷電路板是由做為承載體的塑膠基板和用於傳導用的銅箔線路所組成，其中鋪銅線路通常錯綜複雜。也就是說，印刷電路板是屬於以兩種以上材料所組成的非均質材料產品。然而，複合材料於不同方向與不同區域之材料性質皆為不同。如此一來，當在產品製造設計時，應用電腦輔助工程（Computer Aided Engineering，CAE）技術來進行材料設定選擇時往往因此類複合材料無法單純以均質材料來設定而面臨分析上的困難，同時也難以兼顧分析效率與準確性。現有方式將銅箔密度較高的部分近似成一個較大區域，再將此區域另外設定成特定材料，但此法誤差較大且每個近似區域的材料性質亦不固定。因此，現有的技術實有改進之必要。Currently, most electronic products use printed circuit boards (PCBs) to embed various electronic components, so printed circuit boards have become an important component of electronic products. As electronic products develop towards miniaturization and lightweight, printed circuit boards also tend to be high-density, small-hole, thin-line, thin, and multi-layer. Generally speaking, printed circuit boards are composed of a plastic substrate as a carrier and copper foil lines for conduction, in which the copper-plated lines are usually complex. In other words, printed circuit boards are non-homogeneous material products composed of two or more materials. However, the material properties of composite materials are different in different directions and different regions. As a result, when applying Computer Aided Engineering (CAE) technology to select materials during product manufacturing and design, it is often difficult to analyze such composite materials because they cannot be simply configured as homogeneous materials. It is also difficult to balance analysis efficiency and accuracy. The existing method approximates the copper foil with a higher density into a larger area, and then sets this area as a specific material. However, this method has a large error and the material properties of each approximated area are not fixed. Therefore, the existing technology really needs to be improved.
為了解決上述之問題，本發明提供一種可有效提昇分析校路及準確性之非均質材料性質的設定方法及電子裝置，以解決上述問題。In order to solve the above problems, the present invention provides a method and an electronic device for setting the properties of heterogeneous materials that can effectively improve the analysis calibration and accuracy to solve the above problems.
本發明提供一種非均質材料性質的設定方法，取得一電路板之一電路佈局網格檔案，該電路佈局網格檔案包括被分成複數個網格之一電路佈局圖；取得該電路板之一鋪銅區域佈局檔案；將該電路佈局網格檔案及該鋪銅區域佈局檔案進行一影像疊加運作以取得該電路佈局網格檔案與該鋪銅區域佈局檔案之間之重疊交集區域；針對每一網格，計算對應於該每一網格之重疊交集區域的面積與該每一網格的面積之一交集面積比例；以及依據該交集面積比例設定該每一網格之材料性質。The present invention provides a method for setting the property of a non-homogeneous material. The method comprises the steps of obtaining a circuit layout grid file of a circuit board, wherein the circuit layout grid file includes a circuit layout diagram divided into a plurality of grids; obtaining a copper-laying area layout file of the circuit board; performing an image overlay operation on the circuit layout grid file and the copper-laying area layout file to obtain an overlapping intersection area between the circuit layout grid file and the copper-laying area layout file; calculating, for each grid, an intersection area ratio between an area of the overlapping intersection area corresponding to each grid and an area of each grid; and setting the material property of each grid according to the intersection area ratio.
本發明另提供一種電子裝置，包括︰一儲存裝置，用以儲存指令一處理電路，經配置用以執行所述指令，其中所述指令包括︰取得一電路板之一電路佈局網格檔案，該電路佈局網格檔案包括被分成複數個網格之一電路佈局圖；取得該電路板之一鋪銅區域佈局檔案；將該電路佈局網格檔案及該鋪銅區域佈局檔案進行一影像疊加運作以取得該電路佈局網格檔案與該鋪銅區域佈局檔案之間之重疊交集區域；針對每一網格，計算對應於該每一網格之重疊交集區域的面積與該每一網格的面積之一交集面積比例；以及依據該交集面積比例設定該每一網格之材料性質。The present invention further provides an electronic device, comprising: a storage device for storing instructions and a processing circuit configured to execute the instructions, wherein the instructions include: obtaining a circuit layout grid file of a circuit board, the circuit layout grid file including a circuit layout diagram divided into a plurality of grids; obtaining a copper-plated area layout file of the circuit board; An image overlay operation is performed on the circuit layout grid file and the copper paving area layout file to obtain the overlapping intersection area between the circuit layout grid file and the copper paving area layout file; for each grid, an intersection area ratio between the area of the overlapping intersection area corresponding to each grid and the area of each grid is calculated; and the material property of each grid is set according to the intersection area ratio.
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解，製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及後續的申請專利範圍並不以名稱的差異來做為區分元件的方式，而是以元件在功能上的差異來做為區分的基準。在通篇說明書及後續的申請專利範圍當中所提及的「包括」或「包含」係為一開放式的用語，故應解釋成「包括但不限定於」。另外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接於一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。Certain terms are used in this specification and subsequent patent applications to refer to specific components. A person of ordinary skill in the art should understand that manufacturers may use different terms to refer to the same component. This specification and subsequent patent applications do not use differences in name as a way to distinguish components, but rather use differences in the functions of the components as the basis for distinction. The words "including" or "comprising" mentioned throughout the specification and subsequent patent applications are open-ended terms and should be interpreted as "including but not limited to". In addition, the word "coupled" here includes any direct and indirect electrical connection means. Therefore, if a first device is described herein as being coupled to a second device, it means that the first device may be directly electrically connected to the second device, or may be indirectly electrically connected to the second device via other devices or connection means.
本發明實施例可應用於一印刷電路板之設計過程，藉由本發明實施例可於設計印刷電路板的過程中提供設定印刷電路板的非均質材料性質。請參考第1圖，第1圖為本發明實施例之一流程10之示意圖。流程10用以設定印刷電路板的材料性質。流程10包含以下步驟：The embodiment of the present invention can be applied to a design process of a printed circuit board. The embodiment of the present invention can be used to set the inhomogeneous material properties of the printed circuit board during the design process of the printed circuit board. Please refer to Figure 1, which is a schematic diagram of a
步驟S100：取得電路板之電路佈局網格檔案。Step S100: Obtain the circuit layout grid file of the circuit board.
步驟S102：得電路板之鋪銅區域佈局檔案。Step S102: Obtain the copper plating area layout file of the circuit board.
步驟S104：將電路佈局網格檔案及鋪銅區域佈局檔案進行影像疊加運作以取得兩者間之重疊交集區域。Step S104: Perform image overlay operation on the circuit layout grid file and the copper plating area layout file to obtain the overlapping intersection area between the two.
步驟S106：針對每一網格，計算對應於每一網格之重疊交集區域的面積與每一網格的面積之交集面積比例。Step S106: For each grid, calculate the intersection area ratio between the area of the overlapping intersection region corresponding to each grid and the area of each grid.
步驟S108：依據交集面積比例設定每一網格之材料性質。Step S108: Setting the material properties of each mesh according to the intersection area ratio.
根據流程10，於步驟S100中，本發明實施例可執行於一電子裝置的一電腦輔助設計（Computer Aided Design，CAD）軟體。電子裝置可包括一電腦裝置，且電腦裝置裝設有電腦輔助設計軟體，其中電腦輔助設計軟體可為AutoCAD、Pro/Engineer、SolidWorks，但不以此為限。本發明實施例可透過電腦輔助設計軟體產生一電路板之電路佈局圖檔案。所述電路佈局圖檔案包括電路板之電路佈局圖。所述電路板可為印刷電路板，但不以此為限。於取得所述電路佈局圖檔案後，可將電路佈局圖分成複數個網格以產生一電路佈局網格檔案。例如，將電路佈局圖的邊框區域或輪廓圖形切分成複數個網格。網格可為多邊形幾何圖形。例如，網格可為三角形網格，四邊形網格或其他多邊形網格。請參考第2圖，第2圖為本發明實施例之一電路佈局網格檔案20之示意圖。為便於說明第2圖僅顯示出電路佈局圖的一部份，如第2圖所示，電路佈局網格檔案20之電路佈局圖被劃分成多個多邊形網格。例如，於步驟S100中，可利用電腦輔助工程之ABAQUS分析軟體取得載入電腦輔助設計軟體所產生之電路佈局圖檔案，再將電路佈局網格檔案中之電路佈局圖劃分成複數個網格以產生相應電路佈局網格檔案。其中可透過設定網格之尺寸以及形狀以生成需要的網格元素。在一實施例中，ABAQUS分析軟體可輸出inp檔案格式的電路佈局網格檔案。接著，可利用Python程式軟體讀取所述inp檔案格式的電路佈局網格檔案並將電路佈局網格檔案中的網格轉換成多邊形資料結構以輸出地理空間數據交換格式（GeoJson）的電路佈局網格檔案。According to
於步驟S102中，可取得電路板之一鋪銅區域佈局檔案。其中鋪銅區域佈局檔案包括電路板之電路佈局圖之鋪銅區域。鋪銅區域包括線路走線、焊墊、通孔、接點、覆銅、灌銅及其他使用銅箔的區域。請參考第3圖，第3圖為本發明實施例之一鋪銅區域佈局檔案30之示意圖。為便於說明第3圖僅顯示出電路佈局圖之一部份的鋪銅區域，如第3圖所示，鋪銅區域佈局檔案30包括電路佈局圖之鋪銅區域。例如，可利用Python程式軟體讀取inp檔案格式的鋪銅區域佈局檔案並將鋪銅區域佈局檔案中的銅箔區域依照寬度轉換成多邊形資料結構以輸出地理空間數據交換格式的鋪銅區域佈局檔案。In step S102, a copper-plated area layout file of a circuit board can be obtained. The copper-plated area layout file includes the copper-plated area of the circuit layout diagram of the circuit board. The copper-plated area includes circuit traces, pads, through holes, contacts, copper coatings, copper pours and other areas using copper foil. Please refer to FIG. 3, which is a schematic diagram of a copper-plated
於步驟S104中，可將電路佈局網格檔案及鋪銅區域佈局檔案進行影像疊加運作以取得電路佈局網格檔案與鋪銅區域佈局檔案之間之重疊交集區域，也就是說，本發明實施例通過影像疊加技術的運作將電路佈局圖之每一網格區域與對應鋪銅區域的重疊交集區域判斷出來。例如，可利用Python程式軟體執行程式庫的Shapely套件來進行影像疊加運作，以取得電路佈局網格檔案與鋪銅區域佈局檔案之間之重疊交集區域。請參考第4圖，第4圖為本發明實施例之電路佈局網格檔案與鋪銅區域佈局檔案於影像疊加後的之實施例示意圖。例如，在網格M1中，網格M1與對應鋪銅區域的重疊交集區域為I1。在網格M2中，網格M2與對應鋪銅區域的重疊交集區域為I2。電路佈局網格檔案與鋪銅區域佈局檔案可具有相同檔案格式，以利於進行影像疊加運作，例如電路佈局網格檔案與鋪銅區域佈局檔案可為inp檔案格式、地理空間數據交換檔案格式，但不以此為限。In step S104, the circuit layout grid file and the copper-laying area layout file may be subjected to an image overlay operation to obtain the overlapping intersection area between the circuit layout grid file and the copper-laying area layout file. In other words, the embodiment of the present invention determines the overlapping intersection area between each grid area of the circuit layout diagram and the corresponding copper-laying area through the operation of the image overlay technology. For example, the Shapely package of the Python program library may be used to perform the image overlay operation to obtain the overlapping intersection area between the circuit layout grid file and the copper-laying area layout file. Please refer to FIG. 4, which is a schematic diagram of an embodiment of the circuit layout grid file and the copper-paving area layout file after image superposition of the embodiment of the present invention. For example, in grid M1, the overlapping intersection area of grid M1 and the corresponding copper-paving area is I1. In grid M2, the overlapping intersection area of grid M2 and the corresponding copper-paving area is I2. The circuit layout grid file and the copper-paving area layout file can have the same file format to facilitate image superposition operation. For example, the circuit layout grid file and the copper-paving area layout file can be inp file format or geospatial data exchange file format, but it is not limited thereto.
於步驟S106中，可針對每一網格，計算對應於每一網格之重疊交集區域的面積與每一網格的面積之一交集面積比例。例如，計算出對應於每一網格之重疊交集區域的面積以及每一網格的面積，並將對應於每一網格之重疊交集區域的面積除以每一網格的面積以得到對應之交集面積比例。請繼續參考第4圖，以在網格M1中，網格M1與對應鋪銅區域的重疊交集區域為I1。於計算出網格M1之面積及重疊交集區域I1之面積後，將重疊交集區域I1之面積除以網格M1之面積以得到相應於網格M1之交集面積比例。同樣地，針對網格M2，將重疊交集區域I2之面積除以網格M2之面積以得到相應於網格M2之交集面積比例，依此類推。In step S106, for each grid, the intersection area ratio of the area of the overlapping intersection region corresponding to each grid and the area of each grid can be calculated. For example, the area of the overlapping intersection region corresponding to each grid and the area of each grid are calculated, and the area of the overlapping intersection region corresponding to each grid is divided by the area of each grid to obtain the corresponding intersection area ratio. Please continue to refer to Figure 4, in the grid M1, the overlapping intersection area of the grid M1 and the corresponding copper paving area is I1. After calculating the area of the grid M1 and the area of the overlapping intersection region I1, the area of the overlapping intersection region I1 is divided by the area of the grid M1 to obtain the intersection area ratio corresponding to the grid M1. Similarly, for the grid M2, the area of the overlapping intersection region I2 is divided by the area of the grid M2 to obtain the intersection area ratio corresponding to the grid M2, and so on.
於步驟S108中，可依據交集面積比例設定每一網格之材料性質。當計算出對應於每一網格之重疊交集區域的面積與每一網格的面積之相應交集面積比例後，便可依據每一網格所對應之交集面積比例來設定每一網格之材料性質。其中每一網格之材料性質係有關於銅、塑膠、玻璃纖維板FR4 或上述之任意組合。例如，可利用Python程式軟體將每一網格與鋪銅的面積與對應之交集面積比例儲存下來，例如以試算表資料格式，如csv檔案，來儲存。ABAQUS分析軟體可透過設定腳本項目的執行以讀取前述存儲在試算表資料格式中的網格以及其對應之交集面積比例的資訊，並依照每個網格之交集面積占比來設定每個網格之材料性質。例如，請參考第5圖，第5圖為本發明實施例之電路佈局圖之各網格所對應的材料性質之實施例示意圖。網格M1、M2、M3具有不同之交集面積比例的情況。對應於網格M1之交集面積比例為R1，網格M1之材料性質設定為MP1。對應於網格M2之交集面積比例為R2，網格M2之材料性質設定為MP2。對應於網格M3之交集面積比例為R3，網格M3之材料性質設定為MP3。如此一來，便可依照各網格的交集面積占比來設定各別網格之材料性質。In step S108, the material properties of each grid can be set according to the intersection area ratio. After calculating the corresponding intersection area ratio of the area of the overlapping intersection region corresponding to each grid and the area of each grid, the material properties of each grid can be set according to the intersection area ratio corresponding to each grid. The material properties of each grid are related to copper, plastic, glass fiber board FR4 or any combination of the above. For example, the Python program software can be used to store the area of each grid and the copper paving and the corresponding intersection area ratio, for example, in a spreadsheet data format, such as a csv file. ABAQUS analysis software can read the information of the grids and their corresponding intersection area ratios stored in the spreadsheet data format by setting the execution of the script project, and set the material properties of each grid according to the intersection area ratio of each grid. For example, please refer to Figure 5, which is a schematic diagram of an embodiment of the material properties corresponding to each grid of the circuit layout diagram of the embodiment of the present invention. Grids M1, M2, and M3 have different intersection area ratios. Corresponding to the intersection area ratio of grid M1 is R1, the material property of grid M1 is set to MP1. Corresponding to the intersection area ratio of grid M2 is R2, the material property of grid M2 is set to MP2. The intersection area ratio of mesh M3 is R3, and the material property of mesh M3 is set to MP3. In this way, the material properties of each mesh can be set according to the intersection area ratio of each mesh.
簡言之，本發明實施例通過影像疊加運作取得並計算鋪銅區域與網格的面積交集占比並據以決定電路板之各網格區域的非均質材料性質，而能有效地提升電腦輔助工程的分析效率與準確性。再者，相較於傳統方式通常以一整塊的近似方式來設定，本發明實施例透過將電路佈局切成多個網格來進行各別網格的材料性質設定，將更能兼顧準確性。In short, the embodiment of the present invention obtains and calculates the area intersection ratio of the copper-plated area and the grid through image superposition operation and determines the heterogeneous material properties of each grid area of the circuit board accordingly, which can effectively improve the analysis efficiency and accuracy of computer-aided engineering. Furthermore, compared with the traditional method of usually setting in an approximate manner of a whole block, the embodiment of the present invention cuts the circuit layout into multiple grids to set the material properties of each grid, which will take into account more accuracy.
本領域具通常知識者當可依本發明的精神加以結合、修飾或變化以上所述的實施例，而不限於此。上述所有的陳述、步驟、及/或流程（包含建議步驟），可透過硬體、軟體、韌體（即硬體裝置與電腦指令的組合，硬體裝置中的資料為唯讀軟體資料）、電子系統、或上述裝置的組合等方式實現。硬體可包含類比、數位及混合電路（即微電路、微晶片或矽晶片）。例如，硬體可爲特定應用集成電路（ASIC）、現場可程序邏輯閘陣列（field programmable gate array，FPGA）、可程序化邏輯元件、耦接的硬體元件，或上述硬體的組合。在其他實施例中，硬件可包括通用處理器、微處理器、控制器、數字信號處理器（digital signal processor，DSP），或上述硬件的組合。軟體可爲程式碼的組合、指令的組合及／或函數（功能）的組合，其儲存在一儲存裝置中，例如一電腦可讀取記錄媒體或一非瞬時性電腦可讀取介質（non～transitory computer～readable medium）。舉例來說，電腦可讀取記錄媒體可包括唯讀記憶體（read～only memory，ROM）、快閃記憶體（Flash Memory）、隨機存取記憶體（random～access memory，RAM）、用戶識別模組（Subscriber Identity Module，SIM）、硬碟、軟碟或光碟唯讀記憶體（CD-ROM／DVD-ROM／BD-ROM），但不以此為限。本發明實施例可包括一電子裝置，電子裝置包括處理電路以及儲存裝置。本發明之流程步驟與實施例可被編譯成程式碼或指令的型態存在而儲存於所述電子裝置之儲存裝置中。所述電子裝置之處理電路可用於讀取與執行儲存裝置所儲存的程式碼或指令以實現前述所有步驟與功能。A person of ordinary skill in the art may combine, modify or change the above-described embodiments according to the spirit of the present invention, but is not limited thereto. All of the above statements, steps, and/or processes (including recommended steps) may be implemented through hardware, software, firmware (i.e., a combination of hardware devices and computer instructions, where the data in the hardware devices are read-only software data), electronic systems, or a combination of the above devices. The hardware may include analog, digital, and hybrid circuits (i.e., microcircuits, microchips, or silicon chips). For example, the hardware may be an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic element, a coupled hardware element, or a combination of the above hardware. In other embodiments, the hardware may include a general purpose processor, a microprocessor, a controller, a digital signal processor (DSP), or a combination of the above hardware. The software may be a combination of program codes, a combination of instructions, and/or a combination of functions, which are stored in a storage device, such as a computer-readable recording medium or a non-transitory computer-readable medium. For example, the computer-readable recording medium may include read-only memory (ROM), flash memory, random-access memory (RAM), subscriber identity module (SIM), hard disk, floppy disk or optical disk read-only memory (CD-ROM/DVD-ROM/BD-ROM), but is not limited thereto. The embodiment of the present invention may include an electronic device, the electronic device includes a processing circuit and a storage device. The process steps and embodiments of the present invention may be compiled into a program code or instruction form and stored in the storage device of the electronic device. The processing circuit of the electronic device can be used to read and execute the program code or instructions stored in the storage device to implement all the above steps and functions.
綜上所述， 本發明實施例通過影像疊加運作取得並計算鋪銅區域與網格的面積交集占比來據以決定電路板之各網格區域的非均質材料性質，而能有效地提升電腦輔助工程的分析效率與準確性。並且，相較於傳統方式通常以一整塊的近似方式來設定，本發明實施例透過將電路佈局切成多個網格來進行各別網格的材料性質設定，將更能兼顧準確性。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 In summary, the embodiment of the present invention obtains and calculates the area intersection ratio of the copper-plated area and the grid through image superposition operation to determine the inhomogeneous material properties of each grid area of the circuit board, which can effectively improve the analysis efficiency and accuracy of computer-aided engineering. Moreover, compared with the traditional method of usually setting in an approximate manner of a whole block, the embodiment of the present invention cuts the circuit layout into multiple grids to set the material properties of each grid, which will be more accurate. The above is only a preferred embodiment of the present invention. All equal changes and modifications made according to the scope of the patent application of the present invention should be covered by the present invention.
10:流程 20:電路佈局網格檔案 30:鋪銅區域佈局檔案 I1,I2:重疊交集區域 M1,M2,M3:網格 R1,R2,R3:交集面積比例 S100,S102,S104,S106,S108:步驟10: Process 20: Circuit layout grid file 30: Copper area layout file I1, I2: Overlapping intersection area M1, M2, M3: Grid R1, R2, R3: Intersection area ratio S100, S102, S104, S106, S108: Steps
第1圖為本發明實施例之一流程之示意圖。 第2圖為本發明實施例之一電路佈局網格檔案之示意圖。 第3圖為本發明實施例之一鋪銅區域佈局檔案之示意圖。 第4圖為本發明實施例之電路佈局網格檔案與鋪銅區域佈局檔案於影像疊加後的之實施例示意圖。 第5圖為本發明實施例之電路佈局圖中之各網格所對應的材料性質之實施例示意圖 Figure 1 is a schematic diagram of a process of an embodiment of the present invention. Figure 2 is a schematic diagram of a circuit layout grid file of an embodiment of the present invention. Figure 3 is a schematic diagram of a copper-plated area layout file of an embodiment of the present invention. Figure 4 is a schematic diagram of an embodiment of the circuit layout grid file and the copper-plated area layout file after image superposition of the embodiment of the present invention. Figure 5 is a schematic diagram of an embodiment of the material properties corresponding to each grid in the circuit layout diagram of the embodiment of the present invention
10:流程 10: Process
S100,S102,S104,S106,S108:步驟 S100, S102, S104, S106, S108: Steps
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| TW202312021A (en) * | 2021-09-14 | 2023-03-16 | 台達電子工業股份有限公司 | Automatic recognizing system and automatic recognizing method for a pick-up position of a printed circuit board |
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| TWI306567B (en) * | 2002-06-07 | 2009-02-21 | Cadence Design Systems Inc | Characterization and reduction of variation for integrated circuits |
| TW201205326A (en) * | 2010-07-29 | 2012-02-01 | Unimicron Technology Crop | Method for improving circuit pattern design and system using the method |
| TW201301073A (en) * | 2011-06-30 | 2013-01-01 | Hon Hai Prec Ind Co Ltd | System and method for inspecting power of a printed circuit board |
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