201205326 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種改良電路設計之方法及改良電路設計之系 統，特別是一種可降低產生賈凡尼腐蝕效應之改良電路設計之方 法及改良電路設計之系統。 【先前技術】 在選擇性化錄金之印刷電路板之表面被防焊材料所曝露出的 • 圖案化線路中，部分線路圖案使用覆有鎳金材料的金屬表面抗氧 化處理’其餘非鎳金區域為使用有機保護膜(〇rganic s〇lder Preservative, OSP) ° 賈凡尼效應(Galvanic Effect)或賈凡尼腐蝕(Galvanic Corrosion) 係指具有不同氧化電位的金屬在電解液(譬如酸性蝕刻溶液或具有 氧化還原能力的化學溶液)中，會有電位差而產生電化學反應，其 中由氧化電位高的(如鋅、鐵等)形成陽極，氧化電位低的作為陰 極，而陽極在電化學反應時，會形成離子而溶於電解液中，因此 ® 陽極金屬會逐漸被腐钱。 因此，當印刷電路板進行各種化學處理時，裸露導線為金屬 銅為陽極’鑛金層為陰極，銅面將因賈凡尼效應產生腐#，裸露 之導線將會逐漸變細，最後可能會產生線斷(trace〇pen)之缺失，或 者裸露之銅面接墊，其尺寸將會逐漸變小，最後可能會腐蝕過度 (overetching) ’甚至產生接墊不見之缺失。 目前關於印刷電路板之線路設計係採下列流程：取得客戶工 程資料；製前之客戶工程資料讀取與轉譯；輸出生產治具及底片； 201205326 實際生產及驗證；經劣化實驗後，取得實際位置雜；進行製前 之客戶工程資料修正；以及生產治具及底片。然而此流程具有下 列缺點：1.無法第-咖刪會發生賈凡尼效應之位置，須經劣化 實驗後’才能得知發生賈凡尼效應之正確位置，影響良率及出貨 速度；及2.浪費相關的生產治具的製作費用。 因此，有必要提供-觀良電路設計之方法及改良電路設計 之系統，以改善上述所存在的問題。 【發明内容】 本發明之主要目的係在提供—種可增域率及降低製作成本 之改良電路設計之方法及改良電路設計之系統。 為達成上述之目的，本發明之改良電路設計之方法包括下列 步驟：接受客戶工程資料；分析客戶卫崎料域得至少一金/非 金之面積比值；根據儲存在資料庫之相對關係資料及至少一金/非 金之面積比值，提供至少—修正對策；根據修正職， 工程資料。 〆 在本發明之一實施例中，在根據修正對策，修改客戶工程資 料之步驟後’更包括下列步驟：接受_資料並儲存 資料庫’其中回饋資料包括對修正對策之修正。 為達成上述之目的，本發明之改良電路設計之系統包括接受 =組、分析模組、資料庫、建議模組、修正模組及回饋模电。其 =接受客戶卫_料。分析模組用以分析客戶工程 資枓並獲付至少-金/非金之面積比值。資料庫包括至少—金/非金 產生賈凡尼效應之相對關係資料。建議模組用以根 =貝枓庫及至少-金/非金之面積比值，提供客戶工程資料至少一 U正對策。修正模組用以根據至少一修正對策對客戶卫程資料進 201205326 資料庫， :修正。回細_以接受回饋資料並儲細饋資料至 其中回饋資料包括對修正對策之修正。 【實施方式】 下文翻之上述和其他目的、繼和優離更_易懂， 文特舉出較佳實酬’並配合所關式，作詳細說明如下。 以下請先參考圖1關於依據本發明之一實施例的改 汁之系統的架構示意圖。 。又201205326 VI. Description of the Invention: [Technical Field] The present invention relates to a method for improving circuit design and a system for improving circuit design, and more particularly to an improved circuit design method and improved circuit capable of reducing the effect of Giovanni corrosion Design system. [Prior Art] In the patterned circuit in which the surface of the selectively printed gold printed circuit board is exposed by the solder resist material, part of the line pattern is treated with a metal surface coated with a nickel-gold material to prevent oxidation. The region uses an organic protective film (〇rganic s〇lder Preservative, OSP) ° Galvanic Effect or Galvanic Corrosion refers to a metal with different oxidation potentials in an electrolyte (such as an acidic etching solution) Or a chemical solution having a redox capability, an electrochemical reaction occurs in which a potential difference is formed, wherein an anode is formed by a high oxidation potential (such as zinc, iron, etc.), a cathode having a low oxidation potential is used as a cathode, and an anode is in an electrochemical reaction. It will form ions and dissolve in the electrolyte, so the ® anode metal will gradually be rotted. Therefore, when the printed circuit board is subjected to various chemical treatments, the bare conductor is made of metal copper as the anode, and the gold layer is the cathode. The copper surface will be rotted by the Jaffan effect. The exposed wire will be tapered, and finally may be The lack of traces, or bare copper pads, will gradually become smaller and may overetching 'even the missing pads. At present, the circuit design of printed circuit boards adopts the following processes: obtaining customer engineering materials; reading and translating customer engineering data before production; outputting production fixtures and negative films; 201205326 Actual production and verification; after degrading experiments, obtaining actual positions Miscellaneous; correction of customer engineering data before the system; and production of fixtures and negatives. However, this process has the following disadvantages: 1. The position of the Jaffany effect can not occur in the first and the second, and the correct position of the Giovanni effect must be known after the deterioration experiment, which affects the yield and the speed of shipment; 2. Waste the production costs of the relevant production fixtures. Therefore, it is necessary to provide a method of designing a circuit and a system for improving circuit design to improve the above problems. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for improving circuit design and a system for improving circuit design that can increase the domain rate and reduce the manufacturing cost. In order to achieve the above object, the improved circuit design method of the present invention comprises the steps of: accepting customer engineering data; analyzing at least one gold/non-gold area ratio of the customer Weiqi material domain; and according to the relative relationship data stored in the database and At least one gold/non-gold area ratio provides at least—corrective countermeasures; according to the revised job, engineering data. In an embodiment of the present invention, after the step of modifying the customer engineering materials according to the correction countermeasures, the method further includes the steps of: accepting the data and storing the database, wherein the feedback data includes the correction of the correction countermeasure. To achieve the above objectives, the improved circuit design system of the present invention includes a acceptance group, an analysis module, a database, a suggestion module, a correction module, and a feedback mode. It = accept customer service. The analysis module is used to analyze customer engineering assets and receive at least a gold/non-gold area ratio. The database includes at least - gold/non-gold data on the relative relationship of the Giovanni effect. It is recommended that the module be used to provide at least one positive response to customer engineering data using the area ratio of root = shellfish and at least - gold/non-gold. The correction module is used to enter the customer service data according to at least one correction strategy 201205326 database, : correction. Back to the _ to accept the feedback data and store the fine feedback data to which the feedback data includes corrections to the correction countermeasures. [Embodiment] The following is a description of the above and other purposes, and the following is an easy-to-understand, and the article gives a better remuneration, and the details are as follows. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to Figure 1, a schematic diagram of the architecture of a system for modifying a juice in accordance with an embodiment of the present invention is provided. . also
1所心本發明之改良電路設計之系統丨包括接受模组 、为析模組12、資料庫13、建議模組14、修正模組15及回饋 模組16。其中接受模組11用以接受客戶工程資料21。在本發明 之-實施财，客戶工程龍21係Gefe _(正式 洲’ Gerber Data係印刷電路板產業常見使用的工程圖轉標格 式，包括各導電線路層、防焊層、文字層、成型(外型尺寸^面 處理(例如鎳金表面位置)的圖檔資料，(通常 測試點）、組抗線示意圖及孔位資料等。 、]忒的 分析模組12用以分析客戶工程資料21並獲得至少一金/非金 之面積比值。在本發明之-實施例中，金/非金之面積比值包括金/ 銅之面積比值或鎳金/銅之面積比值，但本發明不以此為限。在本 發明之-實施例中，分析模組12將客戶工程㈣21依各層次讀 取轉標後，讀取外層線路圖案、孔位、鎳金表面處理位置，並依 不同的聯通網路加以分類，並計算同一聯通網路上的金/非金之面 積比值。 資料庫13包括至少一金/非金之面積比值與產生賈凡尼效應 之相對關係資料。建議模組14用以根據資料庫13及至少一金/非 金之面積比值，提供客戶工程資料21至少一修正對策。修正模組 5 201205326 15用以根據至少-修正對策對客戶工程資料2 組16用以接受回饋資料24並儲存“;回= 回饋資料24包括對修正職之修^讀至讀庫A其中 在本發明之一實施例中，上述各個模 置、軟體程式、韌體哎其細人冰< . j配置為硬體裝 之型式配置。餘卿㈣’亦可以結合 接著請參考圖2 _本判之改㈣路設計 程圖。此處需注意的是，以下雖以圖！所示之改良電路 統1為例朗本發明之改㈣路設狀找，、 不以應用改良電路設計之系統1為限。 3之方法並 :圖2所示，本發明首先進行步驟奶：接受客戶工程資料。 關於接受模組U用以接受客戶工程資料2 上述實施例說明，故不在此贅述。 属万式已在 之面行步驟Μ :分析客戶碎資料並獲得至少一金/非金 關於分析模IE 12用以分析客戶工程資料21並獲得至少一金/ 非金之面積比值之實施方式6在上述實施舰明，故*在此資述。 接著進行步驟S73 :提供至少一修正對策。 建議模組14用以根據資料庫13及至少一金/非金之面精 值’提供客戶工程資料21至少-修正對策；其中修正對策係舞 ίΐί之面積比值之不同’提供客戶工程資料21各種相對脑 乜或修正對策。 ’ 在本發明之-實施例中，當金/非金之面積比值係實質上介於 10至40時，修正對策包括增加非金面積，但本發明不以此範圍為 限；在本發敗-雛實_巾，金/非金之面_值係實質上介 6 201205326 之間。在本發明之—實施射，增加非金面積包括增 加導線線寬、增加接塾面積、增加線路轉角面積或接點圖形等， 但本發明不以此為.限。 在本發明之一實施例中，當金/非金之面積比值係實質上介高 於40時’修正對策包括設置引誘性圖案但本發明不以此數值為 ^在本發明之-較佳實施例中，金/非金之面積比值係實質上介 门；〇弓I誘f生圖案之形狀尺寸並不設限，且引誘性圖案之材質 係實質上為金屬銅，但本發明不以此為限。 •、如圖3所示，在本發明之一實施例中，客戶工程資料21包括 導電線路層3〇a，須注意的是，為方便說明，圖3之導電線路層 3〇a係簡化後之示意圖，導電線路層3〇a可為單層或多層組合之同 二導電性之導電祕層，另祖意的是，圖3巾之虛細未標號) 代表的疋防焊絕緣層(圖未示)之開口位置，部份之導電線路層咖 實際上係被防焊絕緣層所覆蓋。導電線路層池包括金面犯及 複數銅面32a，其中銅面32a係指焊墊，但本發明不以此為限。當 導電線路層30a係串聯網路時，則引誘性圖案3如係設置在離金 • 面3U最遠之銅® 32a之位置；此因印刷電路板在酸性姓刻溶液 或具有氧化還原能力的化學溶液中，且導電線路層3Ga係串聯網 路時’離金面3la最遠之銅自孤氧化(即失去電子)的情形最為嚴 重，故在離金面31a最遠之銅面32a設置引誘性圖案33a，使引誘 $圖案33a因氧化而失去的電子可與銅離子還原在離金面31&最 遠之銅面32a ’以降低賈凡尼效應。 如圖4所示，在本發明之另一實施例中，客戶工程資料21 包括導電線路層30b ’須注意的是，為方便說明，圖4之導電線路 層30b係簡化後之示意圖，導電線路層3〇b可為單層或多層組合 之同一導電性之導電線路層，另須注意的是，圖4中之虛線(圖未 201205326 標號)代表的是防焊絕緣層（圖未示)之開口位置，部份之導電線路 層30b實際上係被防焊絕緣層所覆蓋。導電線路層3%包括金面 31b及複數銅® 32b，其中銅面32b係指焊塾，但本發明不以此為 限。當導電線路層30b係並聯網路時，則引誘性圖案观係設置 在離金面3ib最近之細32b之位置；此因印刷電路板在酸性钱 刻溶液或具有氧化還原能力的化學溶液中，且導電線路層观係 並聯網路時’各銅面32a氧化情形較為平均，故在離金面训最 近之銅面32b旁，或者直接與金面训位置，設置具導通連接的 引誘性圖案33b，以降低賈凡尼效應。 須注意的是，在本發明之另一實施例中，線路圖案不論是串 聯網路、並聯網路或是串、並聯混合網路，引誘性圖雜可皆交 置在金面之旁邊(圖未示）’以降低賈凡尼效應。 & 接著進行步驟S74 :修改客戶工程資料。 在本發明之-實施例中，修正模組15根據相對應之修正對 對Ϊ戶工輯料21進行修正’針對客戶玉程資料21中，可能產 生賈凡尼效應之位置進行補償或修正。 b 如圖1所示’在本發明之一實施例中，經修正後之客戶工 資料21先經生產治具及底片22之製程，其中生產治具及 之製程係指實際生產印刷電路板所需之祕、底片以製作印刷 路板。接著進行生產驗證23之製程，生產驗證23之製程 刷電$板經過劣化測試後，再經工程師檢測印刷電路板是否失 效。若無失效，則可繼續進行生產。 最後進行辣S75:較_㈣並齡_資料至資料庫。 路板實施例中，若經生產驗證23之製程後，印刷電 路板係失效，則玉程_對修正對策進行修正並產生 24 ’回麵a I6肋較㈤饋:雜24並财_雜24至資料 201205326 庫13，用以做為下次客戶工程資料21之修正用。在本發明之 =:(圖效’工程師亦可將此結果形成回饋資料並儲存至The system of the improved circuit design of the present invention comprises an acceptance module, an analysis module 12, a database 13, a suggestion module 14, a correction module 15, and a feedback module 16. The acceptance module 11 is configured to accept the customer engineering data 21. In the invention - implementation of the financial, customer engineering Dragon 21 Gefe _ (formal continent ' Gerber Data printing circuit board industry commonly used engineering drawing conversion format, including each conductive circuit layer, solder mask, text layer, molding ( Profile size data (such as nickel gold surface position) image data, (usual test points), group resistance line diagram and hole position data, etc., 忒 analysis module 12 is used to analyze customer engineering data 21 Obtaining at least one gold/non-gold area ratio. In the embodiment of the present invention, the gold/non-gold area ratio includes a gold/copper area ratio or a nickel gold/copper area ratio, but the present invention does not In the embodiment of the present invention, the analysis module 12 reads the external circuit pattern, the hole position, the nickel gold surface treatment position, and the different connected network according to the customer engineering (4) 21 after reading the transfer standard according to each level. Classify and calculate the gold/non-gold area ratio on the same Unicom network. The database 13 includes at least one gold/non-gold area ratio and the relative relationship of the Giovanni effect. The proposed module 14 is used to Library 13 and at least one / Non-Gold area ratio, providing at least one corrective action for customer engineering data 21. Correction module 5 201205326 15 is used to accept feedback data 24 for customer engineering data group 2 according to at least - correction countermeasures and store "; back = feedback The data 24 includes a revision to the revision library. In one embodiment of the present invention, each of the above-mentioned modules, software programs, firmware, and fine ice is configured as a hard device. Configuration. Yu Qing (4)' can also be combined with the reference to Figure 2 _ This sentence is changed (4) Road design plan. It should be noted here that the following is an example of the improved circuit system 1 shown in Figure! Change (4) road configuration, not limited to the application of improved circuit design system 1. 3 method and: As shown in Figure 2, the invention first steps milk: accept customer engineering data. About accept module U for acceptance Customer Engineering Information 2 The above examples are described, so they are not described here. The genre has been in the process of Μ: analyzing the customer's broken data and obtaining at least one gold/non-gold analysis module IE 12 for analyzing customer engineering data 21 Get at least one gold / non Embodiment 6 of the area ratio is implemented in the above-mentioned implementation, so * is hereby. Next, step S73 is performed: at least one correction countermeasure is provided. The suggestion module 14 is configured to use the database 13 and at least one gold/non-gold surface. The fine value 'provides the customer engineering data 21 at least - the correction countermeasure; wherein the correction countermeasure is the difference in the area ratio of the dance ' ΐ ' 'providing the customer engineering data 21 various relative cerebral palsy or correction countermeasures. ' In the present invention - in the embodiment, when the gold The area ratio of non-gold is substantially between 10 and 40, and the corrective measures include increasing the non-gold area, but the present invention is not limited to this range; in the present defeat - the young _ towel, gold / non-gold noodles The value of _ is essentially between 201205326. In the practice of the present invention, increasing the non-gold area includes increasing the wire width, increasing the joint area, increasing the line corner area or the contact pattern, etc., but the invention is not limited thereto. In an embodiment of the present invention, when the area ratio of gold/non-gold is substantially higher than 40, the correction countermeasure includes setting the attracting pattern, but the present invention does not use this value as the preferred embodiment of the present invention. In the example, the ratio of the area of the gold/non-gold is substantially the same; the shape of the pattern of the 〇 I I 并不 生 生 生 生 生 生 生 , , , , , , , , , , , , , , , , , , , , , , , , Limited. As shown in FIG. 3, in an embodiment of the present invention, the customer engineering data 21 includes a conductive circuit layer 3〇a. It should be noted that, for convenience of explanation, the conductive circuit layer 3〇a of FIG. 3 is simplified. The schematic diagram, the conductive circuit layer 3〇a can be a single layer or a plurality of layers of the same two conductive conductive layer, and the other is the 疋 soldering insulation layer represented by the thin and unlabeled figure of FIG. The position of the opening, not shown, is partially covered by a solder resist layer. The conductive circuit layer pool includes a gold surface and a plurality of copper faces 32a, wherein the copper surface 32a is a solder pad, but the invention is not limited thereto. When the conductive circuit layer 30a is connected in series, the attracting pattern 3 is disposed at the position of the copper® 32a farthest from the gold surface 3U; this is because the printed circuit board is in an acidic solution or has redox capability. In the chemical solution, when the conductive circuit layer 3Ga is connected in series, the copper is the most distant from the gold surface 3la, and the copper is the most severe. Therefore, the copper surface 32a farthest from the gold surface 31a is set to lure. The pattern 33a causes the electrons lost by the entanglement of the pattern 33a due to oxidation to be reduced with copper ions at the farthest copper surface 32a' from the gold surface 31 & to reduce the Giovanni effect. As shown in FIG. 4, in another embodiment of the present invention, the customer engineering data 21 includes the conductive circuit layer 30b. It should be noted that, for convenience of explanation, the conductive circuit layer 30b of FIG. 4 is a simplified schematic diagram, and the conductive circuit The layer 3〇b may be a single-layer or multi-layer combination of the same conductive conductive circuit layer. It should also be noted that the dashed line in FIG. 4 (not labeled 201205326) represents a solder resist insulating layer (not shown). In the open position, part of the conductive wiring layer 30b is actually covered by the solder resist insulating layer. The conductive circuit layer 3% includes a gold surface 31b and a plurality of copper layers 32b, wherein the copper surface 32b refers to a solder bump, but the invention is not limited thereto. When the conductive circuit layer 30b is connected in parallel, the attractive pattern is disposed at a position closest to the thin 32b of the gold surface 3ib; because the printed circuit board is in an acidic solution or a chemical solution having redox capability, When the conductive circuit layer is connected to the parallel network, the oxidation of each copper surface 32a is relatively even. Therefore, an attractive pattern 33b with a conductive connection is provided next to the copper surface 32b closest to the gold surface training, or directly to the gold surface training position. To reduce the Giovanni effect. It should be noted that in another embodiment of the present invention, whether the line pattern is a serial network, a parallel network, or a serial or parallel hybrid network, the lure maps are all placed next to the gold surface (Fig. Not shown) to reduce the Giovanni effect. & Next, proceed to step S74: modify the customer engineering data. In the embodiment of the present invention, the correction module 15 corrects the accountant's material 21 according to the corresponding correction. The compensation or correction of the location of the Jaffany effect may be made in the customer profile data 21. b. As shown in FIG. 1 , in an embodiment of the present invention, the modified customer data 21 is first processed by the production jig and the negative film 22, wherein the production jig and the process refer to the actual production of the printed circuit board. The secrets and negatives are needed to make printed road boards. Then, the process of production verification 23 is carried out, and the process of production verification 23 is subjected to the deterioration test, and then the engineer checks whether the printed circuit board is invalid. If there is no failure, the production can continue. Finally, the spicy S75: _ (four) and _ data to the database. In the embodiment of the road plate, if the printed circuit board fails after the production verification process 23, the jade _ corrects the correction countermeasure and generates 24 'back surface a I6 rib compared with (5) feed: miscellaneous 24 and wealth _ miscellaneous 24 To the data 201205326 library 13, used as a correction for the next customer project data 21. In the present invention =: (Figure effect engineers can also form feedback data and store it to
藉由本發明之改良電路設計之方法及改良電路設計之系統， 除:解決先前技術所存在關，並具有以下優點·丨.改良電 又十之系統1可在生產治具及底片22之製程前提供修正對策， 可增加良率；2·因良率提升，故可降低生產成本及增加ib貨速率； 及3.回饋-貝料24持續儲存至資料庫ls，增加日後建議模組14 對客戶工程資料21提供修正對策之準確性。 。綜上所陳，本發明無論就目的、手段及功效，在在均顯示其 避異於S知技術之特徵，懇請貴審查委員明察，早曰賜准專利， 俾嘉惠社會’實感德便。惟餘意的是’上述諸多實施例僅係為 了，於說明而舉例而已，本發明所主張之權利範圍自應以申請專 利範圍所述為準’而非僅限於上述實施例。 201205326 【圖式簡單說明】 圖1關於本發明之改良電路設計之系統之一實施例之架構示意圖。 圖2關於本發明之改良電路設計之方法之一實施例之步驟流程圖。 圖3關於本發明於串聯網路設置引誘性圖案之一實施例之示意圖。 圖4關於本發明於並聯網路設置引誘性圖案之—實施例之示意圖。 【主要元件符號說明】 改良電路設計之系統1 接受模組11 分析模組12 資料庫13 建議模組14 回饋模組16 客戶工程資料21 生產治具及底片22 驗證23 回饋資料24 導電線路層30a、30b 金面 31a、31b 鋼面 32a、32b 引誘性圖案33a、33bThe improved circuit design method and the improved circuit design system of the present invention, in addition to: solving the prior art, have the following advantages. The improved system 10 can be used before the process of producing the jig and the film 22 Provide corrective measures to increase yield; 2) Reduce production costs and increase ib cargo rate due to improved yield; and 3. Reward-bee feed 24 continues to be stored in database ls, adding future recommended modules 14 to customers The engineering data 21 provides the accuracy of the corrective measures. . In summary, the present invention, regardless of its purpose, means and efficacy, shows its characteristics of avoiding the S-knowledge technology, and asks the reviewing committee to inspect the patent, and to give the company a real sense of virtue. It is to be understood that the various embodiments described above are intended to be illustrative only, and the scope of the invention is intended to be 201205326 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an embodiment of a system for improving circuit design of the present invention. 2 is a flow chart showing the steps of an embodiment of a method for improving circuit design of the present invention. Figure 3 is a schematic illustration of one embodiment of the present invention for providing an attractive pattern in a series network. Figure 4 is a schematic illustration of an embodiment of the present invention in which an attractive pattern is placed in a parallel network. [Main component symbol description] Improved circuit design system 1 Acceptance module 11 Analysis module 12 Database 13 Suggestion module 14 Feedback module 16 Customer engineering data 21 Production fixture and film 22 Verification 23 Feedback data 24 Conductive circuit layer 30a , 30b gold surface 31a, 31b steel surface 32a, 32b attracting patterns 33a, 33b