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TWI847771B - AMOLED pixel compensation circuit, OLED display device and information processing device - Google Patents

AMOLED pixel compensation circuit, OLED display device and information processing device Download PDF

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TWI847771B
TWI847771B TW112123258A TW112123258A TWI847771B TW I847771 B TWI847771 B TW I847771B TW 112123258 A TW112123258 A TW 112123258A TW 112123258 A TW112123258 A TW 112123258A TW I847771 B TWI847771 B TW I847771B
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voltage
pmos transistor
switch
storage capacitor
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TW202501449A (en
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高雪岭
譚仲齊
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大陸商北京歐錸德微電子技術有限公司
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Abstract

一種AMOLED像素補償電路,具有一開關電路、一PMOS電晶體、一儲存電容及一OLED元件,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,該開關操作程序包括:以一第一直流電壓設定該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓;以一第二直流電壓設定該PMOS電晶體之源極電壓使該PMOS電晶體之該閘極電壓和該源極電壓的差等於(該第一直流電壓-該第二直流電壓);使該PMOS電晶體與該儲存電容串聯於一資料電壓與一直流供應電壓之間以使該儲存電容儲存的電壓為該直流供應電壓與(該資料電壓與該PMOS電晶體之閾值電壓之和)之差;以及使該儲存電容的兩端分別耦接該PMOS電晶體的該閘極和該源極而產生該驅動電流。An AMOLED pixel compensation circuit has a switch circuit, a PMOS transistor, a storage capacitor and an OLED element. The switch circuit is used to execute a switch operation procedure to drive the PMOS transistor to generate a driving current so that the OLED element generates a brightness. The switch operation procedure includes: setting the gate voltage of the PMOS transistor and the anode voltage of the OLED element with a first DC voltage; setting the source voltage of the PMOS transistor with a second DC voltage; The voltage makes the difference between the gate voltage and the source voltage of the PMOS transistor equal to (the first DC voltage-the second DC voltage); the PMOS transistor and the storage capacitor are connected in series between a data voltage and a DC supply voltage so that the voltage stored in the storage capacitor is the difference between the DC supply voltage and (the sum of the data voltage and the threshold voltage of the PMOS transistor); and the two ends of the storage capacitor are respectively coupled to the gate and the source of the PMOS transistor to generate the driving current.

Description

AMOLED像素補償電路、OLED顯示裝置及資訊處理裝置AMOLED pixel compensation circuit, OLED display device and information processing device

本發明係有關積體電路領域,尤指一種AMOLED像素補償電路。The present invention relates to the field of integrated circuits, and more particularly to an AMOLED pixel compensation circuit.

一般AMOLED(active mode organic light emitting diode;主動模式有機發光二極體)顯示模組之各像素係由一像素電路構成,該像素電路包括一OLED單元及用以產生一驅動電流以驅動該OLED(organic light emitting diode;有機發光二極體)單元之一電晶體電路,該電晶體電路一般包含多個電晶體及一個儲存電容,例如7T1C(七個PMOS電晶體及一個儲存電容)架構,且係依該儲存電容所儲存的顯示資料電壓產生一定電流,及依一脈衝調變信號控制該定電流的輸出時間以決定該驅動電流的等效值,從而驅使該OLED單元呈現一預定亮度。Each pixel of a general AMOLED (active mode organic light emitting diode) display module is composed of a pixel circuit, which includes an OLED unit and a transistor circuit for generating a driving current to drive the OLED (organic light emitting diode) unit. The transistor circuit generally includes a plurality of transistors and a storage capacitor, such as a 7T1C (seven PMOS transistors and a storage capacitor) structure, and generates a certain current according to the display data voltage stored in the storage capacitor, and controls the output time of the certain current according to a pulse modulation signal to determine the equivalent value of the driving current, thereby driving the OLED unit to present a predetermined brightness.

然而,由於製程存在變異,該些像素電路中的電晶體會有閾值電壓不均勻的情形,導致各像素之顯示亮度不均而使顯示畫面有Mura(殘痕)現象。However, due to process variations, the transistors in the pixel circuits may have uneven threshold voltages, resulting in uneven display brightness of each pixel and causing Mura (mura) on the display screen.

另外,為增加行動裝置的續航力,當其顯示的畫面為靜態畫面時,一般的AMOLED顯示模組會降低顯示掃描刷新率以節省功耗。然而,當顯示掃描刷新率降低時,該電晶體電路中的電晶體漏電流卻會讓該儲存電容的儲存電壓下降,從而影響該OLED單元的顯示亮度。In addition, to increase the battery life of mobile devices, when the displayed image is a static image, the general AMOLED display module will reduce the display scan refresh rate to save power. However, when the display scan refresh rate is reduced, the transistor leakage current in the transistor circuit will cause the storage voltage of the storage capacitor to drop, thereby affecting the display brightness of the OLED unit.

為解決上述問題,本領域亟需一種新穎的 AMOLED像素補償電路架構。To solve the above problems, a novel AMOLED pixel compensation circuit architecture is urgently needed in the art.

本發明之一目的在於提供一種AMOLED像素補償電路,其可在顯示一幀畫面的過程中先快速均一化各OLED像素的電流源電晶體的源-閘極電壓,從而極小化電流源電晶體之源-閘極寄生電容之遲滯電壓對顯示畫面所造成的短期殘影。One purpose of the present invention is to provide an AMOLED pixel compensation circuit, which can quickly equalize the source-gate voltage of the current source transistor of each OLED pixel in the process of displaying a frame, thereby minimizing the short-term afterimage caused by the hysteresis voltage of the source-gate parasitic capacitance of the current source transistor on the display image.

本發明之另一目的在於提供一種AMOLED像素補償電路,其可補償電流源電晶體之閾值電壓以極小化因製程偏差及供應電壓的電壓降所帶來的顯示不均及Mura現象。Another object of the present invention is to provide an AMOLED pixel compensation circuit that can compensate the threshold voltage of a current source transistor to minimize display unevenness and Mura caused by process deviation and voltage drop of a supply voltage.

本發明之另一目的在於揭露一種AMOLED像素補償電路,其可延長儲存電容的電壓保持時間以支持低畫面刷新率。Another object of the present invention is to disclose an AMOLED pixel compensation circuit that can extend the voltage holding time of a storage capacitor to support a low screen refresh rate.

本發明之另一目的在於揭露一種OLED顯示裝置,其可藉由前述的AMOLED像素補償電路極小化顯示畫面的短期殘影。Another object of the present invention is to disclose an OLED display device which can minimize the short-term afterimage of the display screen by using the aforementioned AMOLED pixel compensation circuit.

本發明之另一目的在於揭露一種OLED顯示裝置,其可藉由前述的AMOLED像素補償電路極小化因製程偏差及供應電壓的電壓降所帶來的顯示不均及Mura現象,以及延長儲存電容的電壓保持時間以支持低畫面刷新率。Another object of the present invention is to disclose an OLED display device, which can minimize display unevenness and Mura caused by process deviation and voltage drop of supply voltage through the aforementioned AMOLED pixel compensation circuit, and prolong the voltage holding time of the storage capacitor to support a low screen refresh rate.

本發明之又一目的在於揭露一種資訊處理裝置,其可藉由前述的AMOLED像素補償電路優化顯示效果及支持低畫面刷新率。Another object of the present invention is to disclose an information processing device that can optimize display effects and support low picture refresh rates by using the aforementioned AMOLED pixel compensation circuit.

為達到前述目的,一種AMOLED像素補償電路乃被提出,其具有一開關電路、一PMOS電晶體、一儲存電容及一OLED元件,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,該開關操作程序包括: 一第一階段:以一第一直流電壓設定該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓; 一第二階段:以一第二直流電壓設定該PMOS電晶體之源極電壓使該PMOS電晶體之該閘極電壓和該源極電壓的差等於(該第一直流電壓-該第二直流電壓); 一第三階段:使該PMOS電晶體與該儲存電容串聯於一資料電壓與一直流供應電壓之間以使該儲存電容儲存的電壓為該直流供應電壓與(該資料電壓與該PMOS電晶體之閾值電壓之和)之差;以及 一第四階段:使該儲存電容的兩端分別耦接該PMOS電晶體的該閘極和該源極而產生該驅動電流。 To achieve the above-mentioned purpose, an AMOLED pixel compensation circuit is proposed, which has a switching circuit, a PMOS transistor, a storage capacitor and an OLED element. The switching circuit is used to execute a switching operation procedure to drive the PMOS transistor to generate a driving current so that the OLED element generates a brightness. The switching operation procedure includes: A first stage: setting the gate voltage of the PMOS transistor and the anode voltage of the OLED element with a first DC voltage; A second stage: setting the source voltage of the PMOS transistor with a second DC voltage so that the difference between the gate voltage and the source voltage of the PMOS transistor is equal to (the first DC voltage-the second DC voltage); A third stage: connecting the PMOS transistor and the storage capacitor in series between a data voltage and a DC supply voltage so that the voltage stored in the storage capacitor is the difference between the DC supply voltage and (the sum of the data voltage and the threshold voltage of the PMOS transistor); and A fourth stage: coupling the two ends of the storage capacitor to the gate and the source of the PMOS transistor respectively to generate the driving current.

在一實施例中,該開關電路和該PMOS電晶體係由低温多晶氧化物製程製造而成。In one embodiment, the switch circuit and the PMOS transistor are fabricated using a low temperature polycrystalline oxide process.

在一實施例中,該開關電路中之任一電晶體係由PMOS電晶體、NMOS電晶體和CMOS電晶體所組成群組所選擇的一種電晶體。In one embodiment, any transistor in the switch circuit is a transistor selected from the group consisting of PMOS transistors, NMOS transistors and CMOS transistors.

為達到前述目的,本發明進一步提出一種OLED顯示裝置,其具有一AMOLED面板,該AMOLED面板具有如前述之AMOLED像素補償電路。To achieve the aforementioned object, the present invention further provides an OLED display device having an AMOLED panel. The AMOLED panel has the AMOLED pixel compensation circuit as described above.

為達到前述目的,本發明進一步提出一種資訊處理裝置,其具有一中央處理單元及如前述之OLED顯示裝置,該中央處理單元係用以與該OLED顯示裝置通信。To achieve the aforementioned object, the present invention further provides an information processing device having a central processing unit and the aforementioned OLED display device, wherein the central processing unit is used to communicate with the OLED display device.

在可能的實施例中,所述之資訊處理裝置可為一攜帶型電腦、一智慧型手機或一車用電腦。In possible embodiments, the information processing device may be a portable computer, a smart phone or a car computer.

為使  貴審查委員能進一步瞭解本創作之結構、特徵、目的、與其優點,茲附以圖式及較佳具體實施例之詳細說明如後。In order to enable the review committee to further understand the structure, features, purpose, and advantages of this creation, the following are attached with diagrams and detailed descriptions of the preferred specific implementation examples.

本發明的原理在於:The principle of the present invention is:

(一)利用一開關電路在顯示一幀畫面的初始化期間均一化各OLED像素的電流源電晶體的源-閘極電壓以極小化各電流源電晶體之源-閘極寄生電容之遲滯電壓的差異,從而有效降低顯示畫面的短期殘影現象;(i) using a switch circuit to uniformize the source-gate voltage of the current source transistor of each OLED pixel during the initialization period of displaying a frame of picture to minimize the difference in the hysteresis voltage of the source-gate parasitic capacitance of each current source transistor, thereby effectively reducing the short-term afterimage phenomenon of the displayed picture;

(二)利用該開關電路採集包含一正供應電壓、一資料電壓及一電流源電晶體之閾值電壓之一線性組合電壓,並將該線性組合電壓預存在一儲存電容上;(ii) using the switch circuit to collect a linear combination voltage including a positive supply voltage, a data voltage and a threshold voltage of a current source transistor, and pre-storing the linear combination voltage in a storage capacitor;

(三)利用該開關電路驅使該儲存電容的電壓驅動該電流源電晶體以產生與所述閾值電壓無關之一驅動電流;以及(iii) using the switch circuit to drive the voltage of the storage capacitor to drive the current source transistor to generate a driving current that is independent of the threshold voltage; and

(四)利用氧化物半導體製程製造之開關電路提供低漏電流以延長該儲存電容的電壓保持時間。(iv) A switching circuit manufactured using an oxide semiconductor process provides low leakage current to extend the voltage retention time of the storage capacitor.

依此,本發明即可有效降低顯示畫面的短期殘影現象、極小化閾值電壓對驅動電流的影響以優化OLED面板的顯示效果,且可支持低畫面刷新率。Accordingly, the present invention can effectively reduce the short-term afterimage phenomenon of the display screen, minimize the influence of the threshold voltage on the driving current to optimize the display effect of the OLED panel, and support a low screen refresh rate.

請參照圖1,其繪示本發明之AMOLED像素補償電路之一實施例之電路圖。如圖1所示,一AMOLED像素補償電路100具有一第一開關111、一第二開關112、一第三開關113、一第四開關114、一第五開關115、一PMOS電晶體120、一第一導通時間調變開關121、一第二導通時間調變開關122、一儲存電容130以及一OLED元件140,其中,PMOS電晶體120和該些開關可由LTPO(low temperature polycrystalline oxide;低温多晶氧化物)製程製造而成。Please refer to FIG. 1, which shows a circuit diagram of an embodiment of the AMOLED pixel compensation circuit of the present invention. As shown in FIG. 1, an AMOLED pixel compensation circuit 100 has a first switch 111, a second switch 112, a third switch 113, a fourth switch 114, a fifth switch 115, a PMOS transistor 120, a first on-time modulation switch 121, a second on-time modulation switch 122, a storage capacitor 130 and an OLED element 140, wherein the PMOS transistor 120 and the switches can be manufactured by a LTPO (low temperature polycrystalline oxide) process.

第一開關111之通道係耦接於一正直流電壓V INI與一第一節點A之間,且第一開關111係由一第一開關信號SW1控制其通道之導通與斷開。 The channel of the first switch 111 is coupled between a positive DC voltage V INI and a first node A, and the first switch 111 is controlled by a first switch signal SW1 to turn on and off the channel.

第二開關112之通道係耦接於第一節點A與一共通電壓V COM之間,且第二開關112係由一第二開關信號SW2控制其通道之導通與斷開。 The channel of the second switch 112 is coupled between the first node A and a common voltage V COM , and the conduction and disconnection of the channel of the second switch 112 are controlled by a second switch signal SW2.

第三開關113之通道係耦接於一資料電壓V DATA與一第二節點B之間,且第三開關113係由一第三開關信號SW3控制其通道之導通與斷開。 The channel of the third switch 113 is coupled between a data voltage V DATA and a second node B, and the conduction and disconnection of the channel of the third switch 113 are controlled by a third switch signal SW3.

第四開關114之通道係耦接於一第三節點C與一第四節點D之間,且第四開關114係由一第四開關信號SW4控制其通道之導通與斷開。The channel of the fourth switch 114 is coupled between a third node C and a fourth node D, and the conduction and disconnection of the channel of the fourth switch 114 are controlled by a fourth switch signal SW4.

第五開關115之通道係耦接於第一節點A與第三節點C之間,且第五開關115係由一第五開關信號SW5控制其通道之導通與斷開。另外,較佳地,第四開關114和第五開關115均可為NMOS電晶體以在其被斷開時提供良好的絕緣效果,從而可延長儲存電容130的電壓保持時間以支持低畫面刷新率,例如1H Z的畫面刷新率。 The channel of the fifth switch 115 is coupled between the first node A and the third node C, and the fifth switch 115 is controlled by a fifth switch signal SW5 to turn on and off the channel. In addition, preferably, the fourth switch 114 and the fifth switch 115 can both be NMOS transistors to provide a good insulation effect when they are disconnected, thereby extending the voltage holding time of the storage capacitor 130 to support a low screen refresh rate, such as a 1 Hz screen refresh rate.

PMOS電晶體120具有一源極、一閘極和一汲極,該源極耦接第一節點A,該閘極耦接第三節點C,且該汲極耦接第二節點B,且PMOS電晶體120係用以藉由該汲極輸出一驅動電流至OLED元件140。The PMOS transistor 120 has a source, a gate and a drain. The source is coupled to the first node A, the gate is coupled to the third node C, and the drain is coupled to the second node B. The PMOS transistor 120 is used to output a driving current to the OLED element 140 via the drain.

第一導通時間調變開關121係耦接於第一節點A與一第五節點E之間,且第一導通時間調變開關121係依一PWM信號EM控制其導通時間。另外,第五節點E係與一直流供應電壓ELVDD耦接。The first on-time modulation switch 121 is coupled between the first node A and a fifth node E, and the on-time of the first on-time modulation switch 121 is controlled according to a PWM signal EM. In addition, the fifth node E is coupled to a DC supply voltage ELVDD.

第二導通時間調變開關122係耦接於第二節點B與第四節點D之間,且第二導通時間調變開關122係依PWM信號EM控制其導通時間。The second on-time modulation switch 122 is coupled between the second node B and the fourth node D, and the on-time of the second on-time modulation switch 122 is controlled according to the PWM signal EM.

儲存電容130係耦接於第三節點C與第五節點E之間,用以儲存電壓以提供PMOS電晶體120之該源極和該閘極間之電壓差以產生該驅動電流。The storage capacitor 130 is coupled between the third node C and the fifth node E, and is used to store a voltage to provide a voltage difference between the source and the gate of the PMOS transistor 120 to generate the driving current.

OLED元件140係耦接於第四節點D與一負直流電壓ELVSS之間,且係依該驅動電流產生對應的亮度。The OLED element 140 is coupled between the fourth node D and a negative DC voltage ELVSS, and generates corresponding brightness according to the driving current.

於操作時,AMOLED像素補償電路100依序執行以下步驟:During operation, the AMOLED pixel compensation circuit 100 performs the following steps in sequence:

(一)第一階段:使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、第一導通時間調變開關121、第二導通時間調變開關122)對應呈現(導通、斷開、斷開、導通、導通、斷開、斷開),以使第一節點A、第三節點C及第四節點D之電壓均為正直流電壓V INI以初始化PMOS電晶體120之閘極電壓及OLED元件140的陽極電壓,其情形請參照圖2a; (i) The first stage: (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the first on-time modulation switch 121, the second on-time modulation switch 122) are made to present (on, off, off, on, on, off, off) correspondingly, so that the voltages of the first node A, the third node C and the fourth node D are all positive DC voltages VINI to initialize the gate voltage of the PMOS transistor 120 and the anode voltage of the OLED element 140. Please refer to FIG. 2a for the situation;

(二)第二階段:使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、第一導通時間調變開關121、第二導通時間調變開關122)對應呈現(斷開、導通、斷開、斷開、斷開、斷開、斷開),以使第三節點C之電壓為正直流電壓V INI,及第一節點A之電壓為共通電壓V COM,其情形請參照圖2b;依此,設於一顯示面板之多個像素中之像素補償電路的PMOS電晶體120之閘-源極電壓會均一化為(V INI-V COM),從而可極小化PMOS電晶體120之源-閘極寄生電容之遲滯電壓的差異而有效降低顯示畫面的短期殘影現象; (ii) The second stage: the (first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the first on-time modulation switch 121, the second on-time modulation switch 122) are made to present (off, on, off, off, off, off, off, off), so that the voltage of the third node C is the positive DC voltage V INI , and the voltage of the first node A is the common voltage V COM , as shown in FIG. 2 b ; accordingly, the gate-source voltage of the PMOS transistor 120 of the pixel compensation circuit in the plurality of pixels of a display panel is uniformly (V INI -V COM ), thereby minimizing the difference in hysteresis voltage of the source-gate parasitic capacitance of the PMOS transistor 120 and effectively reducing the short-term afterimage phenomenon of the display screen;

(三)第三階段:使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、第一導通時間調變開關121、第二導通時間調變開關122)對應呈現(斷開、斷開、導通、斷開、導通、斷開、斷開),以使第三節點C之電壓及第一節點A之電壓均為(V DATA+V th),其中,V th為PMOS電晶體120之閾值電壓,其情形請參照圖2c;此時儲存電容130所儲存的電壓為ELVDD與(V DATA+V th)之差,亦即,儲存電容130儲存的電壓中包含了PMOS電晶體120之閾值電壓,其將可用以在驅使PMOS電晶體120產生該驅動電流時補償PMOS電晶體120之閾值電壓;以及 (III) The third stage: (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the first on-time modulation switch 121, the second on-time modulation switch 122) are made to present (off, off, on, off, on, off, off) correspondingly, so that the voltage of the third node C and the voltage of the first node A are both (V DATA +V th ), wherein V th is the threshold voltage of the PMOS transistor 120, and the situation is shown in FIG. 2c ; at this time, the voltage stored in the storage capacitor 130 is ELVDD and (V DATA +V th ), that is, the voltage stored in the storage capacitor 130 includes the threshold voltage of the PMOS transistor 120, which can be used to compensate the threshold voltage of the PMOS transistor 120 when the PMOS transistor 120 is driven to generate the driving current; and

(四)第四階段:使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、第一導通時間調變開關121、第二導通時間調變開關122)對應呈現(斷開、斷開、斷開、斷開、斷開、導通、導通),以使第三節點C之電壓為(V DATA+V th),及第一節點A之電壓為ELVDD,其情形請參照圖2d;依此,儲存電容130儲存的電壓即可用以偏壓PMOS電晶體120的該閘極和該源極而產生該驅動電流,並使該驅動電流流過OLED元件140而使OLED元件140發光,且該驅動電流與PMOS電晶體120之閾值電壓無關。該驅動電流可用以下的公式表示:IOLED=(WCOXμ/2L)(Vgs-Vth)2=(WCOXμ/2L)(VDATA+Vth-ELVDD-Vth)2=(WCOXμ/2L)(VDATA-ELVDD)2,其中,IOLED代表該驅動電流,W代表通道寬度,COX代表以氧化層介質電容,μ代表載子移動率,L代表通道長度。 (IV) The fourth stage: the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the first on-time modulation switch 121, the second on-time modulation switch 122 are made to present (off, off, off, off, off, on, on) correspondingly, so that the voltage of the third node C is (V DATA +V TH ), and the voltage of the first node A is ELVDD, please refer to FIG. 2d; accordingly, the voltage stored in the storage capacitor 130 can be used to bias the gate and the source of the PMOS transistor 120 to generate the driving current, and the driving current flows through the OLED element 140 to make the OLED element 140 emit light, and the driving current is independent of the threshold voltage of the PMOS transistor 120. The driving current can be expressed by the following formula: I OLED =(WC OX μ/2L)(V gs -V th ) 2 =(WC OX μ/2L)(V DATA +V th -ELVDD-V th ) 2 =(WC OX μ/2L)(V DATA -ELVDD) 2 , wherein I OLED represents the driving current, W represents the channel width, C OX represents the oxide layer dielectric capacitance, μ represents the carrier mobility, and L represents the channel length.

請參照圖2e,其繪示圖1之AMOLED像素補償電路100之一工作時序圖。如圖2d所示,T1代表第一階段,T2代表第二階段,T3代表第三階段,以及T4代表第四階段。第一開關111為PMOS電晶體,第二開關112為PMOS電晶體,第三開關113為PMOS電晶體,第四開關114為NMOS電晶體,第五開關115為NMOS電晶體,第一導通時間調變開關121為PMOS電晶體,第二導通時間調變開關122為PMOS電晶體。 Please refer to FIG. 2e, which shows a working timing diagram of the AMOLED pixel compensation circuit 100 of FIG. 1. As shown in FIG. 2d, T1 represents the first stage, T2 represents the second stage, T3 represents the third stage, and T4 represents the fourth stage. The first switch 111 is a PMOS transistor, the second switch 112 is a PMOS transistor, the third switch 113 is a PMOS transistor, the fourth switch 114 is an NMOS transistor, the fifth switch 115 is an NMOS transistor, the first on-time modulation switch 121 is a PMOS transistor, and the second on-time modulation switch 122 is a PMOS transistor.

在T1中,EM為高電位,SW1為低電位,SW2為高電位,SW3為高電位,SW4為高電位,SW5為高電位,致使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、第一導通時間調變開關121、第二導通時間調變開關122)對應呈現(導通、斷開、斷開、導通、導通、斷開、斷開)。 In T1, EM is at a high potential, SW1 is at a low potential, SW2 is at a high potential, SW3 is at a high potential, SW4 is at a high potential, and SW5 is at a high potential, so that (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the first on-time modulation switch 121, and the second on-time modulation switch 122) are displayed correspondingly (on, off, off, on, on, off, off).

在T2中,EM為高電位,SW1為高電位,SW2為低電位,SW3為高電位,SW4為低電位,SW5為低電位,致使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、第一導通時間調變開關121、第二導通時間調變開關122)對應呈現(斷開、導通、斷開、斷開、斷開、斷開、斷開)。 In T2, EM is at a high potential, SW1 is at a high potential, SW2 is at a low potential, SW3 is at a high potential, SW4 is at a low potential, and SW5 is at a low potential, so that (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the first on-time modulation switch 121, and the second on-time modulation switch 122) are displayed correspondingly (disconnect, conduct, disconnect, disconnect, disconnect, disconnect, disconnect, disconnect).

在T3中,EM為高電位,SW1為高電位,SW2為高電位,SW3為低電位,SW4為低電位,SW5為高電位,致使(第一開關111、第二開關112、 第三開關113、第四開關114、第五開關115、第一導通時間調變開關121、第二導通時間調變開關122)對應呈現(斷開、斷開、導通、斷開、導通、斷開、斷開)。 In T3, EM is at a high potential, SW1 is at a high potential, SW2 is at a high potential, SW3 is at a low potential, SW4 is at a low potential, and SW5 is at a high potential, so that (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the first on-time modulation switch 121, the second on-time modulation switch 122) are displayed correspondingly (disconnect, disconnect, conduct, disconnect, conduct, disconnect, disconnect).

在T4中,EM為低電位,SW1為高電位,SW2為高電位,SW3為高電位,SW4為低電位,SW5為低電位,致使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、第一導通時間調變開關121、第二導通時間調變開關122)對應呈現(斷開、斷開、斷開、斷開、斷開、導通、導通)。 In T4, EM is at a low potential, SW1 is at a high potential, SW2 is at a high potential, SW3 is at a high potential, SW4 is at a low potential, and SW5 is at a low potential, so that (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the first on-time modulation switch 121, and the second on-time modulation switch 122) are displayed correspondingly (off, off, off, off, off, on, on).

由上述的說明可知,本發明揭露了一種AMOLED像素補償電路,其具有一開關電路、一PMOS電晶體、一儲存電容及一OLED元件,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,且該開關操作程序包括:以一第一直流電壓設定該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓;以一第二直流電壓設定該PMOS電晶體之源極電壓使該PMOS電晶體之該閘極電壓和該源極電壓的差等於(該第一直流電壓-該第二直流電壓);使該PMOS電晶體與該儲存電容串聯於一資料電壓與一直流供應電壓之間以使該儲存電容儲存的電壓為該直流供應電壓與(該資料電壓與該PMOS電晶體之閾值電壓之和)之差;以及使該儲存電容的兩端分別耦接該PMOS電晶體的該閘極和該源極而產生該驅動電流。 As can be seen from the above description, the present invention discloses an AMOLED pixel compensation circuit, which has a switch circuit, a PMOS transistor, a storage capacitor and an OLED element. The switch circuit is used to execute a switch operation procedure to drive the PMOS transistor to generate a driving current so that the OLED element generates a brightness, and the switch operation procedure includes: setting the gate voltage of the PMOS transistor and the anode voltage of the OLED element with a first DC voltage; setting the PM with a second DC voltage. The source voltage of the OS transistor makes the difference between the gate voltage and the source voltage of the PMOS transistor equal to (the first DC voltage - the second DC voltage); the PMOS transistor and the storage capacitor are connected in series between a data voltage and a DC supply voltage so that the voltage stored in the storage capacitor is the difference between the DC supply voltage and (the sum of the data voltage and the threshold voltage of the PMOS transistor); and the two ends of the storage capacitor are respectively coupled to the gate and the source of the PMOS transistor to generate the driving current.

在可能的實施例中,該開關電路和該PMOS電晶體可由低温多晶氧化物製程製造而成。另外,該開關電路中之任一電晶體可為PMOS電晶體、NMOS電晶體或CMOS電晶體。 In a possible embodiment, the switch circuit and the PMOS transistor can be manufactured by a low temperature polycrystalline oxide process. In addition, any transistor in the switch circuit can be a PMOS transistor, an NMOS transistor, or a CMOS transistor.

依上述的說明,本發明進一步提出一種OLED顯示裝置。請參照圖3,其繪示本發明之OLED顯示裝置之一實施例之方塊圖。如圖3所示,一OLED顯示裝置200具有一驅動電路210及一AMOLED面板220,AMOLED面板220具有 多個AMOLED像素補償電路221,其中,AMOLED像素補償電路221係由AMOLED像素補償電路100實現,驅動電路210係用以使各AMOLED像素補償電路221依前述的工作時序點亮OLED元件。 According to the above description, the present invention further proposes an OLED display device. Please refer to FIG. 3, which shows a block diagram of an embodiment of the OLED display device of the present invention. As shown in FIG. 3, an OLED display device 200 has a driving circuit 210 and an AMOLED panel 220, and the AMOLED panel 220 has a plurality of AMOLED pixel compensation circuits 221, wherein the AMOLED pixel compensation circuit 221 is implemented by the AMOLED pixel compensation circuit 100, and the driving circuit 210 is used to make each AMOLED pixel compensation circuit 221 light up the OLED element according to the aforementioned working sequence.

依上述的說明,本發明進一步提出一種資訊處理裝置。請參照圖4,其繪示本發明之資訊處理裝置之一實施例之方塊圖。如圖4所示,一資訊處理裝置300具有一中央處理單元310及一OLED顯示裝置320,其中,中央處理單元310係用以與OLED顯示裝置320通信,OLED顯示裝置320係由OLED顯示裝置200實現。 According to the above description, the present invention further proposes an information processing device. Please refer to FIG. 4, which shows a block diagram of an embodiment of the information processing device of the present invention. As shown in FIG. 4, an information processing device 300 has a central processing unit 310 and an OLED display device 320, wherein the central processing unit 310 is used to communicate with the OLED display device 320, and the OLED display device 320 is implemented by the OLED display device 200.

另外,資訊處理裝置300可為一攜帶型電腦、一智慧型手機或一車用電腦。 In addition, the information processing device 300 may be a portable computer, a smart phone, or a car computer.

藉由前述所揭露的設計,本發明乃具有以下的優點: Through the design disclosed above, the present invention has the following advantages:

一、本發明之AMOLED像素補償電路可在顯示一幀畫面的過程中先快速均一化各OLED像素的電流源電晶體的源-閘極電壓,從而極小化電流源電晶體之源-閘極寄生電容之遲滯電壓對顯示畫面所造成的短期殘影。 1. The AMOLED pixel compensation circuit of the present invention can quickly equalize the source-gate voltage of the current source transistor of each OLED pixel in the process of displaying a frame, thereby minimizing the short-term residual effect of the hysteresis voltage of the source-gate parasitic capacitance of the current source transistor on the display image.

二、本發明之AMOLED像素補償電路可補償電流源電晶體之閾值電壓以極小化因製程偏差及供應電壓的電壓降所帶來的顯示不均及Mura現象。 2. The AMOLED pixel compensation circuit of the present invention can compensate the threshold voltage of the current source transistor to minimize the display unevenness and Mura phenomenon caused by process deviation and supply voltage drop.

三、本發明之AMOLED像素補償電路可延長儲存電容的電壓保持時間以支持低畫面刷新率。 3. The AMOLED pixel compensation circuit of the present invention can extend the voltage holding time of the storage capacitor to support low screen refresh rate.

四、本發明之OLED顯示裝置可藉由前述的AMOLED像素補償電路極小化顯示畫面的短期殘影。 4. The OLED display device of the present invention can minimize the short-term afterimage of the display screen through the aforementioned AMOLED pixel compensation circuit.

五、本發明之OLED顯示裝置可藉由前述的AMOLED像素補償電路極小化因製程偏差及供應電壓的電壓降所帶來的顯示不均及Mura現象,以及延長儲存電容的電壓保持時間以支持低畫面刷新率。 5. The OLED display device of the present invention can minimize the display unevenness and Mura phenomenon caused by process deviation and voltage drop of supply voltage through the aforementioned AMOLED pixel compensation circuit, and extend the voltage retention time of the storage capacitor to support low screen refresh rate.

六、本發明之資訊處理裝置可藉由前述的AMOLED像素補償電路優化顯示效果及支持低畫面刷新率。 6. The information processing device of the present invention can optimize the display effect and support low screen refresh rate through the aforementioned AMOLED pixel compensation circuit.

本發明所揭示者,乃較佳實施例之一種,舉凡局部之變更或修飾而源於本發明之技術思想而為熟習該項技藝知人所易於推知者,俱不脫本發明之專利權範疇。 The invention disclosed is one of the preferred embodiments. Any partial changes or modifications that are derived from the technical concept of the invention and are easily inferred by those familiar with the art do not deviate from the scope of the patent right of the invention.

綜上所陳,本案無論目的、手段與功效,皆顯示其迥異於習知技術,且其首先發明合於實用,確實符合發明之專利要件,懇請 貴審查委員明察,並早日賜予專利俾嘉惠社會,是為至禱。 In summary, this case shows that it is very different from the known technology in terms of purpose, means and effect, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely ask the review committee to examine it carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

100:AMOLED像素補償電路 100:AMOLED pixel compensation circuit

111:第一開關 111: First switch

112:第二開關 112: Second switch

113:第三開關 113: The third switch

114:第四開關 114: The fourth switch

115:第五開關 115: The fifth switch

120:PMOS電晶體 120: PMOS transistor

121:第一導通時間調變開關 121: First on-time modulation switch

122:第二導通時間調變開關 122: Second on-time modulation switch

130:儲存電容 130: Storage capacitor

140:OLED元件 140:OLED components

200:OLED顯示裝置 200:OLED display device

210:驅動電路 210:Drive circuit

220:AMOLED面板 220:AMOLED panel

221:AMOLED像素補償電路 221: AMOLED pixel compensation circuit

300:資訊處理裝置 300: Information processing device

310:中央處理單元 310: Central processing unit

320:OLED顯示裝置 320:OLED display device

圖1繪示本發明之AMOLED像素補償電路之一實施例之電路圖; 圖2a繪示圖1之AMOLED像素補償電路操作於一第一階段之等效電路圖。 圖2b繪示圖1之AMOLED像素補償電路操作於一第二階段之等效電路圖。 圖2c繪示圖1之AMOLED像素補償電路操作於一第三階段之等效電路圖。 圖2d繪示圖1之AMOLED像素補償電路操作於一第四階段之等效電路圖。 圖2e繪示圖1之AMOLED像素補償電路一工作時序圖。 圖3繪示本發明之OLED顯示裝置之一實施例之方塊圖。 圖4繪示本發明之資訊處理裝置之一實施例之方塊圖。 FIG. 1 shows a circuit diagram of an embodiment of the AMOLED pixel compensation circuit of the present invention; FIG. 2a shows an equivalent circuit diagram of the AMOLED pixel compensation circuit of FIG. 1 operating in a first stage. FIG. 2b shows an equivalent circuit diagram of the AMOLED pixel compensation circuit of FIG. 1 operating in a second stage. FIG. 2c shows an equivalent circuit diagram of the AMOLED pixel compensation circuit of FIG. 1 operating in a third stage. FIG. 2d shows an equivalent circuit diagram of the AMOLED pixel compensation circuit of FIG. 1 operating in a fourth stage. FIG. 2e shows a working timing diagram of the AMOLED pixel compensation circuit of FIG. 1. FIG. 3 shows a block diagram of an embodiment of the OLED display device of the present invention. FIG4 is a block diagram showing an embodiment of the information processing device of the present invention.

100:AMOLED像素補償電路 100:AMOLED pixel compensation circuit

111:第一開關 111: First switch

112:第二開關 112: Second switch

113:第三開關 113: The third switch

114:第四開關 114: The fourth switch

115:第五開關 115: The fifth switch

120:PMOS電晶體 120: PMOS transistor

121:第一導通時間調變開關 121: First on-time modulation switch

122:第二導通時間調變開關 122: Second on-time modulation switch

130:儲存電容 130: Storage capacitor

140:OLED元件 140:OLED components

Claims (10)

一種AMOLED像素補償電路,其具有一開關電路、一PMOS電晶體、一儲存電容及一OLED元件,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,該開關操作程序包括: 一第一階段:以一第一直流電壓設定該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓; 一第二階段:以一第二直流電壓設定該PMOS電晶體之源極電壓使該PMOS電晶體之該閘極電壓和該源極電壓的差等於(該第一直流電壓-該第二直流電壓); 一第三階段:使該PMOS電晶體與該儲存電容串聯於一資料電壓與一直流供應電壓之間以使該儲存電容儲存的電壓為該直流供應電壓與(該資料電壓與該PMOS電晶體之閾值電壓之和)之差;以及 一第四階段:使該儲存電容的兩端分別耦接該PMOS電晶體的該閘極和該源極而產生該驅動電流。 An AMOLED pixel compensation circuit has a switch circuit, a PMOS transistor, a storage capacitor and an OLED element. The switch circuit is used to execute a switch operation procedure to drive the PMOS transistor to generate a driving current so that the OLED element generates a brightness. The switch operation procedure includes: A first stage: setting the gate voltage of the PMOS transistor and the anode voltage of the OLED element with a first DC voltage; A second stage: setting the source voltage of the PMOS transistor with a second DC voltage so that the difference between the gate voltage and the source voltage of the PMOS transistor is equal to (the first DC voltage - the second DC voltage); A third stage: connecting the PMOS transistor and the storage capacitor in series between a data voltage and a DC supply voltage so that the voltage stored in the storage capacitor is the difference between the DC supply voltage and (the sum of the data voltage and the threshold voltage of the PMOS transistor); and A fourth stage: coupling the two ends of the storage capacitor to the gate and the source of the PMOS transistor respectively to generate the driving current. 如請求項1所述之AMOLED像素補償電路,其中,該開關電路和該PMOS電晶體係由低温多晶氧化物製程製造而成。An AMOLED pixel compensation circuit as described in claim 1, wherein the switch circuit and the PMOS transistor are manufactured by a low temperature polycrystalline oxide process. 如請求項2所述之AMOLED像素補償電路,其中,該開關電路中之任一電晶體係由PMOS電晶體、NMOS電晶體和CMOS電晶體所組成群組所選擇的一種電晶體。An AMOLED pixel compensation circuit as described in claim 2, wherein any transistor in the switch circuit is a transistor selected from a group consisting of PMOS transistors, NMOS transistors and CMOS transistors. 一種OLED顯示裝置,具有一AMOLED面板,該AMOLED面板具有多個AMOLED像素補償電路,各所述AMOLED像素補償電路均具有一開關電路、一PMOS電晶體、一儲存電容及一OLED元件,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,該開關操作程序包括: 一第一階段:以一第一直流電壓設定該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓; 一第二階段:以一第二直流電壓設定該PMOS電晶體之源極電壓使該PMOS電晶體之該閘極電壓和該源極電壓的差等於(該第一直流電壓-該第二直流電壓); 一第三階段:使該PMOS電晶體與該儲存電容串聯於一資料電壓與一直流供應電壓之間以使該儲存電容儲存的電壓為該直流供應電壓與(該資料電壓與該PMOS電晶體之閾值電壓之和)之差;以及 一第四階段:使該儲存電容的兩端分別耦接該PMOS電晶體的該閘極和該源極而產生該驅動電流。 An OLED display device has an AMOLED panel, the AMOLED panel has a plurality of AMOLED pixel compensation circuits, each of the AMOLED pixel compensation circuits has a switch circuit, a PMOS transistor, a storage capacitor and an OLED element, the switch circuit is used to execute a switch operation procedure to drive the PMOS transistor to generate a drive current so that the OLED element generates a brightness, the switch operation procedure includes: A first stage: setting the gate voltage of the PMOS transistor and the anode voltage of the OLED element with a first DC voltage; A second stage: setting the source voltage of the PMOS transistor with a second DC voltage so that the difference between the gate voltage and the source voltage of the PMOS transistor is equal to (the first DC voltage - the second DC voltage); A third stage: connecting the PMOS transistor and the storage capacitor in series between a data voltage and a DC supply voltage so that the voltage stored in the storage capacitor is the difference between the DC supply voltage and (the sum of the data voltage and the threshold voltage of the PMOS transistor); and A fourth stage: coupling the two ends of the storage capacitor to the gate and the source of the PMOS transistor respectively to generate the driving current. 如請求項4所述之OLED顯示裝置,其中,該開關電路和該PMOS電晶體係由低温多晶氧化物製程製造而成。An OLED display device as described in claim 4, wherein the switch circuit and the PMOS transistor are manufactured by a low-temperature polycrystalline oxide process. 如請求項5所述之OLED顯示裝置,其中,該開關電路中之任一電晶體係由PMOS電晶體、NMOS電晶體和CMOS電晶體所組成群組所選擇的一種電晶體。An OLED display device as described in claim 5, wherein any transistor in the switch circuit is a transistor selected from a group consisting of PMOS transistors, NMOS transistors and CMOS transistors. 一種資訊處理裝置,其具有一中央處理單元及一OLED顯示裝置,該中央處理單元係用以與該OLED顯示裝置通信,該OLED顯示裝置具有一AMOLED面板,該AMOLED面板具有多個AMOLED像素補償電路,各所述AMOLED像素補償電路均具有一開關電路、一PMOS電晶體、一儲存電容及一OLED元件,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,該開關操作程序包括: 一第一階段:以一第一直流電壓設定該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓; 一第二階段:以一第二直流電壓設定該PMOS電晶體之源極電壓使該PMOS電晶體之該閘極電壓和該源極電壓的差等於(該第一直流電壓-該第二直流電壓); 一第三階段:使該PMOS電晶體與該儲存電容串聯於一資料電壓與一直流供應電壓之間以使該儲存電容儲存的電壓為該直流供應電壓與(該資料電壓與該PMOS電晶體之閾值電壓之和)之差;以及 一第四階段:使該儲存電容的兩端分別耦接該PMOS電晶體的該閘極和該源極而產生該驅動電流。 An information processing device has a central processing unit and an OLED display device. The central processing unit is used to communicate with the OLED display device. The OLED display device has an AMOLED panel. The AMOLED panel has multiple AMOLED pixel compensation circuits. Each of the AMOLED pixel compensation circuits has a switch circuit, a PMOS transistor, a storage capacitor and an OLED element. The switch circuit is used to execute a switch operation procedure to drive the PMOS transistor to generate a drive current so that the OLED element generates a brightness. The switch operation procedure includes: A first stage: setting the gate voltage of the PMOS transistor and the anode voltage of the OLED element with a first DC voltage; A second stage: setting the source voltage of the PMOS transistor with a second DC voltage so that the difference between the gate voltage and the source voltage of the PMOS transistor is equal to (the first DC voltage - the second DC voltage); A third stage: connecting the PMOS transistor and the storage capacitor in series between a data voltage and a DC supply voltage so that the voltage stored in the storage capacitor is the difference between the DC supply voltage and (the sum of the data voltage and the threshold voltage of the PMOS transistor); and A fourth stage: coupling the two ends of the storage capacitor to the gate and the source of the PMOS transistor respectively to generate the driving current. 如請求項7所述之資訊處理裝置,其中,該開關電路和該PMOS電晶體係由低温多晶氧化物製程製造而成。An information processing device as described in claim 7, wherein the switch circuit and the PMOS transistor are manufactured by a low temperature polycrystalline oxide process. 如請求項8所述之資訊處理裝置,其中,該開關電路中之任一電晶體係由PMOS電晶體、NMOS電晶體和CMOS電晶體所組成群組所選擇的一種電晶體。An information processing device as described in claim 8, wherein any transistor in the switch circuit is a transistor selected from a group consisting of PMOS transistors, NMOS transistors and CMOS transistors. 如請求項7至9中任一項所述之資訊處理裝置,其係由一攜帶型電腦、一智慧型手機和一車用電腦所組成群組所選擇的一種裝置。The information processing device as described in any one of claims 7 to 9 is a device selected from the group consisting of a portable computer, a smart phone and a car computer.
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