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TWI849991B - AMOLED pixel compensation circuit, OLED display device and information processing device - Google Patents

AMOLED pixel compensation circuit, OLED display device and information processing device Download PDF

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TWI849991B
TWI849991B TW112123259A TW112123259A TWI849991B TW I849991 B TWI849991 B TW I849991B TW 112123259 A TW112123259 A TW 112123259A TW 112123259 A TW112123259 A TW 112123259A TW I849991 B TWI849991 B TW I849991B
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voltage
pmos transistor
switch
switch circuit
oled element
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TW202501450A (en
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高雪岭
譚仲齊
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大陸商北京歐錸德微電子技術有限公司
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Abstract

一種AMOLED像素補償電路,具有一開關電路、一PMOS電晶體、一電容組合及一OLED元件,該PMOS電晶體之源極耦接一直流供應電壓,該OLED元件之陰極耦接一負電壓,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,且該開關操作程序包括:該開關電路形成一第一組態以使一參考電壓耦接該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓;該開關電路形成一第二組態以使該PMOS電晶體與該電容組合連接成串聯於一共通電壓與該直流供應電壓之間的電路以採集該PMOS電晶體之閾值電壓;該開關電路形成一第三組態以使該電容組合之一端耦接一資料電壓而使其另一端呈現之電壓之成分包含該閾值電壓和該資料電壓;以及該開關電路形成一第四組態以使該PMOS電晶體和該OLED元件連接成一串聯電路以產生該驅動電流,其中,該驅動電流係由該直流供應電壓和該電容電路之該另一端之電壓的差值決定。An AMOLED pixel compensation circuit has a switch circuit, a PMOS transistor, a capacitor combination and an OLED element. The source of the PMOS transistor is coupled to a DC supply voltage, and the cathode of the OLED element is coupled to a negative voltage. The switch circuit is used to execute a switch operation procedure to drive the PMOS transistor to generate a driving current so that the OLED element generates a brightness, and the switch operation procedure includes: the switch circuit forms a first configuration to couple a reference voltage to the gate voltage of the PMOS transistor and the anode voltage of the OLED element; the switch circuit forms a second configuration. The switch circuit forms a second configuration so that the PMOS transistor and the capacitor combination are connected in series to form a circuit between a common voltage and the DC supply voltage to collect the threshold voltage of the PMOS transistor; the switch circuit forms a third configuration so that one end of the capacitor combination is coupled to a data voltage so that the components of the voltage presented at the other end include the threshold voltage and the data voltage; and the switch circuit forms a fourth configuration so that the PMOS transistor and the OLED element are connected in series to generate the driving current, wherein the driving current is determined by the difference between the DC supply voltage and the voltage at the other end of the capacitor circuit.

Description

AMOLED像素補償電路、OLED顯示裝置及資訊處理裝置AMOLED pixel compensation circuit, OLED display device and information processing device

本發明係有關積體電路領域,尤指一種AMOLED像素補償電路。The present invention relates to the field of integrated circuits, and more particularly to an AMOLED pixel compensation circuit.

一般AMOLED(active mode organic light emitting diode;主動模式有機發光二極體)顯示模組之各像素係由一像素電路構成,該像素電路包括一OLED單元及用以產生一驅動電流以驅動該OLED(organic light emitting diode;有機發光二極體)單元之一電晶體電路,該電晶體電路一般包含多個電晶體及一個儲存電容,例如7T1C(七個PMOS電晶體及一個儲存電容)架構,且係依該儲存電容所儲存的顯示資料電壓產生一定電流,及依一脈衝調變信號控制該定電流的輸出時間以決定該驅動電流的等效值,從而驅使該OLED單元呈現一預定亮度。Each pixel of a general AMOLED (active mode organic light emitting diode) display module is composed of a pixel circuit, which includes an OLED unit and a transistor circuit for generating a driving current to drive the OLED (organic light emitting diode) unit. The transistor circuit generally includes a plurality of transistors and a storage capacitor, such as a 7T1C (seven PMOS transistors and a storage capacitor) structure, and generates a certain current according to the display data voltage stored in the storage capacitor, and controls the output time of the certain current according to a pulse modulation signal to determine the equivalent value of the driving current, thereby driving the OLED unit to present a predetermined brightness.

然而,由於製程存在變異,該些像素電路中的電晶體會有閾值電壓不均勻的情形,導致各像素之顯示亮度不均而使顯示畫面有Mura(殘痕)現象。However, due to process variations, the transistors in the pixel circuits may have uneven threshold voltages, resulting in uneven display brightness of each pixel and causing Mura (mura) on the display screen.

另外,為增加行動裝置的續航力,當其顯示的畫面為靜態畫面時,一般的AMOLED顯示模組會降低顯示掃描刷新率以節省功耗。然而,當顯示掃描刷新率降低時,該電晶體電路中的電晶體漏電流卻會讓該儲存電容的儲存電壓下降,從而影響該OLED單元的顯示亮度。In addition, to increase the battery life of mobile devices, when the displayed image is a static image, the general AMOLED display module will reduce the display scan refresh rate to save power. However, when the display scan refresh rate is reduced, the transistor leakage current in the transistor circuit will cause the storage voltage of the storage capacitor to drop, thereby affecting the display brightness of the OLED unit.

為解決上述問題,本領域亟需一種新穎的 AMOLED像素補償電路架構。To solve the above problems, a novel AMOLED pixel compensation circuit architecture is urgently needed in the art.

本發明之一目的在於提供一種AMOLED像素補償電路,其可在顯示一幀畫面的過程中先快速均一化各OLED像素的電流源電晶體的源-閘極電壓,從而極小化電流源電晶體之源-閘極寄生電容之遲滯電壓對顯示畫面所造成的短期殘影。One purpose of the present invention is to provide an AMOLED pixel compensation circuit, which can quickly equalize the source-gate voltage of the current source transistor of each OLED pixel in the process of displaying a frame, thereby minimizing the short-term afterimage caused by the hysteresis voltage of the source-gate parasitic capacitance of the current source transistor on the display image.

本發明之另一目的在於提供一種AMOLED像素補償電路,其可補償電流源電晶體之閾值電壓以極小化因製程偏差及供應電壓的電壓降所帶來的顯示不均及Mura現象。Another object of the present invention is to provide an AMOLED pixel compensation circuit that can compensate the threshold voltage of a current source transistor to minimize display unevenness and Mura caused by process deviation and voltage drop of a supply voltage.

本發明之另一目的在於揭露一種AMOLED像素補償電路,其可延長驅動電壓的保持時間以支持低畫面刷新率。Another object of the present invention is to disclose an AMOLED pixel compensation circuit that can extend the holding time of the driving voltage to support a low screen refresh rate.

本發明之另一目的在於揭露一種OLED顯示裝置,其可藉由前述的AMOLED像素補償電路極小化顯示畫面的短期殘影。Another object of the present invention is to disclose an OLED display device which can minimize the short-term afterimage of the display screen by using the aforementioned AMOLED pixel compensation circuit.

本發明之另一目的在於揭露一種OLED顯示裝置,其可藉由前述的AMOLED像素補償電路極小化因製程偏差及供應電壓的電壓降所帶來的顯示不均及Mura現象,以及延長驅動電壓的保持時間以支持低畫面刷新率。Another object of the present invention is to disclose an OLED display device, which can minimize display unevenness and Mura caused by process deviation and voltage drop of supply voltage through the aforementioned AMOLED pixel compensation circuit, and prolong the holding time of driving voltage to support low screen refresh rate.

本發明之另一目的在於揭露一種OLED顯示裝置,其可藉由前述的AMOLED像素補償電路提供亮度均勻的畫面顯示效果。Another object of the present invention is to disclose an OLED display device which can provide a screen display effect with uniform brightness by using the aforementioned AMOLED pixel compensation circuit.

本發明之又一目的在於揭露一種資訊處理裝置,其可藉由前述的AMOLED像素補償電路優化顯示效果及支持低畫面刷新率。Another object of the present invention is to disclose an information processing device that can optimize display effects and support low picture refresh rates by using the aforementioned AMOLED pixel compensation circuit.

為達到前述目的,一種AMOLED像素補償電路乃被提出,其具有一開關電路、一PMOS電晶體、一電容組合及一OLED元件,該PMOS電晶體之源極耦接一直流供應電壓,該OLED元件之陰極耦接一負電壓,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,且該開關操作程序包括: 該開關電路形成一第一組態以使一參考電壓耦接該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓; 該開關電路形成一第二組態以使該PMOS電晶體與該電容組合連接成串聯於一共通電壓與該直流供應電壓之間的電路以採集該PMOS電晶體之閾值電壓; 該開關電路形成一第三組態以使該電容組合之一端耦接一資料電壓而使其另一端呈現之電壓之成分包含該閾值電壓和該資料電壓;以及 該開關電路形成一第四組態以使該PMOS電晶體和該OLED元件連接成一串聯電路以產生該驅動電流,其中,該驅動電流係由該直流供應電壓和該電容電路之該另一端之電壓的差值決定。 To achieve the above-mentioned purpose, an AMOLED pixel compensation circuit is proposed, which has a switching circuit, a PMOS transistor, a capacitor combination and an OLED element, the source of the PMOS transistor is coupled to a DC supply voltage, the cathode of the OLED element is coupled to a negative voltage, the switching circuit is used to perform a switching operation procedure to drive the PMOS transistor to generate a driving current so that the OLED element generates a brightness, and the switching operation procedure includes: The switching circuit forms a first configuration to couple a reference voltage to the gate voltage of the PMOS transistor and the anode voltage of the OLED element; The switch circuit forms a second configuration so that the PMOS transistor and the capacitor combination are connected in series between a common voltage and the DC supply voltage to collect the threshold voltage of the PMOS transistor; The switch circuit forms a third configuration so that one end of the capacitor combination is coupled to a data voltage so that the voltage presented at the other end includes the threshold voltage and the data voltage; and The switch circuit forms a fourth configuration so that the PMOS transistor and the OLED element are connected in series to generate the driving current, wherein the driving current is determined by the difference between the DC supply voltage and the voltage at the other end of the capacitor circuit.

在一實施例中,該開關電路和該PMOS電晶體係由低温多晶氧化物製程製造而成。In one embodiment, the switch circuit and the PMOS transistor are fabricated using a low temperature polycrystalline oxide process.

在一實施例中,該開關電路中之任一電晶體係由PMOS電晶體、NMOS電晶體和CMOS電晶體所組成群組所選擇的一種電晶體。In one embodiment, any transistor in the switch circuit is a transistor selected from the group consisting of PMOS transistors, NMOS transistors and CMOS transistors.

為達到前述目的,本發明進一步提出一種OLED顯示裝置,其具有一AMOLED面板,該AMOLED面板具有如前述之AMOLED像素補償電路。To achieve the aforementioned object, the present invention further provides an OLED display device having an AMOLED panel. The AMOLED panel has the AMOLED pixel compensation circuit as described above.

為達到前述目的,本發明進一步提出一種資訊處理裝置,其具有一中央處理單元及如前述之OLED顯示裝置,該中央處理單元係用以與該OLED顯示裝置通信。To achieve the aforementioned object, the present invention further provides an information processing device having a central processing unit and the aforementioned OLED display device, wherein the central processing unit is used to communicate with the OLED display device.

在可能的實施例中,所述之資訊處理裝置可為一攜帶型電腦、一智慧型手機或一車用電腦。In possible embodiments, the information processing device may be a portable computer, a smart phone or a car computer.

為使  貴審查委員能進一步瞭解本創作之結構、特徵、目的、與其優點,茲附以圖式及較佳具體實施例之詳細說明如後。In order to enable the review committee to further understand the structure, features, purpose, and advantages of this creation, the following are attached with diagrams and detailed descriptions of the preferred specific implementation examples.

本發明的原理在於:The principle of the present invention is:

(一)利用一開關電路在顯示一幀畫面的初始化期間均一化各OLED像素的電流源電晶體的源-閘極電壓以極小化各電流源電晶體之源-閘極寄生電容之遲滯電壓的差異,從而有效降低顯示畫面的短期殘影現象;(i) using a switch circuit to uniformize the source-gate voltage of the current source transistor of each OLED pixel during the initialization period of displaying a frame of picture to minimize the difference in the hysteresis voltage of the source-gate parasitic capacitance of each current source transistor, thereby effectively reducing the short-term afterimage phenomenon of the displayed picture;

(二)利用該開關電路採集包含一正供應電壓、一資料電壓及一電流源電晶體之閾值電壓之一線性組合電壓,並將該線性組合電壓預存在一儲存電容上;(ii) using the switch circuit to collect a linear combination voltage including a positive supply voltage, a data voltage and a threshold voltage of a current source transistor, and pre-storing the linear combination voltage in a storage capacitor;

(三)利用該開關電路驅使該儲存電容的電壓驅動該電流源電晶體以產生與所述正供應電壓及閾值電壓無關之一驅動電流;以及(iii) using the switch circuit to drive the voltage of the storage capacitor to drive the current source transistor to generate a driving current that is independent of the positive supply voltage and the threshold voltage; and

(四)利用氧化物半導體製程製造之開關電路提供低漏電流以延長該驅動電壓的電壓保持時間。(iv) A switch circuit manufactured using an oxide semiconductor process provides a low leakage current to extend the voltage holding time of the driving voltage.

依此,本發明即可有效降低顯示畫面的短期殘影現象、極小化閾值電壓及正供應電壓對驅動電流的影響而優化OLED面板的顯示效果,且可支持低畫面刷新率。Accordingly, the present invention can effectively reduce the short-term afterimage phenomenon of the display screen, minimize the influence of the threshold voltage and the positive supply voltage on the driving current, thereby optimizing the display effect of the OLED panel, and can support a low screen refresh rate.

請參照圖1,其繪示本發明之AMOLED像素補償電路之一實施例之電路圖。如圖1所示,一AMOLED像素補償電路100具有一第一開關111、一第二開關112、一第三開關113、一第四開關114、一第五開關115、一PMOS電晶體120、一導通時間調變開關121、一第一電容131、一第二電容132以及一OLED元件140,其中,PMOS電晶體120和該些開關可由LTPO(low temperature polycrystalline oxide;低温多晶氧化物)製程製造而成。Please refer to FIG. 1, which shows a circuit diagram of an embodiment of the AMOLED pixel compensation circuit of the present invention. As shown in FIG. 1, an AMOLED pixel compensation circuit 100 has a first switch 111, a second switch 112, a third switch 113, a fourth switch 114, a fifth switch 115, a PMOS transistor 120, a conduction time modulation switch 121, a first capacitor 131, a second capacitor 132 and an OLED element 140, wherein the PMOS transistor 120 and the switches can be manufactured by a LTPO (low temperature polycrystalline oxide) process.

第一開關111之通道係耦接於一第一節點A與一第二節點B之間,且第一開關111係由一第一開關信號SW1控制其通道之導通與斷開。The channel of the first switch 111 is coupled between a first node A and a second node B, and the first switch 111 is controlled by a first switch signal SW1 to turn on and off the channel.

第二開關112之通道係耦接於一第三節點C與一第四節點D之間,且第二開關112係由一第二開關信號SW2控制其通道之導通與斷開。The channel of the second switch 112 is coupled between a third node C and a fourth node D, and the conduction and disconnection of the channel of the second switch 112 are controlled by a second switch signal SW2.

第三開關113之通道係耦接於一資料電壓V DATA與第三節點C之間,且第三開關113係由一第三開關信號SW3控制其通道之導通與斷開。 The channel of the third switch 113 is coupled between a data voltage V DATA and the third node C, and the conduction and disconnection of the channel of the third switch 113 are controlled by a third switch signal SW3.

第四開關114之通道係耦接於第四節點D與一共通電壓V COM之間,且第四開關114係由第一開關信號SW1控制其通道之導通與斷開。 The channel of the fourth switch 114 is coupled between the fourth node D and a common voltage V COM , and the conduction and disconnection of the channel of the fourth switch 114 are controlled by the first switch signal SW1.

第五開關115之通道係耦接於第五節點E與一參考電壓V REF之間,且第五開關115係由第一開關信號SW1控制其通道之導通與斷開。 The channel of the fifth switch 115 is coupled between the fifth node E and a reference voltage V REF , and the conduction and disconnection of the channel of the fifth switch 115 are controlled by the first switch signal SW1.

PMOS電晶體120具有一源極、一閘極和一汲極,該源極耦接一直流供應電壓ELVDD,該閘極耦接第一節點A,且該汲極耦接第二節點B,且PMOS電晶體120係用以藉由該汲極輸出一驅動電流至OLED元件140。The PMOS transistor 120 has a source, a gate and a drain. The source is coupled to a DC supply voltage ELVDD, the gate is coupled to the first node A, and the drain is coupled to the second node B. The PMOS transistor 120 is used to output a driving current to the OLED element 140 via the drain.

導通時間調變開關121係耦接於第二節點B與第五節點E之間,且導通時間調變開關121係依一PWM信號EM控制其導通時間。The on-time modulation switch 121 is coupled between the second node B and the fifth node E, and the on-time modulation switch 121 controls its on-time according to a PWM signal EM.

第一電容131係耦接於第三節點C與第一節點A之間,且第二電容132係耦接於第四節點D與一第六節點F之間。第一電容131和第二電容132係用以形成一串聯電路以儲存資料電壓V DATA和採集PMOS電晶體120之閾值電壓。 The first capacitor 131 is coupled between the third node C and the first node A, and the second capacitor 132 is coupled between the fourth node D and a sixth node F. The first capacitor 131 and the second capacitor 132 are used to form a series circuit to store the data voltage V DATA and sample the threshold voltage of the PMOS transistor 120 .

OLED元件140係耦接於第五節點E與一負直流電壓ELVSS之間,且係依該驅動電流產生對應的亮度。The OLED element 140 is coupled between the fifth node E and a negative DC voltage ELVSS, and generates corresponding brightness according to the driving current.

於操作時,AMOLED像素補償電路100依序執行以下步驟:During operation, the AMOLED pixel compensation circuit 100 performs the following steps in sequence:

(一)第一階段:使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、導通時間調變開關121)對應呈現(導通、導通、斷開、導通、導通、導通),其情形請參照圖2a,以使第一節點A之電壓為V REF、第二節點B之電壓為V REF、第三節點C之電壓為V COM、第四節點D之電壓為V COM、第五節點E之電壓為V REF、第六節點F之電壓為第一開關信號SW1之邏輯0電壓,從而以一相對穩定的電壓初始化PMOS電晶體120之閘極電壓及OLED元件140的陽極電壓,以極小化PMOS電晶體120之源-閘極寄生電容之遲滯電壓(亦即,消除前一幀顯示電壓的殘留值)的影響而有效降低顯示畫面的短期殘影現象; (I) First stage: Make (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the on-time modulation switch 121) present (on, on, off, on, on, on) correspondingly, and refer to FIG. 2a for the situation, so that the voltage of the first node A is V REF , the voltage of the second node B is V REF , the voltage of the third node C is V COM , the voltage of the fourth node D is V COM , and the voltage of the fifth node E is V REF , the voltage of the sixth node F is the logic 0 voltage of the first switch signal SW1, thereby initializing the gate voltage of the PMOS transistor 120 and the anode voltage of the OLED element 140 with a relatively stable voltage, so as to minimize the influence of the hysteresis voltage of the source-gate parasitic capacitance of the PMOS transistor 120 (that is, eliminate the residual value of the previous frame display voltage) and effectively reduce the short-term afterimage phenomenon of the display screen;

(二)第二階段:使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、導通時間調變開關121)對應呈現(導通、導通、斷開、導通、導通、斷開) ,其情形請參照圖2b,以使第一節點A之電壓為(ELVDD+V th)、第二節點B之電壓為(ELVDD+ V th)、第三節點C之電壓為V COM、第四節點D之電壓為V COM、第五節點E之電壓為V REF、第六節點F之電壓為第一開關信號SW1之邏輯0電壓,其中,V th為PMOS電晶體120之閾值電壓; (ii) The second stage: make (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the on-time modulation switch 121) present (on, on, off, on, on, off) correspondingly, and refer to FIG. 2b for the situation, so that the voltage of the first node A is (ELVDD+V th ), the voltage of the second node B is (ELVDD+ V th ), the voltage of the third node C is V COM , the voltage of the fourth node D is V COM , the voltage of the fifth node E is V REF , and the voltage of the sixth node F is the logic 0 voltage of the first switch signal SW1, wherein V th is the threshold voltage of the PMOS transistor 120;

(三)第三階段:使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、導通時間調變開關121)對應呈現(斷開、導通、斷開、斷開、斷開、斷開) ,其情形請參照圖2c,以使第一節點A之電壓為(ELVDD+V th+(V H-V L)*C2/(C1+C2))、第三節點C之電壓為(V COM+(V H-V L)*C2/(C1+C2))、第四節點D之電壓為(V COM+(V H-V L)*C2/(C1+C2))、第六節點F之電壓為V H,其中,V H為第一開關信號SW1之邏輯1電壓; (III) The third stage: make (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the on-time modulation switch 121) present (off, on, off, off, off, off, off) correspondingly, and refer to FIG. 2c for the situation, so that the voltage of the first node A is (ELVDD+ Vth +( VH - VL )*C2/(C1+C2)), the voltage of the third node C is ( VCOM +( VH - VL )*C2/(C1+C2)), the voltage of the fourth node D is ( VCOM +( VH - VL )*C2/(C1+C2)), and the voltage of the sixth node F is VH , wherein V H is the logic 1 voltage of the first switch signal SW1;

(四)第四階段:使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、導通時間調變開關121)對應呈現(斷開、斷開、導通、斷開、斷開、斷開) ,其情形請參照圖2d,以使第一節點A之電壓為(ELVDD+V th+V DATA- V COM)、第三節點C之電壓為V DATA、第四節點D之電壓為(V COM+(V H-V L)*C2/(C1+C2))、第六節點F之電壓為V H;以及 (iv) The fourth stage: make (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the on-time modulation switch 121) present (off, off, on, off, off, off) correspondingly, and refer to FIG. 2d for the situation, so that the voltage of the first node A is (ELVDD+ Vth + VDATA - VCOM ), the voltage of the third node C is VDATA , the voltage of the fourth node D is ( VCOM +( VH - VL )*C2/(C1+C2)), and the voltage of the sixth node F is VH ; and

(五)第五階段:使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、導通時間調變開關121)對應呈現(斷開、斷開、斷開、斷開、斷開、導通) ,其情形請參照圖2e,以使第一節點A之電壓為(ELVDD+V th+V DATA- V COM)、第三節點C之電壓為V DATA、第四節點D之電壓為(V COM+(V H-V L)*C2/(C1+C2))、第六節點F之電壓為V H,以及該驅動電流可流過OLED元件140而使OLED元件140發光,且該驅動電流與PMOS電晶體120之閾值電壓無關。該驅動電流可用以下的公式表示: (V) Fifth stage: make (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, the on-time modulation switch 121) present (off, off, off, off, off, on) correspondingly, and refer to FIG. 2e for the situation, so that the voltage of the first node A is (ELVDD+ Vth + VDATA - VCOM ), the voltage of the third node C is VDATA , the voltage of the fourth node D is ( VCOM +( VH - VL )*C2/(C1+C2)), and the voltage of the sixth node F is VH , and the driving current can flow through the OLED element 140 to make the OLED element 140 emit light, and the driving current is independent of the threshold voltage of the PMOS transistor 120. The driving current can be expressed by the following formula:

,其中,I OLED代表該驅動電流,W代表通道寬度,C OX代表以氧化層介質電容, 代表載子移動率,L代表通道長度。依此,該驅動電流即可與閾值電壓V th及直流供應電壓ELVDD無關,從而提供亮度均勻的畫面顯示效果。 , where I OLED represents the driving current, W represents the channel width, and C OX represents the oxide dielectric capacitance. represents the carrier mobility, and L represents the channel length. Thus, the driving current is independent of the threshold voltage Vth and the DC supply voltage ELVDD, thereby providing a uniform brightness display effect.

請參照圖2f,其繪示圖1之AMOLED像素補償電路100之一工作時序圖,其中,第一開關111、第二開關112、第三開關113、第四開關114、第五開關115和導通時間調變開關121均為PMOS電晶體。如圖2f所示,T1代表第一階段,T2代表第二階段,T3代表第三階段,T4代表第四階段,以及T5代表第五階段。Please refer to FIG. 2f, which shows a working timing diagram of the AMOLED pixel compensation circuit 100 of FIG. 1, wherein the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115 and the on-time modulation switch 121 are all PMOS transistors. As shown in FIG. 2f, T1 represents the first stage, T2 represents the second stage, T3 represents the third stage, T4 represents the fourth stage, and T5 represents the fifth stage.

在T1中,EM為低電位(邏輯0),SW1為低電位(邏輯0),SW2為低電位(邏輯0),SW3為高電位(邏輯1),致使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、導通時間調變開關121)對應呈現(導通、導通、斷開、導通、導通、導通)。In T1, EM is at a low potential (logic 0), SW1 is at a low potential (logic 0), SW2 is at a low potential (logic 0), and SW3 is at a high potential (logic 1), causing (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, and the on-time modulation switch 121) to correspondingly present (on, on, off, on, on, on).

在T2中,EM為高電位,SW1為低電位,SW2為低電位,SW3為高電位,致使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、導通時間調變開關121)對應呈現(導通、導通、斷開、導通、導通、斷開)。In T2, EM is at a high potential, SW1 is at a low potential, SW2 is at a low potential, and SW3 is at a high potential, causing (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, and the on-time modulation switch 121) to correspondingly present (on, on, off, on, on, off).

在T3中,EM為高電位,SW1為高電位,SW2為低電位,SW3為高電位,致使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、導通時間調變開關121)對應呈現(斷開、導通、斷開、斷開、斷開、斷開)。In T3, EM is at a high level, SW1 is at a high level, SW2 is at a low level, and SW3 is at a high level, causing (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, and the on-time modulation switch 121) to correspondingly present (off, on, off, off, off, off, off).

在T4中,EM為高電位,SW1為高電位,SW2為高電位,SW3為低電位,致使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、導通時間調變開關121)對應呈現(斷開、斷開、導通、斷開、斷開、斷開)。In T4, EM is at a high level, SW1 is at a high level, SW2 is at a high level, and SW3 is at a low level, causing (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, and the on-time modulation switch 121) to correspondingly present (off, off, on, off, off, off, off).

在T5中,EM為低電位,SW1為高電位,SW2為高電位,SW3為高電位,致使(第一開關111、第二開關112、第三開關113、第四開關114、第五開關115、導通時間調變開關121)對應呈現(斷開、斷開、斷開、斷開、斷開、導通)。In T5, EM is at a low potential, SW1 is at a high potential, SW2 is at a high potential, and SW3 is at a high potential, causing (the first switch 111, the second switch 112, the third switch 113, the fourth switch 114, the fifth switch 115, and the on-time modulation switch 121) to correspondingly present (off, off, off, off, off, off, on).

另外,為延長PMOS電晶體120之閘極電壓的儲存時間,可以一NMOS電晶體實現第一開關111。In addition, in order to extend the storage time of the gate voltage of the PMOS transistor 120, the first switch 111 can be implemented by an NMOS transistor.

請參照圖2g,其繪示本發明之AMOLED像素補償電路之另一實施例之電路圖。如圖2g所示,一AMOLED像素補償電路100a具有一NMOS電晶體111a、一第二開關112a、一第三開關113a、一第四開關114a、一第五開關115a、一PMOS電晶體120a、一導通時間調變開關121a、一第一電容131a、一第二電容132a以及一OLED元件140a,其中,PMOS電晶體120a和該些開關可由LTPO(low temperature polycrystalline oxide;低温多晶氧化物)製程製造而成。Please refer to FIG. 2g, which shows a circuit diagram of another embodiment of the AMOLED pixel compensation circuit of the present invention. As shown in FIG. 2g, an AMOLED pixel compensation circuit 100a has an NMOS transistor 111a, a second switch 112a, a third switch 113a, a fourth switch 114a, a fifth switch 115a, a PMOS transistor 120a, a conduction time modulation switch 121a, a first capacitor 131a, a second capacitor 132a and an OLED element 140a, wherein the PMOS transistor 120a and the switches can be manufactured by a LTPO (low temperature polycrystalline oxide) process.

NMOS電晶體111a之通道係耦接於一第一節點A與一第二節點B之間,且NMOS電晶體111a係由一第四開關信號SW4控制其通道之導通與斷開。The channel of the NMOS transistor 111a is coupled between a first node A and a second node B, and the conduction and disconnection of the channel of the NMOS transistor 111a are controlled by a fourth switch signal SW4.

第二開關112a之通道係耦接於一第三節點C與一第四節點D之間,且第二開關112a係由一第二開關信號SW2控制其通道之導通與斷開。The channel of the second switch 112a is coupled between a third node C and a fourth node D, and the conduction and disconnection of the channel of the second switch 112a are controlled by a second switch signal SW2.

第三開關113a之通道係耦接於一資料電壓V DATA與第三節點C之間,且第三開關113a係由一第三開關信號SW3控制其通道之導通與斷開。 The channel of the third switch 113a is coupled between a data voltage V DATA and the third node C, and the conduction and disconnection of the channel of the third switch 113a are controlled by a third switch signal SW3.

第四開關114a之通道係耦接於第四節點D與一共通電壓V COM之間,且第四開關114a係由第一開關信號SW1控制其通道之導通與斷開。 The channel of the fourth switch 114a is coupled between the fourth node D and a common voltage V COM , and the on and off of the channel of the fourth switch 114a is controlled by the first switch signal SW1.

第五開關115a之通道係耦接於第五節點E與一參考電壓V REF之間,且第五開關115a係由第一開關信號SW1控制其通道之導通與斷開。 The channel of the fifth switch 115a is coupled between the fifth node E and a reference voltage V REF , and the conduction and disconnection of the channel of the fifth switch 115a are controlled by the first switch signal SW1.

PMOS電晶體120a具有一源極、一閘極和一汲極,該源極耦接一直流供應電壓ELVDD,該閘極耦接第一節點A,且該汲極耦接第二節點B,且PMOS電晶體120a係用以藉由該汲極輸出一驅動電流至OLED元件140a。The PMOS transistor 120a has a source, a gate and a drain. The source is coupled to a DC supply voltage ELVDD, the gate is coupled to the first node A, and the drain is coupled to the second node B. The PMOS transistor 120a is used to output a driving current to the OLED element 140a via the drain.

導通時間調變開關121a係耦接於第二節點B與第五節點E之間,且導通時間調變開關121a係依一PWM信號EM控制其導通時間。The on-time modulation switch 121a is coupled between the second node B and the fifth node E, and the on-time modulation switch 121a controls its on-time according to a PWM signal EM.

第一電容131a係耦接於第三節點C與第一節點A之間,且第二電容132a係耦接於第四節點D與一第六節點F之間。第一電容131a和第二電容132a係用以形成一串聯電路以儲存資料電壓V DATA和採集PMOS電晶體120a之閾值電壓。 The first capacitor 131a is coupled between the third node C and the first node A, and the second capacitor 132a is coupled between the fourth node D and a sixth node F. The first capacitor 131a and the second capacitor 132a are used to form a series circuit to store the data voltage V DATA and sample the threshold voltage of the PMOS transistor 120a.

OLED元件140a係耦接於第五節點E與一負直流電壓ELVSS之間,且係依該驅動電流產生對應的亮度。The OLED element 140a is coupled between the fifth node E and a negative DC voltage ELVSS, and generates corresponding brightness according to the driving current.

AMOLED像素補償電路100a之工作時序請參照圖2h,其中,第二開關112a、第三開關113a、第四開關114a、第五開關115a和導通時間調變開關121a均為PMOS電晶體。如圖2h所示,T1代表第一階段,T2代表第二階段,T3代表第三階段,T4代表第四階段,以及T5代表第五階段。Please refer to FIG2h for the working timing of the AMOLED pixel compensation circuit 100a, wherein the second switch 112a, the third switch 113a, the fourth switch 114a, the fifth switch 115a and the on-time modulation switch 121a are all PMOS transistors. As shown in FIG2h, T1 represents the first stage, T2 represents the second stage, T3 represents the third stage, T4 represents the fourth stage, and T5 represents the fifth stage.

在T1中,EM為低電位(邏輯0),SW1為低電位(邏輯0),SW2為低電位(邏輯0),SW3為高電位(邏輯1),SW4為高電位(邏輯1),致使(NMOS電晶體111a、第二開關112a、第三開關113a、第四開關114a、第五開關115a、導通時間調變開關121a)對應呈現(導通、導通、斷開、導通、導通、導通)。In T1, EM is at a low level (logic 0), SW1 is at a low level (logic 0), SW2 is at a low level (logic 0), SW3 is at a high level (logic 1), and SW4 is at a high level (logic 1), causing (NMOS transistor 111a, second switch 112a, third switch 113a, fourth switch 114a, fifth switch 115a, on-time modulation switch 121a) to correspondingly present (on, on, off, on, on, on).

在T2中,EM為高電位,SW1為低電位,SW2為低電位,SW3為高電位,SW4為高電位,致使(NMOS電晶體111a、第二開關112a、第三開關113a、第四開關114a、第五開關115a、導通時間調變開關121a)對應呈現(導通、導通、斷開、導通、導通、斷開)。In T2, EM is at a high level, SW1 is at a low level, SW2 is at a low level, SW3 is at a high level, and SW4 is at a high level, causing (NMOS transistor 111a, second switch 112a, third switch 113a, fourth switch 114a, fifth switch 115a, on-time modulation switch 121a) to correspondingly present (on, on, off, on, on, off).

在T3中,EM為高電位,SW1為高電位,SW2為低電位,SW3為高電位,SW4為低電位,致使(NMOS電晶體111a、第二開關112a、第三開關113a、第四開關114a、第五開關115a、導通時間調變開關121a)對應呈現(斷開、導通、斷開、斷開、斷開、斷開)。In T3, EM is at a high level, SW1 is at a high level, SW2 is at a low level, SW3 is at a high level, and SW4 is at a low level, causing (NMOS transistor 111a, second switch 112a, third switch 113a, fourth switch 114a, fifth switch 115a, on-time modulation switch 121a) to correspondingly present (disconnect, on, disconnect, disconnect, disconnect, disconnect).

在T4中,EM為高電位,SW1為高電位,SW2為高電位,SW3為低電位,SW4為低電位,致使(NMOS電晶體111a、第二開關112a、第三開關113a、第四開關114a、第五開關115a、導通時間調變開關121a)對應呈現(斷開、斷開、導通、斷開、斷開、斷開)。In T4, EM is at a high level, SW1 is at a high level, SW2 is at a high level, SW3 is at a low level, and SW4 is at a low level, causing (NMOS transistor 111a, second switch 112a, third switch 113a, fourth switch 114a, fifth switch 115a, on-time modulation switch 121a) to correspondingly present (off, off, on, off, off, off).

在T5中,EM為低電位,SW1為高電位,SW2為高電位,SW3為高電位,SW4為低電位,致使(NMOS電晶體111a、第二開關112a、第三開關113a、第四開關114a、第五開關115a、導通時間調變開關121a)對應呈現(斷開、斷開、斷開、斷開、斷開、導通)。In T5, EM is at a low level, SW1 is at a high level, SW2 is at a high level, SW3 is at a high level, and SW4 is at a low level, causing (NMOS transistor 111a, second switch 112a, third switch 113a, fourth switch 114a, fifth switch 115a, on-time modulation switch 121a) to correspondingly present (off, off, off, off, off, on).

由上述的說明可知,本發明揭露了一種AMOLED像素補償電路,其具有一開關電路、一PMOS電晶體、一電容組合及一OLED元件,該PMOS電晶體之源極耦接一直流供應電壓,該OLED元件之陰極耦接一負電壓,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,且該開關操作程序包括:該開關電路形成一第一組態以使一參考電壓耦接該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓;該開關電路形成一第二組態以使該PMOS電晶體與該電容組合連接成串聯於一共通電壓與該直流供應電壓之間的電路以採集該PMOS電晶體之閾值電壓;該開關電路形成一第三組態以使該電容組合之一端耦接一資料電壓而使其另一端呈現之電壓之成分包含該閾值電壓和該資料電壓;以及該開關電路形成一第四組態以使該PMOS電晶體和該OLED元件連接成一串聯電路以產生該驅動電流,其中,該驅動電流係由該直流供應電壓和該電容電路之該另一端之電壓的差值決定。As can be seen from the above description, the present invention discloses an AMOLED pixel compensation circuit, which has a switch circuit, a PMOS transistor, a capacitor combination and an OLED element, the source of the PMOS transistor is coupled to a DC supply voltage, the cathode of the OLED element is coupled to a negative voltage, the switch circuit is used to execute a switch operation procedure to drive the PMOS transistor to generate a driving current so that the OLED element generates a brightness, and the switch operation procedure includes: the switch circuit forms a first configuration so that a reference voltage is coupled to the gate voltage of the PMOS transistor and the anode voltage of the OLED element; The switch circuit forms a second configuration so that the PMOS transistor and the capacitor combination are connected in series to form a circuit between a common voltage and the DC supply voltage to collect the threshold voltage of the PMOS transistor; the switch circuit forms a third configuration so that one end of the capacitor combination is coupled to a data voltage so that the components of the voltage presented at the other end include the threshold voltage and the data voltage; and the switch circuit forms a fourth configuration so that the PMOS transistor and the OLED element are connected in series to generate the driving current, wherein the driving current is determined by the difference between the DC supply voltage and the voltage at the other end of the capacitor circuit.

在可能的實施例中,該開關電路和該PMOS電晶體可由低温多晶氧化物製程製造而成。另外,該開關電路中之任一電晶體可為PMOS電晶體、NMOS電晶體或CMOS電晶體。In a possible embodiment, the switch circuit and the PMOS transistor can be manufactured by a low temperature polycrystalline oxide process. In addition, any transistor in the switch circuit can be a PMOS transistor, an NMOS transistor or a CMOS transistor.

依上述的說明,本發明進一步提出一種OLED顯示裝置。請參照圖3,其繪示本發明之OLED顯示裝置之一實施例之方塊圖。如圖3所示,一OLED顯示裝置200具有一驅動電路210及一AMOLED面板220,AMOLED面板220具有多個AMOLED像素補償電路221,其中,AMOLED像素補償電路221係由AMOLED像素補償電路100實現,驅動電路210係用以使各AMOLED像素補償電路221依前述的工作時序點亮OLED元件。According to the above description, the present invention further proposes an OLED display device. Please refer to FIG. 3, which shows a block diagram of an embodiment of the OLED display device of the present invention. As shown in FIG. 3, an OLED display device 200 has a driving circuit 210 and an AMOLED panel 220, and the AMOLED panel 220 has a plurality of AMOLED pixel compensation circuits 221, wherein the AMOLED pixel compensation circuit 221 is implemented by the AMOLED pixel compensation circuit 100, and the driving circuit 210 is used to make each AMOLED pixel compensation circuit 221 light up the OLED element according to the aforementioned working sequence.

依上述的說明,本發明進一步提出一種資訊處理裝置。請參照圖4,其繪示本發明之資訊處理裝置之一實施例之方塊圖。如圖4所示,一資訊處理裝置300具有一中央處理單元310及一OLED顯示裝置320,其中,中央處理單元310係用以與OLED顯示裝置320通信,OLED顯示裝置320係由OLED顯示裝置200實現。According to the above description, the present invention further proposes an information processing device. Please refer to FIG. 4, which shows a block diagram of an embodiment of the information processing device of the present invention. As shown in FIG. 4, an information processing device 300 has a central processing unit 310 and an OLED display device 320, wherein the central processing unit 310 is used to communicate with the OLED display device 320, and the OLED display device 320 is implemented by the OLED display device 200.

另外,資訊處理裝置300可為一攜帶型電腦、一智慧型手機或一車用電腦。In addition, the information processing device 300 may be a portable computer, a smart phone, or a car computer.

藉由前述所揭露的設計,本發明乃具有以下的優點:Through the above disclosed design, the present invention has the following advantages:

一、本發明之AMOLED像素補償電路可在顯示一幀畫面的過程中先快速均一化各OLED像素的電流源電晶體的源-閘極電壓,從而極小化電流源電晶體之源-閘極寄生電容之遲滯電壓對顯示畫面所造成的短期殘影。1. The AMOLED pixel compensation circuit of the present invention can quickly equalize the source-gate voltage of the current source transistor of each OLED pixel in the process of displaying a frame, thereby minimizing the short-term afterimage caused by the hysteresis voltage of the source-gate parasitic capacitance of the current source transistor on the display image.

二、本發明之AMOLED像素補償電路可補償電流源電晶體之閾值電壓以極小化因製程偏差及供應電壓的電壓降所帶來的顯示不均及Mura現象。2. The AMOLED pixel compensation circuit of the present invention can compensate the threshold voltage of the current source transistor to minimize the display unevenness and Mura phenomenon caused by process deviation and voltage drop of the supply voltage.

三、本發明之AMOLED像素補償電路可延長驅動電壓的保持時間以支持低畫面刷新率。3. The AMOLED pixel compensation circuit of the present invention can extend the holding time of the driving voltage to support low screen refresh rate.

四、本發明之OLED顯示裝置可藉由前述的AMOLED像素補償電路極小化顯示畫面的短期殘影。4. The OLED display device of the present invention can minimize the short-term afterimage of the display screen by using the aforementioned AMOLED pixel compensation circuit.

五、本發明之OLED顯示裝置可藉由前述的AMOLED像素補償電路極小化因製程偏差及供應電壓的電壓降所帶來的顯示不均及Mura現象,以及延長驅動電壓的保持時間以支持低畫面刷新率。5. The OLED display device of the present invention can minimize the display unevenness and Mura phenomenon caused by process deviation and voltage drop of the supply voltage through the aforementioned AMOLED pixel compensation circuit, and prolong the holding time of the driving voltage to support a low screen refresh rate.

六、本發明之資訊處理裝置可藉由前述的AMOLED像素補償電路優化顯示效果及支持低畫面刷新率。6. The information processing device of the present invention can optimize the display effect and support low screen refresh rate through the aforementioned AMOLED pixel compensation circuit.

本發明所揭示者,乃較佳實施例之一種,舉凡局部之變更或修飾而源於本發明之技術思想而為熟習該項技藝知人所易於推知者,俱不脫本發明之專利權範疇。The present invention discloses only one of the preferred embodiments. Any partial changes or modifications that are derived from the technical concept of the present invention and are easily inferred by a person familiar with the art do not deviate from the scope of the patent right of the present invention.

綜上所陳,本案無論目的、手段與功效,皆顯示其迥異於習知技術,且其首先發明合於實用,確實符合發明之專利要件,懇請 貴審查委員明察,並早日賜予專利俾嘉惠社會,是為至禱。In summary, this case shows that its purpose, means and effects are all different from the known technology, and it is the first invention that is practical and indeed meets the patent requirements for invention. We sincerely request the review committee to examine this carefully and grant a patent as soon as possible to benefit the society. This is our utmost prayer.

100:AMOLED像素補償電路100:AMOLED pixel compensation circuit

111:第一開關111: First switch

112:第二開關112: Second switch

113:第三開關113: The third switch

114:第四開關114: The fourth switch

115:第五開關115: The fifth switch

120:PMOS電晶體120:PMOS transistor

121:導通時間調變開關121: On-time modulation switch

131:第一電容131: first capacitor

132:第二電容132: Second capacitor

140:OLED元件140:OLED components

100a:AMOLED像素補償電路100a:AMOLED pixel compensation circuit

111a:NMOS電晶體111a: NMOS transistor

112a:第二開關112a: Second switch

113a:第三開關113a: The third switch

114a:第四開關114a: The fourth switch

115a:第五開關115a: Fifth switch

120a:PMOS電晶體120a: PMOS transistor

121a:導通時間調變開關121a: On-time modulation switch

131a:第一電容131a: first capacitor

132a:第二電容132a: second capacitor

140a:OLED元件140a:OLED components

200:OLED顯示裝置200:OLED display device

210:驅動電路210:Drive circuit

220:AMOLED面板220:AMOLED panel

221:AMOLED像素補償電路221:AMOLED pixel compensation circuit

300:資訊處理裝置300: Information processing device

310:中央處理單元310: Central Processing Unit

320:OLED顯示裝置320:OLED display device

圖1繪示本發明之AMOLED像素補償電路之一實施例之電路圖。 圖2a繪示圖1之AMOLED像素補償電路操作於一第一階段之等效電路圖。 圖2b繪示圖1之AMOLED像素補償電路操作於一第二階段之等效電路圖。 圖2c繪示圖1之AMOLED像素補償電路操作於一第三階段之等效電路圖。 圖2d繪示圖1之AMOLED像素補償電路操作於一第四階段之等效電路圖。 圖2e繪示圖1之AMOLED像素補償電路操作於一第五階段之等效電路圖。 圖2f繪示圖1之AMOLED像素補償電路之一工作時序圖。 圖2g繪示本發明之AMOLED像素補償電路之另一實施例之電路圖。 圖2h繪示圖2g之AMOLED像素補償電路之一工作時序圖。 圖3繪示本發明之OLED顯示裝置之一實施例之方塊圖。 圖4繪示本發明之資訊處理裝置之一實施例之方塊圖。 FIG. 1 shows a circuit diagram of an embodiment of the AMOLED pixel compensation circuit of the present invention. FIG. 2a shows an equivalent circuit diagram of the AMOLED pixel compensation circuit of FIG. 1 operating in a first stage. FIG. 2b shows an equivalent circuit diagram of the AMOLED pixel compensation circuit of FIG. 1 operating in a second stage. FIG. 2c shows an equivalent circuit diagram of the AMOLED pixel compensation circuit of FIG. 1 operating in a third stage. FIG. 2d shows an equivalent circuit diagram of the AMOLED pixel compensation circuit of FIG. 1 operating in a fourth stage. FIG. 2e shows an equivalent circuit diagram of the AMOLED pixel compensation circuit of FIG. 1 operating in a fifth stage. FIG. 2f shows a working timing diagram of the AMOLED pixel compensation circuit of FIG. 1. FIG. 2g shows a circuit diagram of another embodiment of the AMOLED pixel compensation circuit of the present invention. FIG. 2h shows a working timing diagram of the AMOLED pixel compensation circuit of FIG. 2g. FIG. 3 shows a block diagram of an embodiment of the OLED display device of the present invention. FIG. 4 shows a block diagram of an embodiment of the information processing device of the present invention.

100:AMOLED像素補償電路 100:AMOLED pixel compensation circuit

111:第一開關 111: First switch

112:第二開關 112: Second switch

113:第三開關 113: The third switch

114:第四開關 114: The fourth switch

115:第五開關 115: The fifth switch

120:PMOS電晶體 120: PMOS transistor

121:導通時間調變開關 121: On-time modulation switch

131:第一電容 131: First capacitor

132:第二電容 132: Second capacitor

140:OLED元件 140:OLED components

Claims (10)

一種AMOLED像素補償電路,其具有一開關電路、一PMOS電晶體、一電容組合及一OLED元件,該PMOS電晶體之源極耦接一直流供應電壓,該OLED元件之陰極耦接一負直流電壓,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,且該開關操作程序包括:該開關電路形成一第一組態以使一參考電壓耦接該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓;該開關電路形成一第二組態以使該PMOS電晶體與該電容組合連接成串聯於一共通電壓與該直流供應電壓之間的電路以採集該PMOS電晶體之閾值電壓;該開關電路形成一第三組態以使該電容組合之一端耦接一資料電壓而使其另一端呈現之電壓之成分包含該閾值電壓和該資料電壓;以及該開關電路形成一第四組態以使該PMOS電晶體和該OLED元件連接成一串聯電路以產生該驅動電流,其中,該驅動電流係由該資料電壓和該共通電壓的差值決定。 An AMOLED pixel compensation circuit has a switch circuit, a PMOS transistor, a capacitor combination and an OLED element. The source of the PMOS transistor is coupled to a DC supply voltage, and the cathode of the OLED element is coupled to a negative DC voltage. The switch circuit is used to execute a switch operation procedure to drive the PMOS transistor to generate a driving current so that the OLED element generates a brightness, and the switch operation procedure includes: the switch circuit forms a first configuration so that a reference voltage is coupled to the gate voltage of the PMOS transistor and the anode voltage of the OLED element; the switch circuit The circuit forms a second configuration so that the PMOS transistor and the capacitor combination are connected in series between a common voltage and the DC supply voltage to collect the threshold voltage of the PMOS transistor; the switch circuit forms a third configuration so that one end of the capacitor combination is coupled to a data voltage so that the voltage presented at the other end includes the threshold voltage and the data voltage; and the switch circuit forms a fourth configuration so that the PMOS transistor and the OLED element are connected in series to generate the driving current, wherein the driving current is determined by the difference between the data voltage and the common voltage. 如請求項1所述之AMOLED像素補償電路,其中,該開關電路和該PMOS電晶體係由低温多晶氧化物製程製造而成。 The AMOLED pixel compensation circuit as described in claim 1, wherein the switch circuit and the PMOS transistor are manufactured by a low temperature polycrystalline oxide process. 如請求項2所述之AMOLED像素補償電路,其中,該開關電路中之任一電晶體係由PMOS電晶體、NMOS電晶體和CMOS電晶體所組成群組所選擇的一種電晶體。 The AMOLED pixel compensation circuit as described in claim 2, wherein any transistor in the switch circuit is a transistor selected from a group consisting of PMOS transistors, NMOS transistors and CMOS transistors. 一種OLED顯示裝置,具有一AMOLED面板,該AMOLED面板具有多個AMOLED像素補償電路,各所述AMOLED像素補償電路均具有一開關電路、一PMOS電晶體、一電容組合及一OLED元件,該PMOS電晶體之源極耦接一直流供應電壓,該OLED元件之陰極耦接一負直流電壓,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,且該開關操作程序包括:該開關電路形成一第一組態以使一參考電壓耦接該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓;該開關電路形成一第二組態以使該PMOS電晶體與該電容組合連接成串聯於一共通電壓與該直流供應電壓之間的電路以採集該PMOS電晶體之閾值電壓;該開關電路形成一第三組態以使該電容組合之一端耦接一資料電壓而使其另一端呈現之電壓之成分包含該閾值電壓和該資料電壓;以及該開關電路形成一第四組態以使該PMOS電晶體和該OLED元件連接成一串聯電路以產生該驅動電流,其中,該驅動電流係由該資料電壓和該共通電壓的差值決定。 An OLED display device has an AMOLED panel, the AMOLED panel has a plurality of AMOLED pixel compensation circuits, each of the AMOLED pixel compensation circuits has a switch circuit, a PMOS transistor, a capacitor combination and an OLED element, the source of the PMOS transistor is coupled to a DC supply voltage, the cathode of the OLED element is coupled to a negative DC voltage, the switch circuit is used to execute a switch operation procedure to drive the PMOS transistor to generate a driving current so that the OLED element generates a brightness, and the switch operation procedure includes: the switch circuit forms a first configuration to couple a reference voltage to the PMOS transistor; The gate voltage of the crystal and the anode voltage of the OLED element; the switch circuit forms a second configuration so that the PMOS transistor and the capacitor combination are connected in series between a common voltage and the DC supply voltage to collect the threshold voltage of the PMOS transistor; the switch circuit forms a third configuration so that one end of the capacitor combination is coupled to a data voltage so that the voltage presented at the other end includes the threshold voltage and the data voltage; and the switch circuit forms a fourth configuration so that the PMOS transistor and the OLED element are connected in series to generate the driving current, wherein the driving current is determined by the difference between the data voltage and the common voltage. 如請求項4所述之OLED顯示裝置,其中,該開關電路和該PMOS電晶體係由低温多晶氧化物製程製造而成。 An OLED display device as described in claim 4, wherein the switch circuit and the PMOS transistor are manufactured by a low temperature polycrystalline oxide process. 如請求項5所述之OLED顯示裝置,其中,該開關電路中之任一電晶體係由PMOS電晶體、NMOS電晶體和CMOS電晶體所組成群組所選擇的一種電晶體。 An OLED display device as described in claim 5, wherein any transistor in the switch circuit is a transistor selected from a group consisting of PMOS transistors, NMOS transistors and CMOS transistors. 一種資訊處理裝置,其具有一中央處理單元及一OLED顯示裝置,該中央處理單元係用以與該OLED顯示裝置通信,該OLED顯示裝置具有一AMOLED面板,該AMOLED面板具有多個AMOLED像素補償電路,各所述AMOLED像素補償電路均具有一開關電路、一PMOS電晶體、一電容組合及一OLED元件,該PMOS電晶體之源極耦接一直流供應電壓,該OLED元件之陰極耦接一負直流電壓,該開關電路係用以執行一開關操作程序以驅使該PMOS電晶體產生一驅動電流以使該OLED元件產生一亮度,且該開關操作程序包括:該開關電路形成一第一組態以使一參考電壓耦接該PMOS電晶體之閘極電壓及該OLED元件的陽極電壓;該開關電路形成一第二組態以使該PMOS電晶體與該電容組合連接成串聯於一共通電壓與該直流供應電壓之間的電路以採集該PMOS電晶體之閾值電壓;該開關電路形成一第三組態以使該電容組合之一端耦接一資料電壓而使其另一端呈現之電壓之成分包含該閾值電壓和該資料電壓;以及該開關電路形成一第四組態以使該PMOS電晶體和該OLED元件連接成一串聯電路以產生該驅動電流,其中,該驅動電流係由該資料電壓和該共通電壓的差值決定。 An information processing device has a central processing unit and an OLED display device. The central processing unit is used to communicate with the OLED display device. The OLED display device has an AMOLED panel. The AMOLED panel has a plurality of AMOLED pixel compensation circuits. Each of the AMOLED pixel compensation circuits has a switch circuit, a PMOS transistor, a capacitor combination and an OLED element. The source of the PMOS transistor is coupled to a DC supply voltage, and the cathode of the OLED element is coupled to a negative DC voltage. The switch circuit is used to execute a switch operation procedure to drive the PMOS transistor to generate a driving current so that the OLED element generates a brightness, and the switch operation procedure includes: The switch circuit forms a first configuration so that a reference voltage is coupled to the gate voltage of the PMOS transistor and the anode voltage of the OLED element; the switch circuit forms a second configuration so that the PMOS transistor and the capacitor combination are connected in series between a common voltage and the DC supply voltage to collect the threshold voltage of the PMOS transistor; the switch circuit forms a third configuration so that the PMOS transistor and the capacitor combination are connected in series to form a circuit between a common voltage and the DC supply voltage to collect the threshold voltage of the PMOS transistor; The third configuration allows one end of the capacitor combination to couple a data voltage and the other end of the capacitor combination presents a voltage whose components include the threshold voltage and the data voltage; and the switch circuit forms a fourth configuration to connect the PMOS transistor and the OLED element into a series circuit to generate the driving current, wherein the driving current is determined by the difference between the data voltage and the common voltage. 如請求項7所述之資訊處理裝置,其中,該開關電路和該PMOS電晶體係由低温多晶氧化物製程製造而成。 An information processing device as described in claim 7, wherein the switch circuit and the PMOS transistor are manufactured by a low temperature polycrystalline oxide process. 如請求項8所述之資訊處理裝置,其中,該開關電路中之任一電晶體係由PMOS電晶體、NMOS電晶體和CMOS電晶體所組成群組所選擇的一種電晶體。 An information processing device as described in claim 8, wherein any transistor in the switch circuit is a transistor selected from a group consisting of PMOS transistors, NMOS transistors and CMOS transistors. 如請求項7至9中任一項所述之資訊處理裝置,其係由一攜帶型電腦、一智慧型手機和一車用電腦所組成群組所選擇的一種裝置。The information processing device as described in any one of claims 7 to 9 is a device selected from the group consisting of a portable computer, a smart phone and a car computer.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106856087A (en) * 2015-12-07 2017-06-16 昆山工研院新型平板显示技术中心有限公司 Image element circuit and its driving method and OLED
US20180301091A1 (en) * 2017-02-24 2018-10-18 Shenzhen China Star Optoelectronics Technology Co., Ltd. Oled pixel driving circuit and pixel driving method
CN111696486A (en) * 2020-07-14 2020-09-22 京东方科技集团股份有限公司 Pixel driving circuit and driving method thereof, display substrate and display device
CN114882834A (en) * 2022-05-27 2022-08-09 Tcl华星光电技术有限公司 Pixel driving circuit, pixel driving method and display panel

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106856087A (en) * 2015-12-07 2017-06-16 昆山工研院新型平板显示技术中心有限公司 Image element circuit and its driving method and OLED
US20180301091A1 (en) * 2017-02-24 2018-10-18 Shenzhen China Star Optoelectronics Technology Co., Ltd. Oled pixel driving circuit and pixel driving method
CN111696486A (en) * 2020-07-14 2020-09-22 京东方科技集团股份有限公司 Pixel driving circuit and driving method thereof, display substrate and display device
CN114882834A (en) * 2022-05-27 2022-08-09 Tcl华星光电技术有限公司 Pixel driving circuit, pixel driving method and display panel

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