TWI847391B - Detection system for slimsas slot and method thereof - Google Patents

Abstract

A detection system for SlimSAS slot and a method thereof are provided. Detection signal is generated by detection device and detection signal is transferred to TAP controller. Detection signal is converted to detection signal in JTAG format and detection signal in JTAG format is transferred to CPLD chip and controllable power module chip of detection card and/or boundary scan chip of circuit board. SMBus pins, differential signal receiving pins, differential signal transmitting pins, CLK pins, SIDEBAND pins and GND pins of SlimSAS connection interface are detected through boundary scan chip, HCSL to LVDS module chip, IIC chip and CPLD chip. Therefore, the improve efficiency of detecting SlimSAS slot stability and detection coverage may be achieved.

Description

Detection system and method applicable to SlimSAS slot

A detection system and method thereof, in particular, refers to a system and method thereof for detecting a SlimSAS slot through a boundary scanning chip of a circuit board and/or a HCSL to LVDS module chip, an IIC chip and a CPLD chip of a detection card.

When the existing border scan test is used for the SlimSAS slot on the motherboard, a custom pin conversion adapter card, a custom pin conversion cable, and a custom SlimSAS adapter card are first required to perform the test through a virtual PCIE.

The existing detection scheme uses a large number of detection components, which makes the connection between the detection components relatively complicated, resulting in unstable detection results, and it is time-consuming to debug when an abnormality occurs during detection. In addition, the existing detection scheme cannot provide detection coverage for the CLK pin signal, SMBus pin signal and SIDEBAND pin signal in the SlimSAS slot, and cannot provide detection coverage for the short-circuit fault abnormality type of the differential signal pin of the SlimSAS slot. When multiple SlimSAS slots need to be de-detected, multiple virtual PCIEs need to be used. For the communication of the virtual PCIE, JTAG needs to be used to form a series connection, which further makes the connection between the detection components relatively complicated, resulting in unstable detection results.

In summary, it can be seen that the existing boundary scanning detection in the SlimSAS slot has long existed in the prior art, such as unstable detection, time-consuming debugging, and incomplete detection coverage. Therefore, it is necessary to propose an improved technical means to solve this problem.

In view of the problems of unstable detection, time-consuming debugging and incomplete detection in the prior art boundary scanning detection of SlimSAS slots, the present invention discloses a detection system and method applicable to SlimSAS slots, wherein:

The present invention discloses a detection system for a SlimSAS slot, which includes: a circuit board, a detection card, a test access port (TAP) controller and a detection device. The detection card further includes: a SlimSAS connection interface, an HCSL to LVDS module chip, an integrated bus circuit (Inter-Integrated Circuit, IIC) chip, a controllable power module chip, a complex programmable logic device (Complex Programmable Logic Device, CPLD) chip and a joint test action group (Joint Test Action Group, JTAG) connection port.

The circuit board has at least one SlimSAS slot and a border scanning chip;

The SlimSAS connection interface of the test card further includes two sets of System Management Bus (SMBus) pins, multiple differential signal receiving pins, multiple differential signal transmitting pins, two sets of clock (CLK) pins, multiple sideband (SIDEBAND) pins and multiple ground (GND) pins; the HCSL to LVDS module chip of the test card is electrically connected to the two sets of CLK pins; the IIC chip of the test card is electrically connected to the SMBus pins; the CPLD chip of the test card is electrically connected to the HCSL to LVDS module chip, the controllable power module chip, the IIC chip, the SIDEBAND pins and the GND pins; and the JTAG connection port of the test card is electrically connected to the CPLD chip and the controllable power module chip.

The TAP controller is electrically connected to the JTAG port; and the detection device is electrically connected to the TAP controller.

The detection device generates a detection signal and transmits it to the TAP controller. The TAP controller converts the detection signal into a detection signal in JTAG format and then transmits it to the CPLD chip and the controllable power module chip of the detection card and/or the boundary scanning chip of the circuit board. The SMBus pin, differential signal receiving pin, differential signal transmitting pin, CLK pin, SIDEBAND pin and ground pin in the SlimSAS connection interface are detected through the boundary scanning chip, HCSL to LVDS module chip, IIC chip and CPLD chip.

The detection method disclosed in the present invention is applicable to a SlimSAS slot, and comprises the following steps:

First, the circuit board has at least one SlimSAS slot and a border scanning chip; then, the detection card has a SlimSAS connection interface, an HCSL to LVDS module chip, an IIC chip, a controllable power module chip, a CPLD chip and a JTAG connection port; then, the SlimSAS connection interface is plugged into the SlimSAS slot, and the SlimSAS connection interface includes two sets of SMBus pins, multiple differential signal receiving pins, multiple differential signal transmitting pins, two sets of CLK pins, multiple SIDEBAND pins and multiple GND pins; then, the HCSL to LVDS module chip is electrically connected to the two sets of CLK pins; then, the IIC chip is electrically connected to the SMBus pins; then, the CPLD chip is electrically connected to the HCSL to LVDS module chip, the controllable power module chip, the IIC chip, the SIDEBAND pins and the GND pins. The ND pin and the GND pin are electrically connected; then, the JTAG port is electrically connected to the CPLD chip and the controllable power module chip respectively; then, the TAP controller is electrically connected to the JTAG port; then, the detection device is electrically connected to the TAP controller; then, the detection device generates a detection signal and transmits it to the TAP controller; then, the TAP controller converts the detection signal into a detection signal in the JTAG format. The detection signal is then transmitted to the CPLD chip and the controllable power module chip of the detection card and/or the boundary scanning chip of the circuit board; finally, the SMBus pin, differential signal receiving pin, differential signal transmitting pin, CLK pin, SIDEBAND pin and ground pin in the SlimSAS connection interface are detected through the boundary scanning chip, HCSL to LVDS module chip, IIC chip and CPLD chip.

The system and method disclosed in the present invention are as described above. The difference between the system and method and the prior art is that the detection device generates a detection signal and transmits it to the TAP controller. The TAP controller converts the detection signal into a detection signal in the JTAG format and then transmits it to the CPLD chip and the controllable power module chip of the detection card and/or the boundary scanning chip of the circuit board. The SMBus pin, differential signal receiving pin, differential signal transmitting pin, CLK pin, SIDEBAND pin and ground pin in the SlimSAS connection interface are detected through the boundary scanning chip, HCSL to LVDS module chip, IIC chip and CPLD chip.

Through the above-mentioned technical means, the present invention can achieve the technical effect of improving the stability and coverage of the detection of SlimSAS slots.

The following will be used in conjunction with drawings and embodiments to explain the implementation of the present invention in detail, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

The following first describes the detection system for SlimSAS slots disclosed in the present invention, and please refer to "FIG. 1", which is a system block diagram of the detection system for SlimSAS slots disclosed in the present invention.

The detection system for SlimSAS slot disclosed in the present invention comprises: a circuit board 10, a detection card 20, a TAP controller 30 and a detection device 40. The detection card 20 further comprises: a SlimSAS connection interface 21, a HCSL to LVDS module chip 22, an IIC chip 23, a controllable power module chip 24, a CPLD chip 25 and a JTAG connection port 26.

The circuit board 10 has at least one SlimSAS slot 11 and a boundary scanning chip 12. The SlimSAS connection interface 21 of the detection card 20 is plugged into one of the SlimSAS slots 11 of the circuit board 10. The TAP controller 30 is electrically connected to the JTAG connection port 26 and the boundary scanning chip 12 of the circuit board 10. The detection device 40 is electrically connected to the TAP controller 30.

Please refer to "Figure 2", which shows a block diagram of the test card of the test system applicable to the SlimSAS slot of the present invention.

The SlimSAS connection interface 21 of the detection card 20 further includes two sets of SMBus pins 211, a plurality of differential signal receiving pins 212, a plurality of differential signal transmitting pins 213, two sets of CLK pins 214, a plurality of SIDEBAND pins 215 and a plurality of GND pins 216.

The HCSL-to-LVDS module chip 22 of the test card 20 is electrically connected to the two sets of CLK pins 214, the IIC chip 23 of the test card 20 is electrically connected to the SMBus pin 211, the CPLD chip 25 of the test card 20 is electrically connected to the HCSL-to-LVDS module chip 22, the controllable power module chip 24, the IIC chip 23, the SIDEBAND pin 215 and the GND pin 216, and the JTAG connection port 26 of the test card 20 is electrically connected to the CPLD chip 25 and the controllable power module chip 24.

When the SlimSAS slot 11 of the circuit board 10 is detected, the detection device 40 generates a detection signal and transmits it to the TAP controller 30. The TAP controller 30 converts the detection signal into a detection signal in the JTAG format and then transmits it to the CPLD chip 25 and the controllable power module chip 24 of the detection card 20 and/or the boundary scanning chip 12 of the circuit board 10. The SMBus pin 211, the differential signal receiving pin 212, the differential signal transmitting pin 213, the CLK pin 214, the SIDEBAND pin 215 and the ground pin in the SlimSAS connection interface 21 are detected through the boundary scanning chip 12, the HCSL to LVDS module chip 22, the IIC chip 23 and the CPLD chip 25.

Please refer to FIG. 3 , which is a schematic diagram showing the electrical connection between the differential signal receiving pins and the differential signal transmitting pins for detecting the SlimSAS slot according to the present invention.

The differential signal receiving pin 212 and the designated differential signal transmitting pin 213 in the SlimSAS connection interface 21 of the detection card 20 are shifted and staggered to form an electrical connection. It is worth noting that the differential signal receiving pin 212 and the differential signal transmitting pin 213 are respectively arranged on different sides of the SlimSAS connection interface 21, one side of the SlimSAS connection interface 21 is called the A side and the other side of the SlimSAS connection interface 21 is called the B side.

In the embodiment, the SlimSAS connection interface 21 has 8 sets of differential pins, 2, 5, 14, 17, 20, 23, 32 and 35 on the A side of the SlimSAS connection interface 21 are DIFF_RX_DP pins (i.e., differential signal receiving pins 212), and 3, 6, 15, 18, 21, 24, 33 and 36 on the A side of the SlimSAS connection interface 21 are DIFF_RX_DN pins (i.e., differential signal receiving pins 212).

Pins 2, 5, 14, 17, 20, 23, 32, and 35 on the B side of the SlimSAS connection interface 21 are DIFF_TX_DP pins (i.e., differential signal transmission pins 213), and pins 3, 6, 15, 18, 21, 24, 33, and 36 on the A side of the SlimSAS connection interface 21 are DIFF_TX_DN pins (i.e., differential signal transmission pins 213).

Pin 2 of the A side of the SlimSAS connection interface 21 is electrically connected to pin 20 of the B side of the SlimSAS connection interface 21, pin 3 of the A side of the SlimSAS connection interface 21 is electrically connected to pin 21 of the B side of the SlimSAS connection interface 21; pin 5 of the A side of the SlimSAS connection interface 21 is electrically connected to pin 23 of the B side of the SlimSAS connection interface 21, and the SlimSAS connection interface Pin 6 of the A side of SlimSAS connection interface 21 is electrically connected to pin 24 of the B side of SlimSAS connection interface 21; pin 14 of the A side of SlimSAS connection interface 21 is electrically connected to pin 32 of the B side of SlimSAS connection interface 21; pin 15 of the A side of SlimSAS connection interface 21 is electrically connected to pin 33 of the B side of SlimSAS connection interface 21; the subsequent steps are shown in "FIG. 3" and will not be described in detail here.

When the boundary scanning chip 12 of the circuit board 10 receives the detection signal in the JTAG format from the TAP controller 30 to perform differential signal detection, the boundary scanning chip 12 of the circuit board 10 pushes the detection signal in the JTAG format to the differential signal receiving pin 212 (i.e., pins 2, 5, 14, 17, 20, 23, 32 and 35 on the A side of the above-mentioned SlimSAS connection interface 21 and pins 3, 6, 15, 18, 21, 24, 33 and 36 on the A side of the SlimSAS connection interface 21) in a boundary scanning manner.

Then, a signal is received from the differential signal transmission pin 213 (i.e., pins 20, 23, 32, 35, 2, 5, 14, and 17 on the B side of the SlimSAS connection interface 21 and pins 21, 24, 33, 36, 3, 6, 15, and 18 on the B side of the SlimSAS connection interface 21) to realize differential signal detection of the differential signal receiving pin 212 and the designated differential signal transmission pin 213.

When the boundary scanning chip 12 of the circuit board 10 receives the detection signal in the JTAG format from the TAP controller 30 to perform the signal detection of the SMBus pin, the boundary scanning chip 12 of the circuit board 10 simulates the detection signal of the IIC protocol according to the detection signal in the JTAG format, and then sends the simulated detection signal of the IIC protocol to the IIC chip 23 of the detection card 20 through the SMBus pin 211 to realize the signal detection of the SMBus pin.

When the boundary scanning chip 12 of the circuit board 10 receives the detection signal in the JTAG format from the TAP controller 30 to perform the signal detection of the CLK pin, the boundary scanning chip 12 of the circuit board 10 transmits the HCSL signal to the CPLD chip 25 of the detection card 20 through the CLK pin 214 and the HCSL to LVDS module chip 22 of the detection card 20 to realize the signal detection of the CLK pin.

When the CPLD chip 25 of the test card 20 receives a JTAG format test signal from the TAP controller 30 to perform a signal test on the SIDEBAND pin or the GND pin, the CPLD chip 25 of the test card 20 performs a boundary scan test on the directly electrically connected SIDEBAND pin 215 and the GND pin 216 to implement the signal test on the SIDEBAND pin and the GND pin.

Next, the operation method of the present invention will be described below, and please refer to "Figure 4A" and "Figure 4B" at the same time. "Figure 4A" and "Figure 4B" are method flow charts of the detection method of the present invention applicable to the SlimSAS slot.

The detection method disclosed in the present invention is applicable to a SlimSAS slot, and comprises the following steps:

First, the circuit board has at least one SlimSAS slot and a border scanning chip (step 501); then, the detection card has a SlimSAS connection interface, an HCSL to LVDS module chip, an IIC chip, a controllable power module chip, a CPLD chip and a JTAG connection port (step 502); then, the SlimSAS connection interface is plugged into the SlimSAS slot, and the SlimSAS connection interface includes two sets of SMBus pins, a plurality of differential signal receiving pins, and a plurality of differential signal receiving pins. bits, multiple differential signal transmission pins, two sets of CLK pins, multiple SIDEBAND pins and multiple GND pins (step 503); then, the HCSL to LVDS module chip is electrically connected to the two sets of CLK pins (step 504); then, the IIC chip is electrically connected to the SMBus pins (step 505); then, the CPLD chip is electrically connected to the HCSL to LVDS module chip, the controllable power module chip, the IIC chip, the SIDEBAND pins, and the GND pins. The JTAG port is electrically connected to the CPLD chip and the controllable power module chip (step 507); the TAP controller is electrically connected to the JTAG port (step 508); the detection device is electrically connected to the TAP controller; the detection device generates a detection signal and transmits it to the TAP controller (step 509); the TAP controller converts the detection signal into a JTAG signal. The detection signal in G format is then transmitted to the CPLD chip and the controllable power module chip of the detection card and/or the boundary scanning chip of the circuit board (step 510); finally, the SMBus pin, differential signal receiving pin, differential signal transmitting pin, CLK pin, SIDEBAND pin and ground pin in the SlimSAS connection interface are detected through the boundary scanning chip, HCSL to LVDS module chip, IIC chip and CPLD chip (step 511).

In summary, the difference between the present invention and the prior art is that the detection device generates a detection signal and transmits it to the TAP controller, and the TAP controller converts the detection signal into a detection signal in the JTAG format and then transmits it to the CPLD chip and the controllable power module chip of the detection card and/or the boundary scanning chip of the circuit board. The SMBus pin, differential signal receiving pin, differential signal transmitting pin, CLK pin, SIDEBAND pin and ground pin in the SlimSAS connection interface are detected through the boundary scanning chip, HCSL to LVDS module chip, IIC chip and CPLD chip.

This technical means can solve the problems of unstable detection, time-consuming debugging and incomplete detection coverage of the existing boundary scanning detection in the SlimSAS slot in the previous technology, thereby achieving the technical effect of improving the stability and detection coverage of the SlimSAS slot.

Although the implementation methods disclosed in the present invention are as above, the above contents are not used to directly limit the scope of patent protection of the present invention. Any person with ordinary knowledge in the technical field to which the present invention belongs can make slight changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention. The scope of patent protection of the present invention shall still be defined by the scope of the attached patent application.

10: Circuit board 11: SlimSAS slot 12: Boundary scanning chip 20: Detection card 21: SlimSAS connection interface 211: SMBus pin 212: Differential signal receiving pin 213: Differential signal transmitting pin 214: CLK pin 215: SIDEBAND pin 216: GND pin 22: HCSL to LVDS module chip 23: IIC chip 24: Controllable power module chip 25: CPLD chip 26: JTAG port 30: TAP controller 40: Detection device Step 501: The circuit board has at least one SlimSAS slot and a boundary scanning chip Step 502: The test card has a SlimSAS connection interface, a HCSL to LVDS module chip, an IIC chip, a controllable power module chip, a CPLD chip, and a JTAG connection port. Step 503: The SlimSAS connection interface is plugged into the SlimSAS slot. The SlimSAS connection interface includes two sets of SMBus pins, multiple differential signal receiving pins, multiple differential signal transmitting pins, two sets of CLK pins, multiple SIDEBAND pins, and multiple GND pins. Step 504: The HCSL to LVDS module chip is electrically connected to the two sets of CLK pins. Step 505: The IIC chip is electrically connected to the SMBus pins. Step 506: The CPLD chip is electrically connected to the HCSL to LVDS module chip, the controllable power module chip, the IIC chip, the SIDEBAND pin and the GND pin respectively. Step 507: The JTAG port is electrically connected to the CPLD chip and the controllable power module chip respectively. Step 508: The TAP controller is electrically connected to the JTAG port. Step 509: The detection device is electrically connected to the TAP controller; then, the detection device generates a detection signal and transmits it to the TAP controller. Step 510: The TAP controller converts the detection signal into a detection signal in the JTAG format and transmits it to the CPLD chip and the controllable power module chip of the detection card and/or the boundary scanning chip of the circuit board. Step 511: Use boundary scanning chip, HCSL to LVDS module chip, IIC chip and CPLD chip to detect SMBus pin, differential signal receiving pin, differential signal transmitting pin, CLK pin, SIDEBAND pin and ground pin in SlimSAS connection interface

FIG. 1 is a system block diagram of the detection system for SlimSAS slots of the present invention. FIG. 2 is a block diagram of the detection card of the detection system for SlimSAS slots of the present invention. FIG. 3 is a schematic diagram of the electrical connection between the differential signal receiving pin and the differential signal transmitting pin for detection of SlimSAS slots of the present invention. FIG. 4A and FIG. 4B are method flow charts of the detection method for SlimSAS slots of the present invention.

10: Circuit board 11: SlimSAS slot 12: Boundary scanning chip 20: Test card 21: SlimSAS connection interface 22: HCSL to LVDS module chip 23: IIC chip 24: Controllable power module chip 25: CPLD chip 26: JTAG port 30: TAP controller 40: Test device

Claims (10)

A detection system suitable for a SlimSAS slot, comprising: A circuit board having at least one SlimSAS slot and a boundary scanning chip; A detection card, the detection card further comprising: A SlimSAS connection interface, the SlimSAS connection interface further comprising two sets of system management bus (SMBus) pins, a plurality of differential signal receiving pins, a plurality of differential signal transmitting pins, two sets of clock (CLK) pins, a plurality of sideband (SIDEBAND) pins and a plurality of ground (GND) pins; An HCSL to LVDS module chip, electrically connected to the two sets of CLK pins; An inter-integrated circuit (IIC) chip, electrically connected to the SMBus pins; A controllable power module chip; A complex programmable logic device (CPLD) chip, electrically connected to the HCSL to LVDS module chip, the controllable power module chip, the IIC chip, the SIDEBAND pin and the GND pin; and A joint test action group (JTAG) connection port, electrically connected to the CPLD chip and the controllable power module chip; A test access port (TAP) controller, electrically connected to the JTAG connection port; and A detection device, electrically connected to the TAP controller; The detection device generates a detection signal and transmits it to the TAP controller. The TAP controller converts the detection signal into the detection signal in JTAG format and transmits it to the CPLD chip of the detection card and the controllable power module chip and/or the boundary scanning chip of the circuit board. The boundary scanning chip, the HCSL to LVDS module chip, the IIC chip and the CPLD chip are used to detect the SMBus pin, the differential signal receiving pin, the differential signal transmitting pin, the CLK pin, the SIDEBAND pin and the ground pin in the SlimSAS connection interface. A detection system suitable for a SlimSAS slot as described in claim 1, wherein the differential signal receiving pins and the designated differential signal transmitting pins are shifted and staggered to form an electrical connection, and the boundary scanning chip of the circuit board performs boundary scanning detection based on the detection signal in the JTAG format to realize differential signal detection of the differential signal receiving pins and the designated differential signal transmitting pins. A detection system suitable for a SlimSAS slot as described in claim 1, wherein the boundary scanning chip simulates the detection signal of the IIC protocol according to the detection signal in the JTAG format, and sends the simulated detection signal of the IIC protocol to the IIC chip through the SMBus pin to realize signal detection of the SMBus pin. A detection system suitable for a SlimSAS slot as described in claim 1, wherein the boundary scanning chip transmits the HCSL signal to the CPLD chip via the CLK pin and the HCSL to LVDS module chip to implement signal detection of the CLK pin. A detection system suitable for a SlimSAS slot as described in claim 1, wherein the CPLD chip performs boundary scanning detection on the SIDEBAND pin and the GND pin that are directly electrically connected to realize signal detection of the SIDEBAND pin and the GND pin. A detection method for a SlimSAS slot comprises the following steps: A circuit board has at least one SlimSAS slot and a boundary scanning chip; A detection card has a SlimSAS connection interface, a HCSL to LVDS module chip, an IIC chip, a controllable power module chip, a CPLD chip and a JTAG connection port; The SlimSAS connection interface is plugged into the SlimSAS slot, and the SlimSAS connection interface comprises two sets of SMBus pins, a plurality of differential signal receiving pins, a plurality of differential signal transmitting pins, two sets of CLK pins, a plurality of SIDEBAND pins and a plurality of GND pins; The HCSL to LVDS module chip is electrically connected to the two sets of CLK pins; The IIC chip is electrically connected to the SMBus pins; The CPLD chip is electrically connected to the HCSL to LVDS module chip, the controllable power module chip, the IIC chip, the SIDEBAND pin and the GND pin respectively; The JTAG port is electrically connected to the CPLD chip and the controllable power module chip respectively; A TAP controller is electrically connected to the JTAG port; A detection device is electrically connected to the TAP controller; The detection device generates a detection signal and transmits it to the TAP controller; The TAP controller converts the detection signal into the detection signal in JTAG format and then transmits it to the CPLD chip and the controllable power module chip of the detection card and/or the boundary scanning chip of the circuit board; and The SMBus pin, the differential signal receiving pin, the differential signal transmitting pin, the CLK pin, the SIDEBAND pin and the ground pin in the SlimSAS connection interface are detected through the boundary scanning chip, the HCSL to LVDS module chip, the IIC chip and the CPLD chip. A detection method applicable to a SlimSAS slot as described in claim 6, wherein in the step of detecting the SMBus pin, the differential signal receiving pin, the differential signal transmitting pin, the CLK pin, the SIDEBAND pin and the ground pin in the SlimSAS connection interface through the boundary scanning chip, the HCSL to LVDS module chip, the IIC chip and the CPLD chip, the differential signal receiving pin and the designated differential signal transmitting pin are shifted and staggered to form an electrical connection, and the boundary scanning chip of the circuit board performs boundary scanning detection based on the detection signal in the JTAG format to realize differential signal detection of the differential signal receiving pin and the designated differential signal transmitting pin. As described in claim 6, the detection method applicable to the SlimSAS slot, wherein in the step of detecting the SMBus pin, the differential signal receiving pin, the differential signal transmitting pin, the CLK pin, the SIDEBAND pin and the ground pin in the SlimSAS connection interface through the boundary scanning chip, the HCSL to LVDS module chip, the IIC chip and the CPLD chip, the boundary scanning chip simulates the detection signal of the IIC protocol according to the detection signal in the JTAG format, and sends the simulated IIC protocol detection signal to the IIC chip through the SMBus pin to realize the signal detection of the SMBus pin. As described in claim 6, the detection method applicable to the SlimSAS slot, wherein in the step of detecting the SMBus pin, the differential signal receiving pin, the differential signal transmitting pin, the CLK pin, the SIDEBAND pin and the ground pin in the SlimSAS connection interface through the boundary scanning chip, the HCSL to LVDS module chip, the IIC chip and the CPLD chip, the boundary scanning chip transmits the HCSL signal to the CPLD chip through the CLK pin and the HCSL to LVDS module chip to realize the signal detection of the CLK pin. As described in claim 6, the detection method applicable to the SlimSAS slot, wherein in the step of detecting the SMBus pin, the differential signal receiving pin, the differential signal transmitting pin, the CLK pin, the SIDEBAND pin and the ground pin in the SlimSAS connection interface through the boundary scanning chip, the HCSL to LVDS module chip, the IIC chip and the CPLD chip, the CPLD chip performs boundary scanning detection on the SIDEBAND pin and the GND pin that are directly electrically connected to realize signal detection of the SIDEBAND pin and the GND pin.

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