TWI846545B - Semiconductor device and forming method thereof - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a channel layer disposed over the substrate, a barrier layer disposed over the channel layer, and a source structure and a drain structure disposed over the barrier layer. The source structure includes a horizontal source portion extending along a first direction and at least one vertical source portion extending along a second direction perpendicular to the first direction. The drain structure includes a horizontal drain portion extending along the first direction and at least one vertical drain portion extending along the second direction, wherein each of the at least one vertical drain portion includes a tip drain portion and a flat drain portion conntecting the horizontal drain portion and the tip drain portion. The semiconductor device further includes a gate structure disposed over the barrier layer and between the source structure and the drain structure; and a field plate structure disposed over the barrier layer, wherein the field plate contacts and surrounds the drain structure.

Description

Semiconductor device and method of forming the same

The present disclosure relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device with a stepped field plate structure and a method for forming the same.

With the development of semiconductor technology, the market is no longer satisfied with traditional silicon transistors. In high-power and high-frequency applications, III-V compound semiconductors have shown the potential to replace silicon transistors. In recent years, high electron mobility transistors (HEMT) made of gallium nitride (GaN) have attracted particular attention.

When operating the existing GaN HEMT, the tip part (commonly known as the fingertip) of the vertical part (commonly known as the finger) of the drain structure will generate more hot carriers due to the higher electric field. Once the operation time is prolonged, the accumulated hot carriers will degrade the performance of the HEMT device or even destroy the HEMT device. Therefore, a novel HEMT structure is needed to prevent the high electric field at the tip part of the drain structure from damaging the HEMT device.

The disclosed embodiment provides a semiconductor device. The semiconductor device includes a substrate, a channel layer disposed above the substrate, a barrier layer disposed above the channel layer, and a source structure and a drain structure disposed above the barrier layer. The source structure includes a horizontal source portion extending along a first direction, and at least one vertical source portion extending along a second direction perpendicular to the first direction. The drain structure includes a horizontal drain portion extending along the first direction and at least one vertical drain portion extending along the second direction, wherein each of the at least one vertical drain portion includes a tip drain portion and a flat end drain portion connecting the horizontal drain portion and the tip drain portion. The semiconductor device further includes a gate structure disposed above the barrier layer and between the source structure and the drain structure, and a field plate structure disposed above the barrier layer, wherein the field plate structure contacts and surrounds the drain structure.

The disclosed embodiment provides a method for forming a semiconductor device. The method for forming the semiconductor device includes providing an epitaxial structure, the epitaxial structure including a substrate, a channel layer above the substrate, and a barrier layer above the channel layer; forming a passivation layer above the barrier layer; patterning the passivation layer to form a source trench and a drain trench exposing the barrier layer; forming an insulating layer on a portion of the barrier layer in the drain trench and on a portion of the passivation layer, wherein the insulating layer includes a first insulating portion in the drain trench and a second insulating portion on the passivation layer; forming a source structure in the source trench and a drain structure in the drain trench, The drain structure includes a horizontal drain portion extending along a first direction and a vertical drain portion extending along a second direction perpendicular to the first direction, and the vertical drain portion includes a tip drain portion and a flat-end drain portion connecting the horizontal drain portion and the tip drain portion, and at least a portion of the tip drain portion is formed on the first insulating portion; and a field plate structure is formed on the insulating layer and the passivation layer, wherein the field plate structure includes a first field plate portion in contact with the tip drain portion, and a second field plate portion in contact with the flat-end drain portion.

The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of the various components and arrangements of the present disclosure are described below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, if a description includes a first feature formed on or above a second feature, it may include embodiments in which the first feature and the second feature are formed in direct contact, and it may also include embodiments in which additional features are formed between the first feature and the second feature, so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeatedly reference numbers and/or letters in various examples. The purpose of this repetition is to simplify and clarify, and does not itself dictate the relationship between the various embodiments and/or configurations discussed.

Furthermore, the present disclosure may use spatially relative terminology, such as "below," "beneath," "below," "above," "above," and the like, to describe the relationship of one element or feature to other elements or features in the drawings. The spatially relative terminology is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in different orientations (rotated 90 degrees or at other orientations), and the spatially relative terminology used herein interpreted accordingly.

Further, unless specifically denied, singular words include plural words and vice versa. In addition, the present disclosure is not limited to the order of operations or events shown, as some operations can occur in a different order and/or simultaneously with other operations or events. In addition, not all operations or events shown are required to implement the methods of the present disclosure.

Generally speaking, in a GaN high electron mobility transistor (HEMT) having an aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructure, the source structure and the drain structure are finger-shaped structures in a top view, and the vertical portion of the finger structure of the source structure (also called the finger portion) and the vertical portion of the finger structure of the drain structure are arranged alternately with each other. However, the tip portion of the vertical portion of the drain structure has a higher electric field, thereby generating a high concentration of hot carriers. After accumulation, these hot carriers caused by the high electric field may cause degradation of the performance of the HEMT device or even damage the HEMT device.

In order to solve the above problems, the present disclosure provides a semiconductor device and a manufacturing method thereof, which adjusts the electric field at the tip portion of the drain structure. In this way, the peak value of the electric field can be reduced, so that the rising curve of the electric field becomes gentle to avoid a sharp change (sudden rise) of the electric field, and the electric field strength at the tip portion of the drain structure can be reduced to a level similar to the electric field at the flat portion of the drain structure, so as to avoid creating an obvious weak point in the HEMT device. In this way, the performance of the HEMT device can be further avoided from being reduced or the HEMT device can be damaged, and the robustness and reliability of the HEMT device can be increased.

FIG. 1 is a partial or entire top view of an exemplary semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 may be a single transistor device or an array of multiple transistor devices, wherein the transistor device is, for example, a GaN HEMT. In some embodiments, the semiconductor device 100 includes a source structure 110, a drain structure 120, and a gate structure 130 disposed above an epitaxial structure (e.g., the epitaxial structure 101 described below).

In some embodiments, the source structure 110 includes a horizontal source portion 112 extending along the X direction, and a vertical source portion extending along the Y direction (which may be referred to as a finger portion of the source structure). In the Y direction, the vertical source portion includes a tip source portion 116 (which may be referred to as a fingertip portion of the source structure) away from the horizontal source portion 112, and a flat-end source portion 114 connecting the horizontal source portion 112 and the tip source portion 116.

In some embodiments, the drain structure 120 includes a horizontal drain portion 122 extending along the X direction, and a vertical drain portion extending along the Y direction perpendicular to the X direction (which may be referred to as a finger portion of the drain structure). In the Y direction, the vertical drain portion includes a tip drain portion 126 (which may be referred to as a fingertip portion of the drain structure) away from the horizontal drain portion 122, and a flat end drain portion 124 connecting the horizontal drain portion 122 and the tip drain portion 126.

In some embodiments, the horizontal source portion 112 and the horizontal drain portion 122 are spaced apart from each other along the Y direction, and the vertical source portion (including the flat-end source portion 114 and the pointed source portion 116) and the vertical drain portion (including the flat-end drain portion 124 and the pointed drain portion 126) are arranged alternately along the X direction, as shown in FIG. 1. The pointed source portion 116 of the source structure 110 points to the horizontal drain portion 122 along the Y direction, and the pointed drain portion 126 of the drain structure 120 points to the horizontal source portion 112 along the Y direction.

In some embodiments, the gate structure 130 is disposed between the source structure 110 and the drain structure 120 and surrounds at least a portion of the source structure 110 and the drain structure 120. For example, the gate structure 130 surrounds a vertical source portion (including a flat-ended source portion 114 and a pointed source portion 116) and a vertical drain portion (including a flat-ended drain portion 124 and a pointed drain portion 126), as shown in FIG. 1. The gate structure 130 may be a continuous whole and continuously extends to be shared by a plurality of transistor devices. In some embodiments, the distance between the gate structure 130 and the source structure 110 is smaller than the distance between the gate structure 130 and the drain structure 120. For clarity of description, the gate structure 130 is divided into a first gate portion 132, a second gate portion 134, and a third gate portion 136 having the same stacking structure.

In the embodiment shown in FIG. 1 , the first gate portion 132 is located between the two flat-ended source portions 114 in the X direction and between the pointed drain portion 126 and the horizontal source portion 112 in the Y direction. The second gate portion 134 is located between the two flat-ended drain portions 124 in the X direction and between the pointed source portion 116 and the horizontal drain portion 122 in the Y direction. The third gate portion 136 is located between a vertical source portion (including the flat-ended source portion 114 and the pointed source portion 116) and a vertical drain portion (including the flat-ended drain portion 124 and the pointed drain portion 126) in the X direction and between the horizontal source portion 112 and the horizontal drain portion 122 in the Y direction. The third gate portion 136 is connected to each other via the first gate portion 132 and the second gate portion 134. In other words, the first gate portion 132 and the second gate portion 134 are connected to each other via the third gate portion 136. In some embodiments, the first gate portion 132 and the second gate portion 134 are arc-shaped in a top view (eg, FIG. 1 ).

In some embodiments, the semiconductor device 100 further includes an insulating layer 140. The insulating layer 140 is disposed above the epitaxial structure (e.g., the epitaxial structure 101 described below) and below the tip drain portion 126 of the drain structure 120. In some embodiments, an end of the insulating layer 140 close to the first gate portion 132 has an arc-shaped profile, as shown in FIG. 1 .

In some embodiments, the semiconductor device 100 further includes a field plate structure 150. The field plate structure 150 surrounds and contacts the drain structure 120. For example, the field plate structure 150 includes a first field plate portion 152 contacting the tip drain portion 126, and a second field plate portion 154 contacting the flat drain portion 124 and the horizontal drain portion 122. In some embodiments, the first field plate portion 152 contacting the tip drain portion 126 is disposed on the insulating layer 140, while the second field plate portion 154 is not disposed on the insulating layer 140, so that the first field plate portion 152 and the second field plate portion 154 form a stepped structure, which will be described in more detail below. In some embodiments, an end of the first field plate portion 152 close to the first gate portion 132 has an arc-shaped profile, as shown in FIG. 1 .

According to some embodiments, FIG. 2A is a cross-sectional view of the semiconductor device 100 along the line segment A-A' of FIG. 1, and FIG. 2B is a cross-sectional view of the semiconductor device 100 along the line segment B-B' of FIG. 1. FIG. 2A shows a cross-sectional view including the flat-end drain portion 124 and the second field plate portion 154 along the X direction, and FIG. 2B shows a cross-sectional view including the tip drain portion 126, the insulating layer 140, and the first field plate portion 152 along the X direction.

2A and 2B , the semiconductor device 100 includes an epitaxial structure 101, wherein the epitaxial structure 101 includes a substrate 102, a buffer layer 103 above the substrate 102, a channel layer 104 above the buffer layer 103, and a barrier layer 105 above the channel layer 104. In some embodiments, the buffer layer 103 and the channel layer 104 may be combined together and collectively referred to as a buffer layer or a channel layer.

In some embodiments, the material of the channel layer 104 is GaN, and the material of the barrier layer 105 is AlGaN. A GaN/AlGaN heterojunction where the channel layer 104 and the barrier layer 105 are stacked together forms a two-dimensional electron gas (2DEG) between the channel layer 104 and the barrier layer 105 to serve as a channel of the semiconductor device 100 (drawn in dotted lines). In some embodiments, the semiconductor device 100 further includes a passivation layer 106 disposed on the barrier layer 105, wherein the material of the passivation layer 106 is, for example, silicon nitride (SiN). It should be noted that, for simplicity of description, the passivation layer 106 is not shown in the top view of FIG. 1 .

The source structure 110, the drain structure 120 and the gate structure 130 are disposed on the epitaxial structure 101, for example, on the barrier layer 105, and disposed in the trench of the passivation layer 106. The gate structure 130 is disposed between the source structure 110 and the drain structure 120. As shown in FIG. 2A , the third gate portion 136 of the gate structure 130 is disposed between the flat-ended source portion 114 of the source structure 110 and the flat-ended drain portion 124 of the drain structure 120 along the X direction. As shown in FIG. 2B , the third gate portion 136 is disposed between the flat-ended source portion 114 and the pointed drain portion 126 of the drain structure 120 along the X direction.

2A , the flat-end drain portion 124 is disposed on the barrier layer 105 in the trench of the passivation layer 106, and the second field plate portion 154 in contact with the flat-end drain portion 124 is disposed on the passivation layer 106. In the embodiment shown in FIG. 2A , the second field plate portion 154 contacts the sidewall of the flat-end drain portion 124. In some embodiments, the top surface of the second field plate portion 154 is coplanar with the top surface of the flat-end drain portion 124. In other embodiments, the top surface of the second field plate portion 154 may be higher or lower than the top surface of the flat-end drain portion 124. In further embodiments, the second field plate portion 154 may partially cover the top surface of the flat-ended drain portion 124.

2B , the semiconductor device 100 includes an insulating layer 140 in a region where the tip drain portion 126 belongs. The insulating layer 140 includes a first insulating portion 142 directly disposed on the barrier layer 105 in the trench of the passivation layer 106, and a second insulating portion 144 directly disposed on the passivation layer 106. In the embodiment shown in FIG. 2B , a portion of the tip drain portion 126 is disposed on the first insulating portion 142, so that the tip drain portion 126 is in a "T" shape in FIG. 2B . In these embodiments, since the insulating layer 140 does not fill up the bottom of the tip drain portion 126, the insulating layer 140 is U-shaped in a top view.

In other embodiments, the insulating layer 140 includes only the second insulating portion 144 but does not include the first insulating portion 142, so that the entire tip drain portion 126 is directly disposed on the barrier layer 105 and contacts the passivation layer 106, similar to the flat-end drain portion 124 shown in FIG. 2A. In still other embodiments, in the region where the tip drain portion 126 belongs, the first insulating portion 142 of the insulating layer 140 extends and covers the entire barrier layer 105 in the trench of the passivation layer 106, so that the entire tip drain portion 126 is disposed on the first insulating portion 142 of the insulating layer 140.

Still referring to FIG. 2B , the first field plate portion 152 in contact with the tip drain portion 126 is disposed on the second insulating portion 144. In the embodiment shown in FIG. 2B , the first field plate portion 152 contacts the sidewall of the tip drain portion 126. In some embodiments, the top surface of the first field plate portion 152 is coplanar with the top surface of the tip drain portion 126. In other embodiments, the top surface of the first field plate portion 152 may be higher or lower than the top surface of the tip drain portion 126. In further embodiments, the first field plate portion 152 may partially cover the top surface of the tip drain portion 126.

As shown in FIG. 2A and FIG. 2B , due to the existence of the insulating layer 140, the first field plate portion 152 disposed on the second insulating portion 144 is higher than the second field plate portion 154 disposed on the passivation layer 106, so that the first field plate portion 152 and the second field plate portion 154 form a stepped structure. In other words, the field plate structure 150 has a stepped structure.

In other embodiments, the semiconductor device 100 may not include the passivation layer 106. In these embodiments, the insulating layer 140 may be directly disposed on the barrier layer 105, the second field plate portion 154 may be directly disposed on the barrier layer 106, and the first field plate portion 152 may also be disposed on the second insulating portion 144. In this way, the first field plate portion 152 disposed on the second insulating portion 144 is also higher than the second field plate portion 154 disposed on the barrier layer 105, so that the first field plate portion 152 and the second field plate portion 154 also form a stepped structure.

According to some embodiments, FIG. 2C is a cross-sectional view of the semiconductor device 100 along the line segment C-C' of FIG. 1, and FIG. 2D is a cross-sectional view of the semiconductor device 100 along the line segment D-D' of FIG. 1. FIG. 2C shows a cross-sectional view along the Y direction including the insulating layer 140, the first field plate portion 152, the tip drain portion 126, and the flat-end drain portion 124, and FIG. 2D shows a cross-sectional view along the Y direction including the insulating layer 140, the first field plate portion 152, and the second field plate portion 154.

2C , the first gate portion 132 of the gate structure 130 is disposed along the Y direction between the horizontal source portion 112 of the source structure 110 and the tip drain portion 126 of the drain structure 120. As described above, a portion of the tip drain portion 126 is disposed on the first insulating portion 142 of the insulating layer 140, and the first field plate portion 152 in contact with the tip drain portion 126 is disposed on the second insulating portion 144 of the insulating layer 140. Also as described above, in other embodiments, the insulating layer 140 includes only the second insulating portion 144 and the tip drain portion 126 is directly disposed on the barrier layer 105, and in still other embodiments, the first insulating portion 142 extends so that the entire tip drain portion 126 is disposed on the first insulating portion 142.

In the embodiment shown in FIG. 2C , the vertical drain portion (including the tip drain portion 126 and the flat drain portion 124) has a stepped top surface. In other embodiments, more drain material may be deposited to make the vertical drain portion have a substantially flat top surface. Since the insulating layer 140 includes a first insulating portion 142 disposed on the barrier layer 105 and a second insulating portion 144 disposed on the passivation layer 106, the insulating layer 140 also has a stepped structure in the cross-sectional views of FIG. 2B and FIG. 2C .

2D, the first field plate portion 152 in contact with the tip drain portion 126 is disposed on the second insulating portion 144, and the second field plate portion 154 in contact with the flat drain portion 124 is disposed on the passivation layer 106. As shown in FIG. 2D, the first field plate portion 152 and the second field plate portion 154 form a stepped structure. That is, the field plate structure 150 has a stepped structure. As shown in FIG. 2D, the top surface of the first field plate portion 152 is higher than the top surface of the second field plate portion 154.

As described above, the present disclosure provides a stepped field plate structure having a first field plate portion that is higher and in contact with a tip drain portion, and a second field plate portion that is lower and in contact with a flat end drain portion. The field plate structure can be used to adjust the electric field intensity, such as reducing the peak value of the electric field, and making the rising curve of the electric field smooth to avoid a sharp rise in the electric field. In this way, the high electric field of the drain structure can be prevented from causing damage to the semiconductor device.

Furthermore, by using an insulating layer to pad the field plate structure at the tip drain portion, a multi-stage first field plate portion with better effect can be formed. In this way, the electric field at the tip drain portion subjected to the highest electric field can be adjusted more effectively. At the same time, the present disclosure uses a single-stage second field plate portion that is not padded by an insulating layer at the flat end drain portion. In other words, the present disclosure uses a multi-stage first field plate portion with better effect at the tip drain portion with the highest electric field, and uses a single-stage second field plate portion that is not as effective as the multi-stage field plate at the flat end drain portion with a relatively lower electric field. In this way, the electric field of the tip drain portion and the electric field of the flat drain portion can be reduced to a similar level, while avoiding the tip drain portion still having a relatively high electric field due to the use of the same field plate structure with similar effects in the entire drain structure. In this way, in addition to reducing the electric field of the entire drain structure, it is also possible to avoid leaving a relatively high electric field weakness in the drain structure, thereby avoiding damage to the performance or structure of the semiconductor device and increasing the robustness and reliability of the semiconductor device. In addition, the insulating layer used to pad the second field plate portion can also be used to reduce leakage at the tip drain portion.

FIG. 3 is a schematic cross-sectional view of the semiconductor device 100 along the line segment C-C' of FIG. 1 according to other embodiments of the present disclosure. FIG. 3 is similar to FIG. 2C, except that FIG. 3 further includes a third insulating portion 146 and a third field plate portion 156. As shown in the figure, the third insulating portion 146 and the first field plate portion 152 are disposed on the second insulating portion 144, and the third field plate portion 156 is disposed on the third insulating portion 146 and the first field plate portion 152. In some embodiments, the third field plate portion 156 does not overlap with the first field plate portion 152, but is only disposed on the third insulating portion 146.

By disposing the third field plate portion 156 on the third insulating portion 146, a more-stepped field plate structure 150 can be formed. For example, the third field plate portion 156, the first field plate portion 152, the second insulating portion 144, and the third insulating portion 146 form a more-stepped stair-like structure. At the same time, the third field plate portion 156, the first field plate portion 152, and the second field plate portion 154 also form a more-stepped stair-like structure. By forming a more-stepped field plate structure (e.g., the third field plate portion 156 and the first field plate portion 152) on the tip drain portion 126, the electric field at the tip drain portion can be more effectively adjusted.

In further embodiments, a field plate structure with more levels than that shown in FIG3 may be formed. In other embodiments, a field plate structure with more levels (but with fewer levels than the field plate structure in the region where the tip drain portion 126 belongs) may also be formed in the region where the flat drain portion 124 belongs to, so as to more effectively adjust the electric field of the drain structure.

FIG. 4 is a flow chart of a method 400 for forming a semiconductor device 100 according to some embodiments of the present disclosure. FIG. 4 will be described below with reference to FIGS. 1 to 3 simultaneously.

In operation 402, the method 400 provides or receives an epitaxial structure, such as the epitaxial structure 101 described above. The epitaxial structure 101 includes a substrate 102, a buffer layer 103 above the substrate 102, a channel layer 104 above the buffer layer 103, and a barrier layer 105 above the channel layer 104. In some embodiments, the buffer layer 103 and the channel layer 104 can be combined and collectively referred to as a buffer layer or a channel layer.

In operation 404, the method 400 forms a passivation layer 106 on the epitaxial structure 101, for example, by forming the passivation layer 106 on the barrier layer 105 of the epitaxial structure 101 by a suitable deposition process. The material of the passivation layer 106 is, for example, silicon nitride (SiN) or silicon oxynitride (SiON). The suitable deposition process may include physical vapor deposition (PVD), chemical vapor deposition (CVD), a coating process, other suitable processes or combinations thereof. The PVD process may include sputtering, evaporation and/or pulsed laser deposition. The CVD process may include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), atomic layer deposition (ALD) process, electroplating, other suitable processes and/or combinations thereof.

In operation 406, method 400 patterns the passivation layer 106 to form source trenches and drain trenches that expose the barrier layer 105. For example, the patterning of the passivation layer 106 can be performed by a suitable lithography process and an etching process. In some embodiments, the lithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). In other embodiments, the lithography process can be performed by other suitable methods, such as maskless lithography, electron beam (e-beam) writing, and ion beam writing. In some embodiments, the etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes.

In operation 408, the method 400 forms an insulating layer 140 on a portion of the barrier layer 105 in the drain trench and on a portion of the passivation layer 106. In some embodiments, the insulating layer 140 includes a first insulating portion 142 disposed directly on the barrier layer 105 in the drain trench and a second insulating portion 144 disposed directly on the passivation layer 106, as shown in FIGS. 2B and 2C. In some embodiments, the insulating layer 140 includes only the second insulating portion 144 disposed on the passivation layer 106. In other embodiments, the insulating layer 140 further includes a third insulating portion 146 disposed on the second insulating portion 144.

In some embodiments, an insulating material may first be deposited on the passivation layer 106 and on the barrier layer 105 in the source trench and the drain trench by a suitable deposition process, and then the insulating material may be patterned by a suitable lithography and etching process to form the insulating layer 140. For example, the insulating material may include silicon nitride, silicon oxide, silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), other suitable insulating materials, or a combination thereof.

In operation 410, the method 400 forms a source structure 110 in the source trench and forms a drain structure 120 in the drain trench. As shown in FIG. 1, the source structure 110 includes a horizontal source portion 112 extending along the X direction and a vertical source portion (including a flat source portion 114 and a pointed source portion 116) extending along the Y direction, and the drain structure 120 includes a horizontal drain portion 122 extending along the X direction and a vertical drain portion (including a flat drain portion 124 and a pointed drain portion 126) extending along the Y direction.

In some embodiments, a portion of the tip drain portion 126 is disposed on the first insulating portion 142, and the remaining portion of the tip drain portion 126 is disposed on the barrier layer 105 together with the flat drain portion 124 and the horizontal drain portion 122, as shown in FIGS. 2B and 2C. In embodiments where the insulating layer 140 includes only the second insulating portion 144, the entire tip drain portion 126 is disposed on the barrier layer 105. In yet other embodiments, the entire tip drain portion 126 is disposed on the first insulating portion 142 of the insulating layer 140.

In some embodiments, operation 410 forms a patterned photoresist layer including openings on the passivation layer 106 and the insulating layer 140 by a lithography process, wherein the openings expose regions (e.g., source and drain trenches) where the source structure 110 and the drain structure 120 are to be formed. Then, a conductive material is deposited on the patterned photoresist layer by a deposition process, and then the patterned photoresist layer and the conductive material on the patterned photoresist layer are removed by a photoresist lift-off process, so as to leave the conductive material in the openings as the source structure 110 and the drain structure 120.

In other embodiments, operation 410 may first deposit a conductive material on the barrier layer 105 and the insulating layer 140 by a deposition process, and then pattern the deposited conductive material by lithography and etching processes to form the source structure 110 and the drain structure 120. The conductive material used for the source structure 110 and the drain structure 120 may include aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), ruthenium (Ru), palladium (Pd), platinum (Pt), manganese (Mn), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), tungsten silicide (WSi), titanium silicide (TiSi ₂ ), other suitable conductive materials or combinations thereof.

In operation 412, the method 400 forms a field plate structure 150 on the passivation layer 106 and the insulating layer 140. The field plate structure 150 includes a first field plate portion 152 (see FIGS. 2B and 2C ) disposed on the second insulating portion 144 of the insulating layer 140 and in contact with the tip drain portion 126, and a second field plate portion 154 (see FIG. 2A ) disposed on the passivation layer 105 and in contact with the flat drain portion 124. The first field plate portion 152 and the second field plate portion 154 form a stepped structure, as shown in FIG. 2D .

In other embodiments, the field plate structure 150 further includes a third field plate portion 156 disposed on the third insulating portion 146 on the second insulating portion 144, as shown in FIG. 3. The third field plate portion 156, the first field plate portion 152, and the second field plate portion 154 form a stepped structure. In further embodiments, more layers of insulating portions and field plate structures may be formed to form a stepped field plate structure with more levels.

In some embodiments, operation 410 and operation 412 are performed simultaneously, and the field plate structure 150 includes the same material as the source structure 110 and the drain structure 120. In other embodiments, operation 410 and operation 412 are performed separately. In these embodiments, operation 412 includes a process similar to operation 410, and the field plate structure 150 may include the same or different conductive material as the source structure 110 and the drain structure 120. In some embodiments, an annealing process may be performed after operation 410 and/or operation 412.

In operation 414, the method 400 forms a gate trench in the passivation layer 106. Operation 414 can form a gate trench in the passivation layer 106 by the same or similar method as operation 406.

In operation 416, the method 400 forms a gate structure 130 in the gate trench. Operation 416 can form the gate structure 130 in the gate trench by the same or similar method as operation 410. The gate structure 130 can include a conductive material such as Al, Cu, Au, Ag, W, Ti, Ta, Ni, Co, Ru, Pd, Pt, Mn, WN, TiN, TaN, MoN, WSi, _TiSi2 , other suitable conductive materials, or combinations thereof.

As shown in FIG. 1 , the gate structure 130 includes a first gate portion 132, a second gate portion 134, and a third gate portion 136. The first gate portion 132 is located between the tip drain portion 126 and the horizontal source portion 112 in the Y direction. The second gate portion 134 is located between the tip source portion 116 and the horizontal drain portion 122 in the Y direction. The third gate portion 136 is located between a vertical source portion and a vertical drain portion in the X direction.

It should be noted that additional operations may be provided before, during, or after the method 400, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of the method 400. For example, a gate dielectric layer may be deposited to form a metal insulator semiconductor (MIS) structure, a gate recess or p-type gallium nitride epitaxial layer may be formed to form an enhancement mode (E-mode) device, and various inter-layer dielectric (ILD) layers and interconnect structures may be formed.

The above text summarizes the features of various embodiments or examples, so that those with ordinary knowledge in the art can better understand the present disclosure. Those with ordinary knowledge in the art should understand that they can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and/or achieve the same advantages as the embodiments or examples introduced herein. Those with ordinary knowledge in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure.

100: semiconductor device 101: epitaxial structure 102: substrate 103: buffer layer 104: channel layer 105: barrier layer 106: passivation layer 110: source structure 112: horizontal source portion 114: flat end source portion 116: pointed source portion 120: drain structure 122: horizontal drain portion 124: flat end drain portion 126: pointed drain portion 130: gate structure 132: first gate portion 134: second gate portion 136: third gate portion 140: insulating layer 142: First insulating portion 144: Second insulating portion 146: Third insulating portion 150: Field plate structure 152: First field plate portion 154: Second field plate portion 156: Third field plate portion 400: Method 402-416: Operation

The present disclosure can be better understood from the following embodiments and drawings. It should be emphasized that, in accordance with standard industry practices, various features are not drawn to scale and are used for illustrative purposes only. FIG. 1 is a top view of a portion or the entirety of an exemplary semiconductor device according to some embodiments of the present disclosure. FIG. 2A is a cross-sectional view of a semiconductor device along line segment A-A’ of FIG. 1 according to some embodiments of the present disclosure. FIG. 2B is a cross-sectional view of a semiconductor device along line segment B-B’ of FIG. 1 according to some embodiments of the present disclosure. FIG. 2C is a cross-sectional view of a semiconductor device along line segment C-C’ of FIG. 1 according to some embodiments of the present disclosure. FIG. 2D is a cross-sectional view of a semiconductor device along line segment D-D’ of FIG. 1 according to some embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional view of a semiconductor device along line segment C-C' in FIG. 1 according to other embodiments of the present disclosure. FIG. 4 is a flow chart of a method for forming a semiconductor device according to some embodiments of the present disclosure.

TWI846645B_112144931_SEQL.xml

100:Semiconductor devices

101: Epitaxial structure

102: Substrate

103: Buffer layer

104: Channel layer

105: Barrier layer

106: Passivation layer

114: Flat-end source part

126: Tip drain part

136: The third gate part

142: First insulation part

144: Second insulation part

152: The first board part

Claims (9)

A semiconductor device comprises: a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a source structure disposed on the barrier layer, the source structure comprising a horizontal source portion extending along a first direction, and at least one vertical source portion extending along a second direction perpendicular to the first direction; a drain structure disposed on the barrier layer, the drain structure comprising a horizontal drain portion extending along the first direction and at least one vertical drain portion extending along the second direction, wherein each of the at least one vertical drain portion comprises a tip drain portion and a drain portion connected to the water A flat drain portion and a flat end drain portion of the tip drain portion; a gate structure disposed above the barrier layer and disposed between the source structure and the drain structure; a field plate structure disposed above the barrier layer, wherein the field plate structure contacts and surrounds the drain structure; and an insulating layer disposed above the barrier layer, wherein at least a portion of the tip drain portion is disposed above the insulating layer, and a first field plate portion of the field plate structure contacting the tip drain portion is also disposed above the insulating layer, and a second field plate portion of the field plate structure contacting the flat end drain portion is not disposed above the insulating layer. The semiconductor device of claim 1 further includes a passivation layer, the passivation layer is disposed above the barrier layer, wherein the insulating layer includes a first insulating portion directly disposed on the barrier layer and a second insulating portion directly disposed on the passivation layer. A semiconductor device as claimed in claim 2, wherein at least a portion of the tip drain portion is disposed on the first insulating portion, and the first field plate portion is disposed on the second insulating portion. A semiconductor device as claimed in claim 3, wherein the second field plate portion is directly disposed on the passivation layer, so that the first field plate portion and the second field plate portion form a stepped structure. A semiconductor device as claimed in claim 4, wherein: the insulating layer further includes a third insulating portion disposed on the second insulating portion; and the field plate structure further includes a third field plate portion disposed on the third insulating portion, so that the third field plate portion, the first field plate portion and the second field plate portion form a stepped structure. A method for forming a semiconductor device, comprising: providing an epitaxial structure, the epitaxial structure comprising a substrate, a channel layer above the substrate, and a barrier layer above the channel layer; forming a passivation layer above the barrier layer; patterning the passivation layer to form a source trench and a drain trench exposing the barrier layer; forming an insulating layer on a portion of the barrier layer in the drain trench and on a portion of the passivation layer, wherein the insulating layer comprises a first insulating portion in the drain trench and a second insulating portion on the passivation layer; forming a source structure in the source trench, and forming a source structure in the drain trench; A drain structure, wherein the drain structure includes a horizontal drain portion extending along a first direction and a vertical drain portion extending along a second direction perpendicular to the first direction, and the vertical drain portion includes a tip drain portion and a flat end drain portion connecting the horizontal drain portion and the tip drain portion, and at least a portion of the tip drain portion is formed on the first insulating portion; and a field plate structure is formed on the insulating layer and the passivation layer, wherein the field plate structure includes a first field plate portion in contact with the tip drain portion, and a second field plate portion in contact with the flat end drain portion. A method for forming a semiconductor device as claimed in claim 6, wherein the first field plate portion of the field plate structure is disposed on the second insulating portion, and the second field plate portion of the field plate structure is disposed on the passivation layer, so that the first field plate portion and the second field plate form a stepped structure. A method for forming a semiconductor device as claimed in claim 7, wherein: the insulating layer further includes a third insulating portion disposed on the second insulating portion; and the field plate structure further includes a third field plate portion disposed on the third insulating portion, so that the third field plate portion, the first field plate portion and the second field plate portion form a stepped structure. A method for forming a semiconductor device as claimed in claim 6, wherein the source structure includes a horizontal source portion extending along the first direction and a vertical source portion extending along the second direction, and the method for forming the semiconductor device further includes: forming a gate trench in the passivation layer; and forming a gate structure in the gate trench, wherein the gate structure includes a first gate portion between the horizontal source portion and the tip drain portion of the vertical drain portion, and a second gate portion between the vertical source portion and the vertical drain portion.

Images