TW201806153A - Semiconductor transistor and processing method thereof - Google Patents

Abstract

HEMT having a drain field plate is provided. The drain field plate is formed in the area between the gate and drain of a HEMT. The drain field plate includes a metal pad that has a larger projection area than the drain pad. The drain field plate and semiconductor layer disposed beneath the drain field plate form a metal-semiconductor (M-S) Schottky structure. The capacitance of the M-S Schottky structure generates capacitance in the semiconductor area, which increases the breakdown voltage of the transistor components of the HEMT. A portion of the substrate under the active area may be removed to thereby increase the heat conductivity and reduce the junction temperature of the transistor components of the HEMT.

Description

Semiconductor transistor and processing method thereof

The present application claims priority to U.S. Provisional Patent Application No. 62/334, No.

The present invention relates to semiconductor devices, and more particularly to high speed electron mobility transistors.

High-Speed Electron Mobility Transistor (HEMT), also known as Heterojunction FET (HFET) or Modulated Doped FET (MODFET), is a field effect transistor (FET) in field effect transistors, channel layers and electrons. A heterojunction is formed between the barrier layers having a lower affinity than the channel layer. HEMT transistors can operate at higher frequencies than ordinary transistors, up to millimeter wave frequencies, and are commonly used in high frequency and high power products, such as power between mobile phones and phase array lasers in military applications. Amplifier.

In general, a HEMT for radio frequency (RF) range operation requires a higher breakdown voltage than a conventional transistor, where the breakdown voltage is the maximum voltage that the gate of the transistor can handle. In existing HEMTs, the source connected to the gate field plate has been used to increase the breakdown voltage. However, with the advent of modern mobile communication technologies, the demand for HEMTs with higher breakdown voltages continues to increase. In addition, in order to achieve good linearity, the capacitance (Cgd) value between the gate and the drain needs to be kept stable in the dynamic driving range.

In addition, HEMTs designed to operate at high power ranges may generate high thermal energy. Therefore, in order to deliver large currents to the load, they need to be designed for low output resistance, as well as good junction insulation to withstand high voltages. Since most of the heat is generated at the heterojunction, the area of the junction can be made as large as possible, so that the heat can be dissipated very quickly, thereby preventing overheating. However, in many high power applications, the HEMT formation factor may impose limits on the size of the device area, thereby limiting the maximum power that the HEMT can handle.

Therefore, HEMTs with high breakdown voltages, smooth Cgd values in the dynamic drive range, and enhanced heat dissipation mechanisms are needed to increase the maximum voltage, linearity, and power rating for various applications, particularly in the RF range.

In an embodiment, a bungee field plate is formed on the drain of the HEMT. The flip field plate includes a metal pad having a larger projection area than the drain pad. The field plate reduces the electric field strength generated by the gate side drain pads, causing the breakdown voltage of the HEMT to increase.

In an embodiment, the flip field plate is formed by depositing a SiN passivation layer, patterning a SiN passivation layer, and depositing a metal layer on the patterned SiN layer. The drain field plate and the underlying semiconductor layer form a metal-semiconductor (M-S) Schottky structure that produces a depletion layer in the semiconductor, wherein the depletion layer increases the breakdown voltage of the HEMT. Moreover, by changing the shape of the field plate, the capacitance between the gate and the drain capacitance (Cgd) can be controlled by the capacitance between the drain and the source (Cds), thereby improving the RF characteristics of the HEMT.

In an embodiment, the HEMT is designed to reduce body leakage current and junction temperature (Tj). Upon completion of the front side processing (ie, forming a transistor element on the front side of the substrate), the back side of the substrate can be processed to enhance heat dissipation. In an embodiment, the backside processing comprises several steps. First, the portion of the substrate under the active region is removed (etched). Then, a SiN layer may be deposited on the entire back surface, wherein the thickness of the SiN layer is preferably about 35 nm. Next, a via hole is formed through the AlGaN/GaN epitaxial layer under the source. The first metal layer composed of Ti / Au may be deposited on the back surface by a suitable process such as sputtering, and may have a composite structure of Cu / Au, Cu / Au / Cu / Au or Cu / Ag / Au A second metal layer is formed on the first metal layer such that the back side of the substrate and the source on the front side are electrically connected through the via.

In an embodiment, the backside treatment may remove the substrate below the active region before the metal layer is deposited below the active region. Since a typical substrate material such as Si or sapphire has a lower thermal conductivity than a metal layer, the backside treatment can increase the thermal conductivity of the HEMT, thereby lowering the Tj of the transistor element. In an embodiment, the backside treatment may remove the substrate below the active region prior to deposition of the SiN layer. Since a typical substrate material has lower electrical insulation than SiN, backside processing can increase electrical insulation and reduce leakage current of the transistor component body.

In an embodiment, each HEMT can be cut from the wafer (ie, subjected to a single separation process) and attached to the package without the need for conventional eutectic wafer mount preforming, which reduces at least one fabrication step, Thereby reducing manufacturing costs. In an embodiment, the wafer can be attached to the package using a surface mount component (SMD) reflow process.

In general, conventional wafer bonding processes must encounter air void problems in which air voids reduce thermal conductivity and adversely affect the reliability of the transistor. In an embodiment, a solder paste is deposited on the back side to fill the vias and recessed areas of the substrate, thereby avoiding the formation of air voids during the wafer bonding process.

In the following description, for purposes of explanation, specific details However, it is apparent that those skilled in the art can practice the invention without these details. Moreover, those of ordinary skill in the art will recognize that the embodiments of the present disclosure described below can be implemented in various ways, such as a process, apparatus, system, apparatus, or method on a tangible computer readable medium.

It will be understood by those of ordinary skill in the art that: (1) certain steps may be selectively performed; (2) steps may not be limited to the specific order specified herein; and (3) certain steps may be performed in a different order, Including simultaneous.

The elements/components shown in the drawings are illustrative of the exemplary embodiments of the present disclosure and are intended to avoid obscuring the disclosure. The description of the "one embodiment", "the preferred embodiment", "an embodiment" or "the embodiment" in this specification means that the specific features, structures, features or functions described in connection with the embodiments are included in at least one. In an embodiment, and in more than one embodiment. The appearances of the phrase "in one embodiment", "in an embodiment" or "in the embodiment" are not necessarily referring to the same embodiment. The terms "including", "comprising", "including" and "including" are to be understood as an open term, and any list below is an example and is not limited to the listed items. Any headings used herein are for organizational purposes only and are not intended to limit the scope of the specification or patent application. In addition, some terms are used in various places in the specification for the purpose of illustration and should not be construed as limiting.

Embodiments of the present disclosure include a bungee field plate for increasing the breakdown voltage of the HEMT. In addition, the baffle field plate can be used to increase or decrease the Cgd and/or Cd of the HEMT, maintain a smooth Cgd value, and enhance the RF characteristics of the HEMT.

Embodiments of the present disclosure include a process of removing a portion of a substrate below the active region to increase thermal conductivity and reduce the junction temperature of the components of the HEMT.

Embodiments of the present disclosure include a process of removing a portion of a substrate under the active region and depositing a SiN layer. Since the SiN layer has better electrical insulation properties than the substrate material, the process can reduce the body leakage current of the components of the HEMT.

Embodiments of the present disclosure include a process of removing a portion of a substrate below a active region and depositing a metal layer. Since the metal layer has better thermal conductivity than the substrate material, the process can increase the thermal conductivity and lower the junction temperature of the components of the HEMT.

Embodiments of the present disclosure include a process of removing a portion of a substrate below the active region and forming a via, wherein a metal layer is deposited in the via. These processes can reduce the source inductance of the HEMT.

Embodiments of the present disclosure include a process of removing a portion of a substrate under the active region to deposit a metal layer and applying a solder paste to the back side of the wafer, thereby avoiding the formation of air voids, thereby enhancing the heat transfer characteristics of the HEMT element and reducing Junction temperature of the HEMT component.

Embodiments of the present disclosure include a process of removing a portion of a substrate under the active region to deposit a metal layer and applying solder paste to the back side of the wafer. These processes can eliminate conventional preforming processes (e.g., eutectic wafer placement processes) for attaching HEMT wafers to packages, which can reduce manufacturing costs.

Embodiments of the present disclosure include a process of removing a portion of a substrate under the active region to deposit a metal layer and applying solder paste to the back side of the wafer. Thus, the HEMT wafer can be attached to the package using a eutectic wafer mount process or an SMD reflow process.

1 through 5 illustrate an exemplary process for forming a HEMT element on the front (or top) side of a substrate in accordance with an embodiment of the present invention. As shown in Fig. 1, an epitaxial layer 102 is formed on the front (top) side of the substrate 100, and the substrate 100 may preferably be formed of Si or sapphire, although other suitable materials may be used for the substrate. The epitaxial layer 102 may be formed of GaN to form an AlGaN/GaN heterostructure layer on the substrate. It should be noted that the epitaxial layer 102 can be formed from other suitable types of materials. Hereinafter, a GaN HEMT is used as an exemplary HEMT, even though other types of HEMTs can be fabricated by the methods described in this document.

A drain may be formed on the epitaxial layer 102 (or equivalently, a drain pad or a drain electrode or an ohmic metal for the drain) 104 and 108 and a source (or equivalently, a source pad) Or source electrode or ohmic metallization for the source) 106, wherein the drain and source may be formed of a suitable metal. In an embodiment, each of the drain and the source may have a composite metal layer structure including Ti / Al / Ni / Au. The ohmic contact of the drain and the source can be produced by alloying the drain and the source, thereby reducing the electrical resistance at the interface between the drain/source and the epitaxial layer 102.

As shown in FIG. 2, an electrically insulating layer 110 may be formed on the front surface of the substrate 100. In an embodiment, the insulating layer 110 may be formed of SiN or by any other suitable material that may be used for electrical insulation. The insulating layer 110 may cover the top surface of the epitaxial layer 102, the drains 104 and 108, and the source 106 that may be damaged during the process. As described later, the SiN layer can be patterned to form a gate.

3 is a diagram showing an ion implantation process for generating an ion implantation portion (or, briefly, an implant portion) 112, wherein the implant portion 112 can be used as a separate operation unit of the HEMT, the drain electrodes 104 and 108, and The source 106 is isolated. In an embodiment, the patterned photoresist layer (not shown in FIG. 3) may be coated on the top surface of the HEMT through a suitable photolithography process and used as a photoresist (PR) mask layer to select Ions, such as nitrogen or oxygen ions, are allowed to pass through the insulating layer 110 and are implanted into the epitaxial layer 102 during the implantation process. Then, the photoresist layer is subsequently removed.

As shown in FIG. 4, one or more portions of the insulating layer 110 are etched through a suitable etching process. In an embodiment, a patterned mask layer (not shown in FIG. 4) may be formed on the insulating layer 110 through a photolithography process, and used to remove portions of the insulating layer, thereby forming the recess 116 and exposing the epitaxial layer. The top surface of the layer.

FIG. 5 illustrates a T-type gate 118 formed in the recess 116 and having wings extending over the insulating layer 110. In an embodiment, a T-type gate lithography process (not depicted in FIG. 5) may be performed, and then gate metallization is performed using a suitable metal such as Ni / Au or Ni / Pt / Au.

As shown in FIG. 6, the passivation layer 120 may be deposited on the front surface of the HEMT. In an embodiment, although the passivation layer 120 may use other suitable electrically insulating materials, the passivation layer 120 may be formed of SiN. The passivation layer 120 can increase the breakdown voltage between the T-type gate 118 and the drain/source, thereby improving the reliability of the HEMT. The wing of the T-type gate 118 and the insulating layer 110 can create a capacitance to reduce the electric field in the gate edge region on the drain side, thereby increasing the breakdown voltage of the gate 118.

Figure 7 illustrates an exemplary method of making a contact opening in accordance with an embodiment of the present invention. As shown, portions of insulating layer 110 and passivation layer 120 are removed to form contact openings (or recesses) 130, 132, and 134 and SiN contact openings (or recesses) 131 and 135. As described below, the SiN contact openings 131 and 135 may be filled with metal to form a bipolar field metal (or equivalently a bland field plate). In an embodiment, a portion of the insulating layer 110 and the passivation layer 120 may be removed using a photolithography-based etching process to expose a portion of the top surface of the epitaxial layer 102.

8 is an illustration of an exemplary process for forming a source-connected gate field metal (or, equivalently, a source-connected gate field plate) 144 and a gate field plate 140, in accordance with an embodiment of the present invention. . Figure 9 is a top plan view of a bungy field plate 140 in accordance with an embodiment of the present invention. A gate field plate (or short gate field plate) 144 and a lower layer 110 and 120 formed on the passivation layer 120 covering the passivation layer 120 of the T-type gate 118 and extending toward the drain 104 generate capacitance, wherein the capacitance is lowered. The electric field in the gate edge region of the drain side increases the breakdown voltage between the gate 118 and the drain 104. In an embodiment, the source connected gate field plate 144 may be formed from a suitable metal.

In an embodiment, the bungy field plate 140 may be formed over the drain 104 and extend beyond the edge of the drain 104. The flip field plate 140 has a similar effect to the gate field plate 144 that is connected to the source because the capacitance generated by the buck field plate 140 can increase the breakdown voltage. More specifically, the flip field plate 140, the layers 110, 120, and the epitaxial layer 102 form a metal semiconductor (M-S) structure. The M-S Schottky structure creates a capacitance that in turn creates a depletion region in the epitaxial layer 102, thereby increasing the breakdown voltage.

Generally, when an RF signal is applied to the gate 118, the edge capacitance (Cgd) between the gate 118 and the drain 104 has a negative effect on the quiescent current from the drain to the source, i.e., the quiescent current has a fluctuating transient period. In an embodiment, the capacitance generated by the M-S Schottky structure of the field plate 140 can control the edge capacitance (Cgd) so that the smoothness of Cgd can be maintained.

As shown in FIG. 9, in an embodiment, the field plate 140 relates to a metal region that covers the projection area of the drain 104 and further extends outside the projection area of the drain 104 in the x direction (hereinafter, the projection area is Refers to a two-dimensional region obtained by projecting the shape of a three-dimensional object onto an xy plane, where the xy plane is parallel to the top surface of the epitaxial layer 102. The flip field plate 140 also relates to a metal region that covers the projection area of the SiN contact opening 131 and further extends outside the projection area of the SiN contact opening 131 in the x and y directions. Conversely, in a typical system, the drain contact opening 130 is filled with a metallic material and the projected area of the drain contact opening 130 does not extend outside of the projected area of the drain 104.

In an embodiment, the length D1 is the distance between the edge of the SiN contact opening 131 and the edge of the buck field plate 140 in the y direction, which is about 1 μm. The length D2 is the distance between the edge of the flip field plate 140 and the edge of the drain 104 in the y direction, which is about 1 μm. The width D3 is the size of the SiN contact opening 131 in the x direction, which is about 1 μm. The width D4 is the distance between the edge of the SiN contact opening 131 and the edge of the drain 104 in the X direction, which is about 1 μm. The width D5 is the distance between the edge of the SiN contact opening 131 and the edge of the flip field plate 140 in the x direction, which is about 1 μm. The width D6 is the distance between the edge of the SiN contact opening 131 and the edge of the field plate 140 in the x direction, which is about 3 μm. The width D7 is the distance between the edge contacting the opening region 130 in the X direction and the edge of the drain 104, which is 5 μm. It should be noted that the values of the lengths D1 to D7 are exemplary, and other suitable values may be used.

In the embodiment, even when the size of the drain 104 is changed, the ratio between the lengths D1 to D7 can be maintained. For example, when the size of the drain 104 is changed, the ratio between D6 and D7 can be kept at 1.

The field plate 140 may be formed of a plurality of metal layer structures such as Ti / Au or Ti / Au / Ti / Au. In an embodiment, the source-connected gate field plate 144 and the drain field plate 140 may be formed during the same process, that is, the patterned mask layer may be deposited through a suitable photolithography process (not shown in FIGS. 8 and 9). The source-connected gate field plate 144 and the drain field plate 140 are thus deposited, and the contact opening regions 130, 132, and 134 may be filled with the same metal material during the same process.

Figure 10 is a top plan view of a bungee field plate in accordance with another embodiment of the present invention. As shown, the flip field plate 150 can include three plates 401, 402, and 403, wherein the plates 401 and 403 are electrically separated from the plate 402, and the plate 402 is electrically coupled to the drain 104. The plate 402 includes a metal layer filling the contact opening region 130, and the plates 401 and 403 respectively include a metal layer filling the two SiN contact openings 131.

In the embodiment, the widths D10, D11, and D12 are similar to the widths D5, D3, and D4 in Fig. 9, each of which is about 1 μm. Likewise, the lengths D13 and D14, which are similar to D2 and D1, respectively, are about 1 μm.

As shown in Fig. 10, the sides of the field plates 401, 402, and 403 may be interdigitated. For example, the lengths D15 to D17 and D19 to D23 associated with the protruding/recessed portions of the interdigitated portion may be about 1 μm, respectively. The length D18 is the distance between the edge of the drain 104 and the edge of the contact opening region 130 in the x direction, and may be about 5 μm.

In an embodiment, the bucker field plates 140, 401, 402, and 403 may have other suitable shapes such that the MS Schottky structure may have a control of Cgd and/or Cgs (edge capacitance between the gate and the source). Expected capacitance. In an embodiment, the shape of the bungy field plate and the distance between the buck field plate and the edge of the drain 104 can be adjusted to achieve the desired capacitance. In an embodiment, the interdigital capacitor is open to the DC signal, but becomes electrically shorted for the RF signal, which causes the interdigital capacitor to selectively operate in response to the RF signal. It should be noted that the top view of the flip field plate 142 and the SiN contact opening 135 has the same configuration as that of FIGS. 9 and 10, that is, the bungy field plate 142 may have the same shape as the bungee field plate 140, or the buck field plate 142. There may be three metal plates similar to the metal plates 401, 402 and 403.

Figure 11 is a diagram showing an exemplary process for plating a metal layer on a transistor element in accordance with an embodiment of the present invention. As shown, the metal components 160, 162, and 164 can be deposited on the drain and source through an electroplating process such as an Au plating process such that the components can be electrically connected through an air bridge or bond pad process.

12 and 13 illustrate an exemplary process for depositing an etched portion of electrically insulating layer 166 and insulating layer 166 in accordance with an embodiment of the present invention. As shown, the insulating layer 166 is partially etched such that the metal components (bond pads) 160, 162, and 164 have contact openings 170, 172, and 174, respectively, for connecting the wires thereto. For example, in an embodiment, the ends of the wires can be bonded to the contact openings 170 (wire bonds) such that electrical signals from/transmitted to the wires can be transmitted to/from via the metal components (joint pads) and the baffle field plate 140 Bungee 104.

14 to 24 illustrate the processing of the back surface (bottom side) of the substrate 100 and the epitaxial layer 102. Figure 14 is a diagram showing an exemplary process for thinning a wafer in accordance with an embodiment of the present invention. As shown, the substrate 100 can be thinned by a suitable process such as grinding and polishing to facilitate assembly of the HEMT into the package and backside processes, such as the creation and separation of vias.

Figure 15 is a diagram showing an exemplary process for substrate etching in accordance with an embodiment of the present invention. As shown, a portion of the substrate 100 below the active region 203 can be removed by a suitable process, such as dry etching or wet etching. Here, the active region 203 refers to an area under active semiconductor elements such as a drain, a gate, and a source that generate thermal energy during operation. Then, as shown in Fig. 16, an electrically insulating layer 204 such as a SiN layer may be deposited on the back (or bottom) surface of the substrate.

Figure 17 is a diagram showing an exemplary process for creating a through hole 306 in accordance with an embodiment of the present invention. As shown, in an embodiment, the through holes 306 can extend to the bottom side of the source 106. As shown, the insulating layer 204 and the epitaxial layer 102 can be etched through a suitable etch process to form the vias 306, wherein the vias 306 can be slit vias.

Figure 18 illustrates an exemplary process for depositing a metal layer 206 on the back side of a substrate in accordance with an embodiment of the present invention. In an embodiment, a sputtering process can be used to deposit a metal layer formed of Ti / Au, for example, over the back side of the substrate, although other suitable processes can be used to deposit the metal layer 206.

Figure 19 illustrates an exemplary process for plating a metal layer 208 on the back side of a substrate in accordance with an embodiment of the present invention. In an embodiment, metal layer 206 can be a seed layer for metal layer 208. In an embodiment, the metal layer 208 may be deposited by a suitable process (eg, an electroplating process), and the metal layer 208 may have a composite metal structure such as Cu / Au / Cu / Au and Cu / Ag / Au.

Figure 20 illustrates an exemplary process for applying solder paste 208 to the back side of a substrate in accordance with an embodiment of the present invention. As shown, the solder paste 208 can fill the via 306 and the recess of the substrate 100 below the active region 203.

As noted above, the portion of the substrate below the active region 203 can be removed prior to deposition of the metal layers 206 and 208. Since the substrate material such as Si or sapphire may have a lower thermal conductivity than the metal layers 206 and 208, the processes of FIGS. 15-20 may increase the thermal conductivity of the HEMT, thereby reducing the Tj of the transistor elements in the active region 203. Likewise, since typical substrate materials have lower electrical insulation than SiN, backside processing increases electrical insulation, thereby reducing body leakage current of the transistor elements.

Figure 21 is a diagram showing an exemplary process for backside processing of a HEMT wafer in accordance with an embodiment of the present invention. The HEMT in FIG. 21 is similar to the HEMT in FIG. 17, except that the HEMT in FIG. 21 has a plurality of sources 310, 314 that are connectable to each other through an air bridge (not shown in FIG. 21). 318. For example, in an embodiment, the vias 302 and 304 can electrically connect the sources 310 and 318 to the bottom side of the HEMT, wherein the vias 302 and 304 can be external to the active region 309. As shown, an insulating layer (e.g., SiN layer) 301, substrate 300, epitaxial layer 305, and ion implantation region 307 can be etched through a suitable etch process to form vias 302 and 304.

It should be noted that only three sources are shown in FIG. However, it will be apparent to those of ordinary skill in the art that other suitable numbers of sources may be connected to each other through an air bridge. In addition, only two general through holes are shown in Fig. 21, but other suitable numbers of through holes may be formed.

Figure 22 illustrates an exemplary process for depositing a metal layer 330 on the back side of a substrate in accordance with an embodiment of the present invention. In an embodiment, a metal layer formed, for example, of Ti / Au may be deposited on the back side of the substrate using a sputtering process.

Figure 23 illustrates an exemplary process for depositing a metal layer 332 on the back side of a substrate in accordance with an embodiment of the present invention. In an embodiment, metal layer 330 can be a seed layer of metal layer 332. In an embodiment, the metal layer 332 may be deposited by a suitable process (eg, an electroplating process), and the metal layer 332 may have a composite metal structure such as Cu / Au / Cu / Au and Cu / Ag / Au.

Figure 24 illustrates an exemplary process for applying solder paste 334 to the back side of a wafer in accordance with an embodiment of the present invention. As shown, the solder paste 334 can fill the vias 302 and 304 below the active region 309 and the recessed portions of the substrate 300.

Embodiments of the present disclosure include a process of removing (etching) a portion of the substrate 100 or 300 under the active region 203 or 309 and depositing a metal layer. Since the metal layer has better thermal conductivity than typical substrate materials, these processes may increase the dissipation of heat generated during operation of the HEMT device.

Embodiments of the present disclosure include a process of removing (etching) a portion of a substrate under the active region to deposit a metal layer and applying solder paste 220 or 334 to the back surface, which avoids the formation of air voids, thereby enhancing the heat transfer characteristics of the HEMT device and Lower the junction temperature of the HEMT component.

Embodiments of the present disclosure include a process of removing (etching) a portion of a substrate under the active region and depositing a SiN layer 204 or 301. Since the SiN layer has better electrical insulation properties than typical substrate materials, this process may reduce the body leakage current of the HEMT device.

In an embodiment, each of the HEMTs of Figures 20 and 24 can be diced (singulated) from the wafer and attached to the package by heating (ie, reflowing) the solder paste 220 or 334 (not drawn in Figures 20 and 24) Show). Conversely, in a common method, a solder paste containing a eutectic metal is coated on a ceramic package or lead frame prior to wafer attachment. Thus, in an embodiment, preforming of a common eutectic material is not required, thereby reducing at least one manufacturing step, thereby reducing manufacturing costs. In an embodiment, the wafer can be attached to the package using a surface mount component (SMD) reflow method.

One or more of the processes described in connection with Figures 1 through 24 can be performed by computer software. It should be noted that embodiments of the present disclosure may also relate to a computer product having a non-transitory tangible computer readable device having computer code thereon for performing various computer implemented operations. The tools and computer code may be specially designed and constructed for the purposes of the present disclosure, or they may be of the kind known or available to those of ordinary skill in the art. Examples of tangible computer readable tools include, but are not limited to, magnetic tools such as hard disks, floppy disks, and magnetic tape; optical tools such as CD-ROMs and hologram devices; magneto-optical devices; and dedicated for storage or storage and execution Program hardware devices such as special application integrated circuits (ASICs), programmable logic devices (PLDs), flash memory, and ROM and RAM devices. Examples of computer code include instruction codes such as those produced by a compiler and files containing higher level code executed by a computer using a translator. Embodiments of the present disclosure may be implemented, in whole or in part, as machine executable instructions that may be in a program module executed by a process device. Examples of program modules include libraries, programs, routines, objects, components, and data structures. In a distributed computing environment, program modules can be physically located locally, remotely, or both.

Those of ordinary skill in the art will appreciate that the key to the present disclosure is that it can be implemented without the use of a computer system or programming language. Those of ordinary skill in the art will also appreciate that many of the above-described elements can be physically and/or functionally divided into sub-modules or combined.

It is to be understood that the foregoing examples and embodiments are illustrative, and are not intended to limit the scope of the disclosure. All of the permutations, enhancements, equivalents, combinations and improvements included in the true spirit and scope of the disclosure are apparent to those of ordinary skill in the art.

100‧‧‧Substrate
102‧‧‧ epitaxial layer
104, 108‧‧‧汲polar
106‧‧‧ source
110‧‧‧Insulation
112‧‧‧ Implant Department
116‧‧‧ dent
118‧‧‧ gate
120‧‧‧ Passivation layer
130‧‧‧Contact opening area
131, 132, 134‧ ‧ contact openings
135‧‧‧SiN contact opening
140, 142‧‧‧汲 pole field board
144, 146‧‧ ‧ gate field plate
166‧‧‧Insulation
203‧‧‧active area
204‧‧‧Insulation, SiN layer
206, 208‧‧‧ metal layer
220‧‧‧ solder paste
300‧‧‧Substrate
301‧‧‧Insulation
302, 304, 306‧‧‧through holes
305‧‧‧Elevation layer
307‧‧‧ implanted area
309‧‧‧active area
310, 314, 318‧‧‧ source
330, 332‧‧‧ metal layer
334‧‧‧ solder paste
401, 402, 403‧‧‧ boards, 汲 field plates

Reference will be made to embodiments of the invention, examples of which may be illustrated in the accompanying drawings. These drawings are intended to be illustrative, and not restrictive. Although the present invention has been generally described in the context of these embodiments, it should be understood that the scope of the invention is not limited to the specific embodiments.

1 to 5 are diagrams showing an exemplary process of forming a semiconductor element on the front surface of a substrate in accordance with an embodiment of the present invention.

Figure 6 is a diagram showing an exemplary process for depositing a passivation layer in accordance with an embodiment of the present invention.

Figure 7 illustrates an exemplary process for forming a contact opening in accordance with an embodiment of the present invention.

Figure 8 illustrates an exemplary process for forming a gate field plate and a bungee field plate in accordance with an embodiment of the present invention.

Figure 9 is a top plan view of a bungee field plate in accordance with an embodiment of the present invention.

Figure 10 is a top plan view of a bungee field plate in accordance with an embodiment of the present invention.

Figure 11 is a diagram showing an exemplary process for plating a metal layer on a transistor element in accordance with an embodiment of the present invention.

12 and 13 are diagrams showing an exemplary process of depositing an electrically insulating layer and etching a portion of the insulating layer in accordance with an embodiment of the present invention.

Figure 14 is a diagram showing an exemplary process for thinning a wafer in accordance with an embodiment of the present invention.

Figure 15 is a diagram showing an exemplary process for etching a substrate in accordance with an embodiment of the present invention.

Figure 16 is a diagram showing an exemplary process for depositing a SiN layer in accordance with an embodiment of the present invention.

Figure 17 is a diagram showing an exemplary process for creating a through hole in accordance with an embodiment of the present invention.

Figure 18 is a diagram showing an exemplary process for depositing a metal layer on the back side of a wafer in accordance with an embodiment of the present invention.

Figure 19 is a diagram showing an exemplary process for depositing a metal layer on the back side of a wafer in accordance with an embodiment of the present invention.

Figure 20 illustrates an exemplary process for applying solder paste to the back side of a wafer in accordance with an embodiment of the present invention.

Figure 21 is a diagram showing an exemplary process for processing the back side of a HEMT wafer in accordance with an embodiment of the present invention.

Figure 22 illustrates an exemplary process for depositing a metal layer on the back side of a wafer in accordance with an embodiment of the present invention.

Figure 23 is a diagram showing an exemplary process for depositing a metal layer on the back side of a wafer in accordance with an embodiment of the present invention.

Figure 24 illustrates an exemplary process for applying solder paste to the back side of a wafer in accordance with an embodiment of the present invention.

100‧‧‧Substrate

104, 108‧‧‧汲polar

106‧‧‧ source

110‧‧‧Insulation

112‧‧‧ Implant Department

118‧‧‧ gate

120‧‧‧ Passivation layer

140, 142‧‧‧汲 pole field board

144, 146‧‧ ‧ gate field plate

Claims (20)

A semiconductor transistor comprising: an epitaxial layer; a drain formed on the epitaxial layer; an insulating layer formed on the epitaxial layer and on a top surface of the drain Outside the first contact opening region, covering the drain; and a flip field plate formed of a conductive material and disposed on a partial region of the insulating layer and the first contact opening region, thereby being capable of being in the first contact The open area directly contacts the drain, the flip field plate having a projection area extending beyond a projection area of the drain. The semiconductor transistor according to claim 1, further comprising a passivation layer formed of a conductive material and disposed between the insulating layer and the drain field plate and on a top surface of the drain The drain is covered by the outside of the first contact opening region. The semiconductor transistor according to claim 2, wherein the passivation layer and the insulating layer have at least one second contact opening region disposed on the side of the drain, and the dipole field plate is formed on the at least a second contact opening region, so that the epitaxial layer can be directly contacted in the at least one second contact opening region. The semiconductor transistor according to claim 1, wherein the epitaxial layer comprises gallium nitride, and the semiconductor electro-crystal system is a high-speed electron mobility transistor (HEMT). The semiconductor transistor according to claim 1, further comprising: a gate formed on the epitaxial layer, the insulating layer covering a top surface of the gate; and a gate field plate, It is formed on the insulating layer and is disposed above the gate. The semiconductor transistor according to claim 1, further comprising: a metal component directly disposed on the drain field plate; and an insulating layer covering the metal component and included in the metal component One of the top surfaces contacts the open area. A semiconductor transistor comprising: an epitaxial layer; a drain formed on the epitaxial layer; an insulating layer formed on the epitaxial layer and the drain, the insulating layer having the drain a first contact opening region on the top surface, and a second contact opening region on the top surface of the epitaxial layer; and a flip field plate comprising a first metal plate and a second metal plate The first metal plate is disposed on a portion of the insulating layer and the first contact opening region, so that the first contact opening region can directly contact the drain, and the second metal plate is disposed on the insulating layer a portion of the region and the second contact opening region are configured to directly contact the epitaxial layer, and the first metal plate and the second metal plate are separated from each other. The semiconductor transistor according to claim 7, wherein the first metal plate and the second metal plate have convex and concave portions disposed in an interdigitated manner. The semiconductor transistor according to claim 7, further comprising: a passivation layer formed of an electrically insulating material and disposed between the insulating layer and the dipole field plate. The semiconductor transistor according to claim 7, wherein the epitaxial layer comprises gallium nitride, and the semiconductor electro-crystal system is a high-speed electron mobility transistor (HEMT). The semiconductor transistor according to claim 7, further comprising: a gate formed on the epitaxial layer, the insulating layer covering a top surface of the gate; and a gate field plate, It is formed on the insulating layer and is disposed above the gate. The semiconductor transistor according to claim 7, further comprising: a metal component directly disposed on the flip field field; and an insulating layer covering the metal component and having the metal component One of the top surfaces contacts the open area. A method of processing a semiconductor transistor, the semiconductor transistor comprising a substrate; an epitaxial layer; and a plurality of transistor elements formed on the epitaxial layer, the method comprising: removing a portion of the substrate, the method The substrate is disposed under one of the plurality of transistor elements to expose a portion of the bottom surface of the epitaxial layer; forming an insulating layer on the exposed portion of the bottom surface of the epitaxial layer, the insulating layer Forming an electrically insulating material; forming at least a uniform hole extending from a bottom surface of the insulating layer to a bottom surface of at least one of the plurality of transistor elements; and depositing at least one metal layer on a bottom surface of the insulating layer On the sidewall of the via, and on the bottom surface of at least one of the plurality of transistor elements. The method of claim 13, further comprising: applying a solder paste on a bottom surface of the at least one metal layer. The method of claim 13, wherein the depositing the at least one metal layer comprises: depositing a first metal layer on a bottom surface of the insulating layer, on a sidewall of the through hole, and Depositing a second metal layer on a bottom surface of each of the plurality of transistor elements; and depositing a second metal layer on a bottom surface of the first metal layer. The method of claim 13, wherein the at least one metal layer has a higher thermal conductivity than the substrate. A semiconductor transistor comprising: an epitaxial layer; a plurality of transistor elements formed on a top surface of one of the epitaxial layers; a substrate formed on a bottom surface of the epitaxial layer and disposed An area outside the region below the portion of the plurality of transistor elements; an insulating layer formed of an electrically insulating material and disposed on a bottom surface of the substrate and a portion of the epitaxial layer a surface of at least one of the bottom surface of the insulating layer extending through the epitaxial layer to at least one of the bottom surfaces of the plurality of transistor elements; at least one metal layer formed on the insulating layer a bottom surface of one of the layers, a sidewall of the at least one of the uniform holes, and at least one of the bottom surfaces of the plurality of transistor elements; and a solder paste formed on a bottom surface of the at least one metal layer. The semiconductor transistor according to claim 17, further comprising: a solder paste applied to a bottom surface of the at least one metal layer. The semiconductor transistor according to claim 17, wherein the at least one metal layer comprises: a first metal layer formed on the bottom surface of the substrate, the sidewall of the at least consistent hole, and at least a bottom surface of the plurality of transistor elements; and a second metal layer formed on a bottom surface of the first metal layer. The semiconductor transistor according to claim 17, wherein the semiconductor electro-crystal system is a high-speed electron mobility transistor (HEMT).