TWI812573B - Semiconductor device and forming method thereof - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate; a channel layer over the substrate; a barrier layer over the channel layer; a source structure disposed on the barrier layer and including a horizontal source portion and a vertical source portion; a drain structure disposed on the barrier layer and including a horizontal drain portion and a vertical drain portion, wherein a tip source portion of the vertical source portion directs to the horizontal drain portion, and wherein a tip drain portion of the vertical drain portion directs to the horizontal source portion; a gate structure disposed on the barrier layer, the gate structure includes a a first gate portion disposed between the tip drain portion and the horizontal source portion, and a second gate portion disposed between the vertical drain portion and the vertical source portion; and a blocking structure disposed on the barrier layer, wherein the blocking structure is between the tip drain portion and the first gate portion.

Description

Semiconductor device and method of forming same

The present disclosure relates to a semiconductor device, and in particular to a semiconductor device in which a barrier structure is provided between a drain tip and a gate structure to suppress hot carriers.

With the development of semiconductor technology, the market is no longer satisfied with traditional silicon transistors. In high-power applications and high-frequency applications, compound semiconductors of the III-V family have shown the potential to replace silicon transistors. In recent years, High Electron Mobility Transistor (HEMT) made of gallium nitride (GaN) has attracted special attention.

When operating the current GaN HEMT, the tip portion (commonly known as the fingertip) of the vertical part of the drain structure (commonly known as the finger) will generate more hot carriers (hot carriers) due to the higher electric field. carrier). Once the operation time is extended, the accumulated hot carriers will degrade the performance of the HEMT device or even damage the HEMT device. Therefore, a novel HEMT structure is needed to prevent the accumulation of hot carriers at the tip portion of the drain structure to avoid causing damage to the HEMT device.

Embodiments of the present disclosure provide a semiconductor device, including a substrate; a channel layer disposed above the substrate; a barrier layer disposed above the channel layer; and a source structure disposed above the barrier layer, including a horizontal source portion and a vertical source and a drain structure disposed above the barrier layer, including a horizontal drain portion and a vertical drain portion, wherein the tip source portion of the vertical source portion points to the horizontal drain portion, and the tip drain portion of the vertical drain portion part pointing to the horizontal source part. The semiconductor device further includes a gate structure disposed above the barrier layer, including a first gate portion disposed between a tip drain portion and a horizontal source portion and a first gate portion disposed between a vertical drain portion and a vertical source portion. a second gate portion; and a barrier structure disposed above the barrier layer, wherein the barrier structure is between the tip drain portion and the first gate portion.

Embodiments of the present disclosure provide a semiconductor device, including a substrate; a channel layer disposed above the substrate; a barrier layer disposed above the channel layer; and a source structure disposed above the barrier layer, including a horizontal a source portion and a plurality of vertical source portions extending along a second direction, wherein the second direction is perpendicular to the first direction; and a drain structure disposed above the barrier layer, including a horizontal drain extending along the first direction and a plurality of vertical drain portions extending along a second direction, wherein the horizontal source portions and the horizontal drain portions are spaced apart from each other along the second direction, and the plurality of vertical source portions and the plurality of vertical drain portions extend along the first direction. Intertwined with each other. The above-mentioned semiconductor device further includes a gate structure disposed above the barrier layer, including a plurality of first gate portions, a plurality of second gate portions and a plurality of third gate portions, wherein the plurality of first gate portions are along the second direction. Disposed between a plurality of vertical drain portions and a horizontal source portion, a plurality of second gate portions are disposed between a plurality of vertical source portions and the horizontal drain portion along the second direction, and a plurality of third gate portions are disposed on between a plurality of staggered vertical source portions and a plurality of vertical drain portions, wherein a plurality of third gate portions are connected to each other by a plurality of first gate portions and a plurality of second gate portions; and disposed above the barrier layer A plurality of barrier structures, wherein the plurality of barrier structures are disposed between a plurality of first gate portions and a plurality of vertical drain portions along the second direction.

Embodiments of the present disclosure provide a method for forming a semiconductor device, including providing an epitaxial structure, including a substrate, a channel layer above the substrate, and a barrier layer above the channel layer; forming a source structure and a drain structure above the barrier layer, wherein The source structure includes a horizontal source part and a vertical source part, and the drain structure includes a horizontal drain part and a vertical drain part; a gate structure is formed above the barrier layer, including a first gate part and a second gate portion, wherein the first gate portion is between the horizontal source portion and the tip drain portion of the vertical drain portion, and the second gate portion is between the vertical source portion and the vertical drain portion; and in the resistor A barrier structure is formed above the barrier layer and between the first gate portion and the tip drain portion.

The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of the various components and arrangements of the present disclosure are described below to simplify the description. Of course, these examples are not intended to limit the disclosure. For example, if a first feature is described as being formed on or over a second feature, it may include an embodiment in which the first feature and the second feature are in direct contact, or it may include an embodiment in which additional features are formed on the first feature. and the second feature, so that there is no direct contact between the first feature and the second feature. Additionally, this disclosure may repeat reference numbers and/or letters in various examples. This repetition is for simplicity and clarity and does not inherently define the relationship between the various embodiments and/or configurations discussed.

Furthermore, this disclosure may use spatially relative terms, such as “below,” “below,” “below,” “above,” “above,” and similar words to facilitate describing one of the diagrams. The relationship between an element or feature and other elements or features. In addition to the orientation depicted in the drawings, spatially relative terms are also intended to cover different orientations of the device in use or operation. The device may be rotated 90 degrees or at other orientations and the spatially relative terms used herein interpreted accordingly.

Furthermore, unless specifically denied, the singular includes the plural and vice versa. Furthermore, the present disclosure is not limited to the order of operations or events shown, as some operations can occur in a different order and/or concurrently with other operations or events. Furthermore, not all operations or events illustrated are required to implement the methods disclosed.

Due to the polarization effect of the aluminum gallium nitride/gallium nitride (AlGaN/GaN) structure, the GaN high electron mobility transistor (HEMT) inherently has a two-dimensional electron gas (2DEG) that can serve as a transistor channel. This is GaN HEMTs bring many benefits. However, such congenitally existing transistor channels may cause some problems in non-channel areas where channels are not required, such as along the length of the vertical portion of the drain structure (i.e., the finger portion). For example, since the tip portion (i.e., the fingertip portion) of the vertical portion of the drain structure has a higher electric field, the current flowing from the tip portion of the drain toward the source in the length direction will produce a higher concentration. of hot carriers. As the operation time increases, the accumulation of these hot carriers may degrade the performance of the HEMT device or even cause damage to the HEMT device.

In order to solve the above problems, the present disclosure provides a semiconductor device and a manufacturing method thereof to suppress the generation of hot carriers at the tip portion of the drain structure and further avoid impairing the performance of the HEMT device or causing damage to the HEMT device. In this way, the robustness and reliability of the HEMT device can be increased.

FIG. 1 is a top view of a portion or the entirety of an exemplary semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 may be a single transistor device or an array of multiple transistor devices, such as a GaN HEMT. In some embodiments, the semiconductor device 100 includes a source structure 110 , a drain structure 120 and a gate structure 130 disposed above an epitaxial structure (eg, the epitaxial structure 101 described below).

In some embodiments, source structure 110 includes horizontal source portions 112 extending along the X direction, and vertical source portions 114 (which may be referred to as finger portions of the source structure) extending along the Y direction. In the Y direction, one end of the vertical source portion 114 is connected to the horizontal source portion 112 , while the other end of the vertical source portion 114 may be referred to as a tip source portion 116 (which may be referred to as a finger of the source structure). tip part).

In some embodiments, the drain structure 120 includes a horizontal drain portion 122 extending along the X direction, and a vertical drain portion 124 extending along the Y direction (which may be referred to as the fingers of the drain structure). In the Y direction, one end of the vertical drain portion 124 is connected to the horizontal drain portion 122 , while the other end of the vertical drain portion 124 may be referred to as a tip drain portion 126 (which may be referred to as a reference to the drain structure). tip part).

In some embodiments, the horizontal source portion 112 and the horizontal drain portion 122 are spaced apart from each other along the Y direction, and the vertical source portion 114 and the vertical drain portion 124 are staggered with each other along the X direction, as shown in FIG. 1 Show. The tip source portion 116 of the vertical source portion 114 points toward the horizontal drain portion 122 along the Y direction, and the tip drain portion 126 of the vertical drain portion 124 points toward the horizontal source portion 112 along the Y direction, so the vertical source portion 114 and the length direction of the vertical drain portion 124 is in the Y direction.

In some embodiments, the gate structure 130 is disposed between the source structure 110 and the drain structure 120 and surrounds at least a portion of the source structure 110 and the drain structure 120 . For example, the gate structure 130 surrounds the vertical source portion 114 and the vertical drain portion 124, as shown in FIG. 1 . The gate structure 130 may be a continuous whole and extend continuously to be shared by a plurality of transistor devices. In some embodiments, the distance between the gate structure 130 and the source structure 110 is smaller than the distance between the gate structure 130 and the drain structure 120 . In order to make the description clear and understandable, the gate structure 130 is divided into a first gate part 132, a second gate part 134 and a third gate part 136 having the same stacked structure.

In the embodiment shown in Figure 1, the first gate portion 132 is located between the two vertical source portions 114 in the 126 pointing in the direction of the horizontal source portion 112 ) is located between the vertical drain portion 124 and the horizontal source portion 112 . The second gate portion 134 is located between the two vertical drain portions 124 in the X direction and in the Y direction (ie, the tip source portion 116 of the vertical source portion 114 points in the direction of the horizontal drain portion 122 ) between the vertical source portion 114 and the horizontal drain portion 122 . The third gate portion 136 is located between a vertical source portion 114 and a vertical drain portion 124 in the X direction, and between the horizontal source portion 112 and the horizontal drain portion 122 in the Y direction. The third gate part 136 is connected to each other through the first gate part 132 and the second gate part 134. It can also be said that the first gate part 132 and the second gate part 134 are connected to each other through the third gate part. Part 136 connection. In some embodiments, the first gate portion 132 and the second gate portion 134 are arc-shaped in a top view (eg, FIG. 1 ).

In some embodiments, the semiconductor device 100 further includes a blocking structure 140 disposed above the epitaxial structure (eg, the epitaxial structure 101 described below). The barrier structure 140 is disposed between the vertical drain portion 124 and the gate structure 130 in the Y direction (ie, the tip drain portion 126 of the vertical drain portion 124 points in the direction of the horizontal source portion 112 ). More specifically, the blocking structure 140 is disposed between the tip drain portion 126 and the first gate portion 132 in the Y direction, as shown in FIG. 1 . In some embodiments, barrier structure 140 is completely surrounded by first gate portion 132 . In some other embodiments, a portion of the blocking structure 140 extends beyond the first gate portion 132 in the Y direction and between the two third gate portions 136 on either side of the vertical drain portion 124 in the X direction. .

The arrangement of the blocking structure 140 can make the two-dimensional electron gas below the blocking structure 140 disappear. Thereby, in the direction in which the tip drain portion 126 points toward the horizontal source portion 112, the transistor channel will be closed and current will not be able to flow in this direction. Due to the lack of carriers brought by the current, the hot carriers generated and accumulated at the tip drain portion 126 are eliminated or reduced. In this way, the blocking structure 140 can prevent hot carriers from damaging the performance of the semiconductor device 100 or causing damage to the semiconductor device 100 . The details of barrier structure 140 will be described in greater detail below.

Figure 2A is a cross-sectional view of the semiconductor device 100A along the line segment AA' of Figure 1 according to some embodiments of the present disclosure, and Figure 2B is a cross-sectional view of the semiconductor device 100A along the line segment AA' according to some embodiments of the present disclosure. Referring to the cross-sectional view of line segment BB′ in FIG. 1 , the semiconductor device 100A is an embodiment of the semiconductor device 100 . In the illustrated embodiment, the cross-sectional view of FIG. 2A belongs to the channel region of the semiconductor device 100 and the cross-sectional view of FIG. 2B belongs to the non-channel region of the semiconductor device 100 . It should be noted that in the cross-sectional view of the semiconductor device 100 along line segment A-A' in FIG. 1 , the configuration of the gate structure 130 will change accordingly with the embodiments in FIGS. 2B to 5 .

Referring to Figures 2A and 2B, the semiconductor device 100A includes an epitaxial structure 101, where the epitaxial structure 101 includes a substrate 102, a buffer layer 103 above the substrate 102, a channel layer 104 above the buffer layer 103, and a channel layer. Barrier layer 105 above 104. In some embodiments, the buffer layer 103 and the channel layer 104 may be merged together and collectively referred to as a buffer layer or a channel layer.

In some embodiments, the material of the channel layer 104 is GaN, and the material of the barrier layer 105 is AlGaN. The GaN/AlGaN heterojunction in which the channel layer 104 and the barrier layer 105 are stacked together forms a two-dimensional electron gas (2DEG) between the channel layer 104 and the barrier layer 105 to serve as the channel 106 of the semiconductor device 100 (shown as a dotted line draw).

In FIGS. 2A and 2B , the gate structure 130A including the first gate portion 132A and the third gate portion 136A is an embodiment of the gate structure 130 , and the barrier structure 140A is an embodiment of the barrier structure 140 . Referring again to FIGS. 2A and 2B , the source structure 110 , the drain structure 120 and the gate structure 130A are disposed above the epitaxial structure 101 , such as above the barrier layer 105 , and the gate structure 130A is disposed on the source structure 110 and the drain structure 120 . As shown in FIG. 2A , the third gate portion 136A of the gate structure 130A is disposed between the vertical source portion 114 of the source structure 110 and the vertical drain portion 124 of the drain structure 120 along the X direction. As shown in FIG. 2B , the first gate portion 132A of the gate structure 130A is disposed between the horizontal source portion 112 of the source structure 110 and the vertical drain portion 124 of the drain structure 120 along the Y direction.

Still referring to FIGS. 2A and 2B , the gate structure 130A includes an epitaxial layer 150 and an electrode layer 152 above the epitaxial layer 150 . In some embodiments, the material of the epitaxial layer 150 is p-type gallium nitride (p-GaN) doped with p-type dopants. In some embodiments, the gate structure 130 further includes other thin layers, such as a gate dielectric layer, a passivation layer, a work function layer, and/or other suitable thin layers.

The epitaxial layer 150 (for example, p-type gallium nitride) can modulate the energy band, causing the heterojunction structure of the barrier layer 105 (for example, AlGaN) and the channel layer 104 (for example, GaN) below to undergo energy band bending. (band bending), and causes the quantum well in which the two-dimensional electron gas exists to disappear. With the disappearance of the quantum well and the two-dimensional electron gas, there is no longer a channel below the gate structure 130A. As shown in Figures 2A and 2B, channel 106 is cut off below gate structure 130A. As a result, a positive voltage must be applied to the gate structure 130A to restore the channel 106 below the gate structure 130A, which makes the semiconductor device 100A a normally-off type that requires a positive voltage to be applied to the gate to turn on. device, that is, an enhancement mode (E-mode) device with a critical voltage (Vth) greater than zero.

On the other hand, if the epitaxial layer 150 is not provided or the energy band is modulated in other ways, the channel 106 under the gate structure 130A will continue to exist, and a negative voltage must be applied to the gate structure 130A to cut off the gate. Channel 106 beneath structure 130A and closes semiconductor device 100A. In this way, the semiconductor device 100A will become a normally-on device that can be turned on without applying voltage to the gate, and can be turned off by applying a negative voltage to the gate. That is, the critical voltage (Vth) is less than Zero depletion mode (D-mode) device.

Referring to FIG. 2B , the barrier structure 140A is disposed above the epitaxial structure 101 , for example, above the barrier layer 105 , and is disposed between the tip drain portion 126 of the vertical drain portion 124 and the first gate portion 132A in the Y direction. . In some embodiments, the length of the barrier structure 140 occupies most of the distance between the gate structure 130A and the vertical drain portion 124 in the Y direction. In the embodiment shown in FIG. 2B , the barrier structure 140A includes a barrier layer 160 and a metal layer 162 above the barrier layer 160 . In some embodiments, barrier structure 140A is electrically floating.

In some embodiments, barrier layer 160 includes the same material as epitaxial layer 150 , and/or metal layer 162 includes the same material as electrode layer 152 . In some embodiments, the barrier layer 160 and the epitaxial layer 150 are formed in the same process, and the metal layer 162 and the electrode layer 152 are formed in the same process. In this way, the barrier structure 140A and the gate structure 130A can be formed simultaneously. Therefore, the formation of the barrier structure 140A can be fully compatible with the current manufacturing process and does not consume additional process time.

As mentioned above, the epitaxial layer 150 (eg, p-type gallium nitride) can modulate the energy band so that the two-dimensional electron gas below it disappears and thereby cuts off the channel of the transistor. Therefore, by disposing the barrier layer 160 with the same material as the epitaxial layer 150 in the barrier structure 140A, the channel 106 under the barrier structure 140A can be cut off, as shown in FIG. 2B. As a result, current will not be able to flow under the blocking structure 140A, that is, current will not be able to flow between the horizontal source portion 112 and the vertical drain portion 124, regardless of whether the semiconductor device 100A is turned on or not. In other words, current cannot flow in the direction in which the tip drain portion 126 points toward the horizontal source portion 112 . Due to the lack of carriers brought by the current, the hot carriers generated and accumulated at the tip drain portion 126 are eliminated or reduced. In this way, the blocking structure 140A can prevent hot carriers from damaging the performance of the semiconductor device 100A or causing damage to the semiconductor device 100A.

In some other embodiments, gate structure 130A does not include epitaxial layer 150 . As mentioned above, the lack of epitaxial layer 150 will allow the channel 106 below the gate structure 130A to persist, and a negative voltage must be applied to the gate structure 130A to turn off the semiconductor device 100A. Therefore, in these embodiments, the semiconductor device 100A is a depletion mode (D-mode) device with a threshold voltage (Vth) less than zero.

Figure 3 is a cross-sectional view of a semiconductor device 100B along line B-B' of Figure 1 according to some embodiments of the present disclosure, wherein the semiconductor device 100B is an embodiment of the semiconductor device 100. The semiconductor device 100B shown in FIG. 3 is similar to the semiconductor device 100A shown in FIG. 2B , except that the semiconductor device 100B includes a barrier structure 140B instead of a barrier structure 140A, where the barrier structure 140B is an embodiment of the barrier structure 140 .

Referring to FIG. 3 , the semiconductor device 100B includes a barrier groove 170 disposed in the barrier layer 105 . The barrier groove 170 extends from the top surface toward the bottom surface of the barrier layer 105 but does not extend through the barrier layer 105 . In other words, the depth of the barrier groove 170 is less than the thickness of the barrier layer 105 , that is, the bottom surface of the barrier groove 170 is higher than the bottom surface of the barrier layer 105 but lower than the top surface of the barrier layer 105 .

Referring to FIG. 3 , the barrier structure 140B includes the metal layer 162 disposed in the barrier groove 170 , but does not include the barrier layer 160 . In some embodiments, barrier structure 140B is T-shaped. In these embodiments, the barrier structure 140B includes a lower portion disposed within the barrier groove 170 and below the top surface of the barrier layer 105 , and a portion disposed outside the barrier groove 170 and above the top surface of the barrier layer 105 the upper part of the surface. In these embodiments, the size of the upper portion of the blocking structure 140B in the Y direction is larger than the size of the lower portion of the blocking structure 140B in the Y direction.

Since the barrier groove 170 is formed by recessing the barrier layer 105 , the presence of the barrier groove 170 will reduce the thickness of the barrier layer 105 . Once the thickness of the barrier layer 105 is reduced, the energy band structure between the barrier layer 105 and the channel layer 104 will change and the quantum well that can accommodate the two-dimensional electron gas cannot be maintained. Therefore, below the blocking groove 170 with the blocking structure 140B disposed therein, the channel 106 will be cut off, as shown in FIG. 3 . As a result, current will not be able to flow under the blocking structure 140B, that is, current will not be able to flow between the horizontal source portion 112 and the vertical drain portion 124, regardless of whether the semiconductor device 100B is turned on or not. In other words, current cannot flow in the direction in which the tip drain portion 126 points toward the horizontal source portion 112 . Due to the lack of carriers brought by the current, the hot carriers generated and accumulated at the tip drain portion 126 are eliminated or reduced. In this way, the blocking structure 140B can prevent hot carriers from damaging the performance of the semiconductor device 100B or causing damage to the semiconductor device 100B.

In further embodiments, in addition to metal layer 162, barrier structure 140B may include a barrier layer such as p-type gallium nitride (not shown). As mentioned above, the barrier layer composed of p-type gallium nitride is the same as the barrier groove 170 formed by digging into the barrier layer 105, and both can cut off the channel 106 below it. Therefore, in these embodiments, the barrier layer and the barrier groove 170 can be used together to enhance the effect of cutting off the channel 106 to avoid the reappearance of the channel 106 caused by external factors such as process errors, defects, and voltage disturbance during operation. As a result, current can flow in the direction from the tip drain portion 126 to the horizontal source portion 112 . Alternatively, using both a barrier layer and barrier recess 170 may reduce the thickness of the barrier layer required and/or the depth of barrier recess 170 required.

FIG. 4 is a cross-sectional view of a semiconductor device 100C along line segment B-B′ of FIG. 1 according to some embodiments of the present disclosure, wherein the semiconductor device 100C is an embodiment of the semiconductor device 100 . The semiconductor device 100C shown in FIG. 4 is similar to the semiconductor device 100A shown in FIG. 2B, except that the semiconductor device 100C includes a gate structure 130C (including a first gate portion 132C) instead of a gate structure 130A, where Gate structure 130C is an embodiment of gate structure 130 .

Referring to FIG. 4 , the semiconductor device 100C further includes a gate recess 180 disposed in the barrier layer 105 . Gate recess 180 extends from the top surface toward the bottom surface of barrier layer 105 but does not extend through barrier layer 105 . In other words, the depth of the gate groove 180 is less than the thickness of the barrier layer 105 , that is, the bottom surface of the gate groove 180 is higher than the bottom surface of the barrier layer 105 but lower than the top surface of the barrier layer 105 .

In some embodiments, gate structure 130C is disposed in gate groove 180 and does not include epitaxial layer 150, as shown in FIG. 4 . The gate groove 180 is similar to the barrier groove 170 , so the gate groove 180 will change the energy band structure between the barrier layer 105 and the channel layer 104 and fail to maintain a quantum well capable of accommodating two-dimensional electron gas. Therefore, the channel 106 will be cut off below the gate recess 180 in which the gate structure 130C is disposed, as shown in FIG. 4 . As a result, a positive voltage must be applied to the gate structure 130C to restore the channel 106 below the gate structure 130C, making the semiconductor device 100C an enhancement mode (E-mode) device with a critical voltage (Vth) greater than zero.

Still referring to FIG. 4 , the semiconductor device 100C of FIG. 4 includes the same barrier structure 140A as the semiconductor device 100A of FIG. 2B . Therefore, as described above with reference to FIG. 2B , the semiconductor device 100C including the barrier structure 140A can also eliminate or reduce the hot carriers generated and accumulated at the tip drain portion 126 and prevent the hot carriers from damaging the performance of the semiconductor device 100C or causing damage to the semiconductor device 100C.

In further embodiments, in addition to the electrode layer 152 , the gate structure 130C may also include an epitaxial layer (not shown) such as p-type gallium nitride. As mentioned above, the epitaxial layer composed of p-type gallium nitride is the same as the gate groove 180 formed by digging into the barrier layer 105, and both can cut off the channel 106 below it. Therefore, in these embodiments, the epitaxial layer and the gate groove 180 can be used together to enhance the effect of cutting off the channel 106 to avoid external factors such as process errors, defects, and voltage disturbance during operation. The reappearance causes the semiconductor device 100C to change from an enhancement mode (E-mode) device to a depletion mode (D-mode) device. Alternatively, using an epitaxial layer together with the gate recess 180 may reduce the required thickness of the epitaxial layer and/or the required depth of the gate recess 180 .

In some embodiments, the semiconductor device 100C does not include the gate recess 180 , but the gate structure 130C is directly disposed on the barrier layer 105 . In these embodiments, the semiconductor device 100C is a depletion mode (D-mode) device with a threshold voltage (Vth) less than zero due to the lack of a mechanism that can cut off the channel underneath the gate structure.

FIG. 5 is a cross-sectional view of a semiconductor device 100D along line segment B-B′ in FIG. 1 according to some embodiments of the present disclosure, wherein the semiconductor device 100D is an embodiment of the semiconductor device 100 . The semiconductor device 100D of FIG. 5 is similar to the semiconductor device 100A of FIG. 2B except that the configuration of the gate structure and the barrier structure is different.

Referring to FIG. 5 , the semiconductor device 100D shown in FIG. 5 has the same barrier structure 140B and barrier groove 170 as in FIG. 3 . Therefore, as described above with reference to FIG. 3 , the semiconductor device 100D shown in FIG. 5 can eliminate or reduce the hot carriers generated and accumulated at the tip drain portion 126 and prevent the hot carriers from damaging the performance of the semiconductor device 100D or This causes damage to the semiconductor device 100D.

Referring also to FIG. 5 , the semiconductor device 100D shown in FIG. 5 has the same gate structure 130C and gate recess 180 as in FIG. 4 . Therefore, as mentioned above with reference to FIG. 4 , the semiconductor device 100D shown in FIG. 5 can be an enhancement mode (E-mode) device with a threshold voltage (Vth) greater than zero.

In some embodiments, metal layer 162 includes the same material as electrode layer 152 . In some embodiments, the barrier groove 170 and the gate groove 180 are formed in the same process, and the metal layer 162 and the electrode layer 152 are formed in the same process. In this way, the barrier structure 140B and the gate structure 130C can be formed simultaneously. Therefore, the formation of the barrier structure 140B can be fully compatible with the current manufacturing process and does not consume additional process time.

In some embodiments, regions doped with fluorine ions can be used to supplement or replace the epitaxial layer 150, the barrier layer 160, the gate groove 180 and/or the barrier groove 170 shown in Figures 2B to 5. . For example, a fluorine doped region may be formed under the gate structure 130 and/or under the barrier structure 140 . The fluorine doped region has the same function as the p-type gallium nitride and the grooves in the barrier layer. The fluorine-doped region can modulate the energy band below it to truncate the channel, resulting in the need to apply a positive voltage to restore the truncated channel. By forming a fluorine doped region under the gate structure 130, the semiconductor device 100 can become an enhancement mode (E-mode) device with a critical voltage (Vth) greater than zero. Further, by forming a fluorine-doped region below the barrier structure 140 , the channel below the barrier structure 140 can be cut off, so that current cannot flow in the direction in which the tip drain portion 126 points toward the horizontal source portion 112 . In this way, hot carriers can also be prevented from damaging the performance of the semiconductor device 100 or causing damage to the semiconductor device 100 .

FIG. 6 is a top view of a portion or the entirety of an exemplary semiconductor device 200 according to some embodiments of the present disclosure. The semiconductor device 200 may be a single transistor device or an array of multiple transistor devices, such as a GaN HEMT. The semiconductor device 200 shown in FIG. 6 has some of the same features as the semiconductor device 100 shown in FIG. 1 , and these features have the same configuration. For example, the semiconductor device 200 has the same source structure 110 , drain structure 120 and gate structure 130 as the semiconductor device 100 .

In some embodiments, unlike semiconductor device 100 , semiconductor device 200 includes barrier structure 210 instead of barrier structure 140 , and barrier structure 210 has a different configuration than barrier structure 140 . The barrier structure 210 is disposed between the vertical drain portion 124 and the gate structure 130 in the Y direction (ie, the tip drain portion 126 of the vertical drain portion 124 points in the direction of the horizontal source portion 112 ). More specifically, the blocking structure 210 is disposed between the tip drain portion 126 and the first gate portion 132 in the Y direction, as shown in FIG. 6 . In some embodiments, the first gate portion 132 is arc-shaped in a top view (eg, FIG. 6 ), and the blocking structure 210 is also arc-shaped in a top view (eg, FIG. 6 ).

Similar to the blocking structure 140, the arrangement of the blocking structure 210 can cause the two-dimensional electron gas below the blocking structure 210 to disappear. Thereby, in the direction in which the tip drain portion 126 points toward the horizontal source portion 112, the transistor channel will be closed and current will not be able to flow in this direction. Due to the lack of carriers brought by the current, the hot carriers generated and accumulated at the tip drain portion 126 are eliminated or reduced. In this way, the blocking structure 210 can prevent hot carriers from damaging the performance of the semiconductor device 200 or causing damage to the semiconductor device 200 . The details of barrier structure 210 will be described in greater detail below.

In some embodiments, the semiconductor device 200 further includes a connection structure 220 . Connection structure 220 connects barrier structure 210 to source structure 110 , for example to horizontal source portion 112 . The connection structure 220 does not contact the gate structure 130, which will be more clearly shown in subsequent figures. By connecting the barrier structure 210 to the source structure 110 with the connection structure 220 , the barrier structure 210 can be maintained at the same potential as the source structure 110 . Generally speaking, the source structure 110 is connected to ground during operation. And as mentioned above, the blocking structure 210 will close the channel below it, so a positive voltage needs to be applied to the blocking structure 210 to make the channel reappear. In this way, by connecting the blocking structure 210 to the source structure 110, the blocking structure 210 can be maintained in a grounded state, that is, maintained at an off potential that prevents the channel from reappearing. Thereby, voltage disturbance during operation or unexpected channel occurrence caused by charges trapped by the structure can be avoided, because the connection structure 220 connected to the source structure 110 can maintain the barrier structure 210 at the off potential.

In some embodiments, the barrier structure 210 is close to the gate structure 130 and away from the drain structure 120 . For example, in the Y direction, the distance between the blocking structure 210 and the first gate portion 132 is smaller than the distance between the blocking structure 210 and the tip drain portion 126 . In embodiments where the semiconductor device 200 is a GaN HEMT, a relatively high voltage (eg, at least several hundred volts) is applied to the drain structure 120 during operation. Thus, a relatively high electric field exists between the barrier structure 210 connected to the source structure 110 (eg, ground) and the vertical drain portion 124 . Therefore, the barrier structure 210 must be far away from the vertical drain portion 124 so that the semiconductor device 200 can withstand high-voltage operation and avoid punch through between the vertical drain portion 124 and the barrier structure 210 .

In some other embodiments, the barrier structure 210 is not connected to the source structure 110 but is electrically floating. In these embodiments, the blocking structure 210 only cuts off the channel under the blocking structure 210 by the same mechanism as the blocking structure 140 to eliminate or reduce the heat carriers generated and accumulated at the tip drain portion 126 and prevent heat carriers from being generated. may damage the performance of the semiconductor device 200 or cause damage to the semiconductor device 200 .

The cross-sectional view of the semiconductor device 200 shown in FIG. 6 along line segment A-A' in FIG. 6 is similar to that in FIG. 2A, and therefore will not be repeated here. It should be noted that in the cross-sectional view of the semiconductor device 200 along line segment A-A' in FIG. 6 , the configuration of the gate structure 130 will change accordingly with the embodiments in FIGS. 7 to 10 .

FIG. 7 is a cross-sectional view of a semiconductor device 200A along line segment B-B′ of FIG. 6 according to some embodiments of the present disclosure, wherein the semiconductor device 200A is an embodiment of the semiconductor device 200 . The semiconductor device 200A shown in FIG. 7 is similar to the semiconductor device 100A shown in FIG. 2B except that the semiconductor device 200A includes a barrier structure 210A instead of the barrier structure 140A, where the barrier structure 210A is an embodiment of the barrier structure 210 .

Referring to FIG. 7 , the barrier structure 210A is disposed above the epitaxial structure 101 , for example, above the barrier layer 105 , and is disposed between the tip drain portion 126 of the vertical drain portion 124 and the first gate portion 132A in the Y direction. . In some embodiments, the distance D1 between the blocking structure 210A and the first gate portion 132A in the Y direction is smaller than the distance D2 between the blocking structure 210A and the vertical drain portion 124 . In some embodiments, barrier structure 210A includes barrier layer 230 and metal layer 232 over barrier layer 230 .

In some embodiments, barrier layer 230 includes the same material as epitaxial layer 150, such as p-type gallium nitride. In some embodiments, metal layer 232 includes the same material as electrode layer 152 . In some embodiments, the barrier layer 230 and the epitaxial layer 150 are formed in the same process, and the metal layer 232 and the electrode layer 152 are formed in the same process. In this way, the barrier structure 210A and the gate structure 130A can be formed simultaneously. Therefore, the formation of the barrier structure 210A can be fully compatible with the current manufacturing process and does not consume additional process time.

As mentioned above, the epitaxial layer 150 (eg, p-type gallium nitride) can modulate the energy band so that the two-dimensional electron gas below it disappears and thereby cuts off the channel of the transistor. Therefore, by disposing the barrier layer 230 with the same material as the epitaxial layer 150 in the barrier structure 210A, the channel 106 under the barrier structure 210A can be cut off, as shown in FIG. 7 . As a result, current will not be able to flow under the blocking structure 210A, that is, current will not be able to flow between the horizontal source portion 112 and the vertical drain portion 124, regardless of whether the semiconductor device 200A is turned on or not. In other words, current cannot flow in the direction in which the tip drain portion 126 points toward the horizontal source portion 112 . Due to the lack of carriers brought by the current, the hot carriers generated and accumulated at the tip drain portion 126 are eliminated or reduced. In this way, the blocking structure 210A can prevent hot carriers from damaging the performance of the semiconductor device 200A or causing damage to the semiconductor device 200A.

In some embodiments, semiconductor device 200A includes connection structure 220 that connects barrier structure 210A to source structure 110 , such as to horizontal source portion 112 . The connection structure 220 may include a first contact disposed on the blocking structure 210A, a second contact disposed on the horizontal source portion 112, and a wire connecting the first contact and the second contact. As described above, by connecting the barrier structure 210A to the source structure 110 through the connection structure 220, the barrier structure 210A can be maintained at the off potential. In this way, unintentional conduction of the channel is avoided to ensure that current does not flow in the direction from the tip drain portion 126 to the horizontal source portion 112 .

In some other embodiments, the connection structure 220 included in the semiconductor device 200A does not connect the blocking structure 210A to the source structure 110 , but connects the blocking structure 210A to other voltage sources (not shown). In these embodiments, a voltage source may apply a ground voltage to barrier structure 210A to achieve the same function as being connected to source structure 110 . That is, the blocking structure 210A can be maintained at a closed potential to avoid accidental conduction of the channel to ensure that current does not flow in the direction in which the tip drain portion 126 points toward the horizontal source portion 112 . Alternatively, the voltage source may apply a negative voltage to barrier structure 210A to more completely block the channel beneath barrier structure 210A. In this way, the channel can be made more difficult to recover to ensure that current does not flow in the direction from the tip drain portion 126 to the horizontal source portion 112 . Alternatively, the voltage source can apply a positive voltage to barrier structure 210A to restore the channel when it is desired to restore the channel, which again allows current to flow in the direction of tip drain portion 126 toward horizontal source portion 112 . By connecting the barrier structure 210A to other voltage sources, the channel underneath the barrier structure 210A can be freely controlled to be closed or not. In this way, the semiconductor device 200A can have more flexibility in operation.

FIG. 8 is a cross-sectional view of a semiconductor device 200B along line segment B-B′ of FIG. 6 according to some embodiments of the present disclosure, wherein the semiconductor device 200B is an embodiment of the semiconductor device 200 . The semiconductor device 200B shown in FIG. 8 is similar to the semiconductor device 200A shown in FIG. 7 , except that the semiconductor device 200B includes a barrier structure 210B instead of a barrier structure 210A, where the barrier structure 210B is an embodiment of the barrier structure 210 .

Referring to FIG. 8 , the semiconductor device 200B includes a barrier groove 240 disposed in the barrier layer 105 . The barrier groove 240 extends from the top surface toward the bottom surface of the barrier layer 105 but does not extend through the barrier layer 105 . In other words, the depth of the barrier groove 240 is less than the thickness of the barrier layer 105 , that is, the bottom surface of the barrier groove 240 is higher than the bottom surface of the barrier layer 105 but lower than the top surface of the barrier layer 105 .

In some embodiments, barrier structure 210B includes metal layer 232 disposed in barrier groove 240, but does not include barrier layer 230. In some embodiments, barrier structure 210B is T-shaped. In these embodiments, the barrier structure 210B includes a lower portion disposed within the barrier groove 240 and below the top surface of the barrier layer 105 , and a portion disposed outside the barrier groove 240 and above the top surface of the barrier layer 105 the upper part of the surface. In these embodiments, the size of the upper portion of the blocking structure 210B in the Y direction is larger than the size of the lower portion of the blocking structure 210B in the Y direction.

Like the barrier groove 170 , the barrier groove 240 is formed by digging into the barrier layer 105 . As previously described with reference to blocking groove 170, channel 106 will be truncated beneath blocking groove 240 with blocking structure 210B disposed therein, as shown in FIG. 8 . In this way, the blocking groove 240 with the blocking structure 210B disposed therein can achieve the same effect as the blocking groove 170 , that is, to eliminate or reduce the heat carriers generated and accumulated at the tip drain portion 126 and prevent heat carriers from being generated. may damage the performance of the semiconductor device 200B or cause damage to the semiconductor device 200B.

In a further embodiment, in addition to metal layer 162, barrier structure 210B includes a barrier layer such as p-type gallium nitride (not shown). In these embodiments, the barrier structure 210B including the barrier layer can achieve the same effect as the barrier structure 140B including the barrier layer described previously with reference to FIG. 3 . That is, the barrier structure 210B including the barrier layer can enhance the effect of blocking the channel 106 and/or reduce the required thickness of the barrier layer and/or the required depth of the barrier groove 240 .

Still referring to FIG. 8 , the semiconductor device 200B of FIG. 8 includes a similar configuration of the connection structure 220 as the semiconductor device 200A of FIG. 7 . In the embodiment shown in FIG. 8 , the connection structure 220 connects the barrier structure 210B to the source structure 110 or connects the barrier structure 210B to other voltage sources, and has the same function as previously described with reference to FIG. 7 Effect.

Figure 9 is a cross-sectional view of a semiconductor device 200C along line segment B-B' of Figure 6 according to some embodiments of the present disclosure, wherein the semiconductor device 200C is an embodiment of the semiconductor device 200. The semiconductor device 200C shown in FIG. 9 is similar to the semiconductor device 200 shown in FIG. 7 , except that the semiconductor device 200C includes a gate structure 130C instead of a gate structure 130A.

Referring to FIG. 9 , the semiconductor device 200C has the same gate structure 130C and gate recess 180 as the semiconductor device 100C shown in FIG. 4 . Therefore, as mentioned above with reference to FIG. 4 , the semiconductor device 200C shown in FIG. 9 can be an enhancement mode (E-mode) device with a threshold voltage (Vth) greater than zero.

Still referring to FIG. 9 , semiconductor device 200C includes the same barrier structure 210A as semiconductor device 200A shown in FIG. 7 . Therefore, as described above with reference to FIG. 7 , the semiconductor device 200C including the barrier structure 210A can also eliminate or reduce the hot carriers generated and accumulated at the tip drain portion 126 and prevent the hot carriers from damaging the performance of the semiconductor device 200C or causing damage to the semiconductor device 200C.

Still referring to FIG. 9 , the semiconductor device 200C of FIG. 9 includes the same arrangement of barrier structures 210A and connection structures 220 as the semiconductor device 200A shown in FIG. 7 . Therefore, in the semiconductor device 200C shown in FIG. 9 , the connection structure 220 has the same effect as previously described with reference to FIG. 7 .

FIG. 10 is a cross-sectional view of a semiconductor device 200D along line segment B-B′ of FIG. 6 according to some embodiments of the present disclosure, wherein the semiconductor device 200D is an embodiment of the semiconductor device 200 . The semiconductor device 200D of FIG. 10 is similar to the semiconductor device 200A of FIG. 7 except that the configuration of the gate structure and the barrier structure is different.

Referring to FIG. 10 , the semiconductor device 200D shown in FIG. 10 has the same barrier structure 210B and barrier groove 240 as in FIG. 8 . Therefore, as mentioned above with reference to FIG. 8 , the semiconductor device 200D shown in FIG. 10 can Eliminate or reduce hot carriers generated and accumulated at the tip drain portion 126 and prevent the hot carriers from damaging the performance of the semiconductor device 200D or causing damage to the semiconductor device 200D.

Referring also to FIG. 10 , the semiconductor device 200D shown in FIG. 10 has the same gate structure 130C and gate recess 180 as in FIG. 4 . Therefore, as mentioned above with reference to FIG. 4 , the semiconductor device 200D shown in FIG. 10 can be an enhancement mode (E-mode) device with a threshold voltage (Vth) greater than zero.

In some embodiments, metal layer 232 includes the same material as electrode layer 152 . In some embodiments, the barrier groove 240 and the gate groove 180 are formed in the same process, and the metal layer 232 and the electrode layer 152 are formed in the same process. In this way, the barrier structure 210B and the gate structure 130C can be formed simultaneously. Therefore, the formation of the barrier structure 210B can be fully compatible with the current manufacturing process and does not consume additional process time.

Still referring to FIG. 10 , the semiconductor device 200D shown in FIG. 10 includes the same arrangement of barrier structures 210B and connection structures 220 as the semiconductor device 200B shown in FIG. 8 . Therefore, in the semiconductor device 200D shown in FIG. 10 , the connection structure 220 has the same effect as previously described with reference to FIG. 8 .

In some embodiments, regions doped with fluorine ions can be used to supplement or replace the epitaxial layer 150, the barrier layer 230, the gate groove 180 and/or the barrier groove 240 shown in Figures 7 to 10. . As described above with reference to FIGS. 2B to 5 , by forming a fluorine doped region, the semiconductor device 200 can become an enhancement mode (E-mode) device with a critical voltage (Vth) greater than zero, and can prevent hot carriers from Impair the performance of the semiconductor device 200 or cause damage to the semiconductor device 200 .

FIG. 11 is a flowchart of a method 300 for forming the semiconductor device 100 and/or the semiconductor device 200 according to some embodiments of the present disclosure. Figure 11 will be described below with reference to Figures 1 to 10 simultaneously.

In operation 302, the method 300 provides or receives an epitaxial structure, such as the epitaxial structure 101 described above. The epitaxial structure 101 includes a substrate 102, a buffer layer 103 above the substrate 102, a channel layer 104 above the buffer layer 103, and a barrier layer 105 above the channel layer 104. In some embodiments, the buffer layer 103 and the channel layer 104 may be merged and collectively referred to as a buffer layer or a channel layer.

In operation 304, the method 300 forms an epitaxial material layer (eg, a p-type gallium nitride layer) over an epitaxial structure (eg, the epitaxial structure 101). The epitaxial material layer can be formed by epitaxial growth processes, such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), atomic layer Epitaxy (ALE), etc. or combinations thereof. The epitaxial material layer can be doped with carbon, iron, magnesium, zinc or other suitable dopants through an ion implantation process, an in-situ doping epitaxial growth process and/or other suitable technologies. Miscellaneous.

In operation 306, the method 300 patterns the epitaxial material layer to form an epitaxial layer of the gate structure or a barrier layer of the barrier structure, such as the epitaxial layer 150, the barrier layer 160 and/or the barrier layer described above. 230. In embodiments that do not include the epitaxial layer of the gate structure and the barrier layer of the barrier structure (eg, the embodiments of FIGS. 5 and 10 ), operations 304 and 306 may be omitted.

Patterning of the epitaxial material layer can be performed using appropriate lithography processes and etching processes. In some embodiments, the lithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing, and drying (e.g., hard baking) . In other embodiments, the lithography process may be performed or replaced by other suitable methods, such as maskless lithography, e-beam writing, and ion beam writing. In some embodiments, the etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes.

In operation 308 , the method 300 forms a source structure and a drain structure, such as a source structure including a horizontal source portion 112 and a vertical source portion 114 , over a barrier layer (eg, barrier layer 105 ) of an epitaxial structure. 110, and a drain structure 120 including a horizontal drain portion 122 and a vertical drain portion 124.

In some embodiments, operation 308 uses a photolithography process to form a patterned photoresist layer including openings on the barrier layer 105, and deposits a conductive material on the patterned photoresist layer through a deposition process, and then through photoresist stripping ( The lift off) process removes the patterned photoresist layer and the conductive material on the patterned photoresist layer, leaving the conductive material in the opening as the source structure and the drain structure. In some other embodiments, operation 308 may first deposit a conductive material on the barrier layer 105 through a deposition process, and then pattern the deposited conductive material through a lithography and etching process to form a source structure and a drain structure.

Suitable deposition processes may include physical vapor deposition (PVD), chemical vapor deposition (CVD), coating processes, other suitable processes, or combinations thereof. The PVD process may include sputtering, evaporation and/or pulsed laser deposition. CVD processes can include low-pressure chemical vapor deposition (LPCVD), low-temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition phase deposition (HDPCVD), MOCVD, remote plasma chemical vapor deposition (RPCVD), atomic layer deposition (ALD) process, electroplating, other suitable processes and/or combinations thereof. Suitable conductive materials may include aluminum (Al), copper (Cu), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co) , ruthenium (Ru), palladium (Pd), platinum (Pt), manganese (Mn), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), silicide Tungsten (WSi), titanium silicon oxide (TiSi ₂ ), other suitable conductive materials or combinations thereof.

In operation 310 , the method 300 digs into the barrier layer (eg, barrier layer 105 ) of the epitaxial structure to form gate grooves and/or barrier grooves, such as gate groove 180 , barrier groove 170 and/or Or blocking groove 240. The barrier layer can be drilled in using a suitable etching process. In embodiments that do not include gate grooves and barrier grooves (eg, FIG. 2B and FIG. 7 ), operation 310 may be omitted. In embodiments that include both a gate groove and/or a barrier groove and an epitaxial layer of the gate structure and/or a barrier layer of the barrier structure, operation 310 may be performed before operations 304 and 306.

In operation 312 , the method 300 deposits a gate metal material to form an electrode layer of the gate structure and/or a metal layer of the barrier structure, such as the electrode layer 152 of the gate structure 130 , the metal layer 162 of the barrier structure 140 and/or the barrier structure. Metal layer 232 of structure 210 . In some embodiments, operation 312 uses a photolithography process to form a patterned photoresist layer including openings over the semiconductor device 100 or 200 , and these openings expose the epitaxial layer 150 , the gate groove 180 , the barrier layer 160 , Barrier groove 170, barrier layer 230 and/or barrier groove 240. Operation 312 then deposits a gate metal material on the patterned photoresist layer through a deposition process, and then removes the patterned photoresist layer and the gate metal material on the patterned photoresist layer through a photoresist stripping process to leave an opening. The gate metal material serves as the electrode layer of the gate structure and/or the metal layer of the barrier structure. In some other embodiments, operation 312 may first deposit a gate metal material on the semiconductor device 100 or the semiconductor device 200 through a deposition process, and then pattern the deposited gate metal material through a lithography and etching process to form a gate structure. electrode layer and/or metal layer of the barrier structure.

Gate metal materials may include Al, Cu, Au, Ag, W, Ti, Ta, Ni, Co, Ru, Pd, Pt, Mn, WN, TiN, TaN, MoN, WSi, TiSi ₂ and other suitable conductive materials or combination thereof.

After operation 312, the method 300 forms the gate structure 130, the barrier structure 140 and/or the barrier structure 210 as described above with reference to FIGS. 1-10. In some embodiments, the electrode layer 152 and the epitaxial layer 150 together form the gate structure 130A. In some embodiments, electrode layer 152 is formed in gate recess 180 and constitutes gate structure 130C. In some embodiments, metal layer 162 and barrier layer 160 together form barrier structure 140A. In some embodiments, metal layer 162 is formed in barrier groove 170 and constitutes barrier structure 140B. In some embodiments, metal layer 232 and barrier layer 230 together form barrier structure 210A. In some embodiments, metal layer 232 is formed in barrier groove 240 and constitutes barrier structure 210B.

In operation 314, method 300 performs further processing. In some embodiments, the method 300 further includes forming a first contact on the barrier structure 210, forming a second contact on the horizontal source portion 112, and forming a conductor connecting the first contact and the second contact to A connection structure 220 is formed connecting the barrier structure 210 to the source structure 110 . In some embodiments, method 300 further includes forming a field plate structure in the semiconductor device. In some embodiments, the method 300 further includes forming various contacts, vias, and wires to form an interconnection structure within a single device and/or between multiple devices.

It should be noted that additional operations may be provided before, during, or after method 300, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of method 300. For example, a gate dielectric layer may be deposited to form a metal insulator semiconductor (MIS) structure, various isolation structures may be formed to separate semiconductor devices, and/or an interlayer dielectric (ILD) layer and an intermetal dielectric (IMD) layer may be formed To assist in the formation of various components and support semiconductor devices.

In some embodiments, the method 300 further includes an implantation process of implanting fluoride ions. Fluorine ions may be implanted in the area below the gate structure 130, the barrier structure 140, and/or the barrier structure 210 to form a fluorine doped area to intercept the semiconductor channel, as described above. In these embodiments, operations 304, 306, and 310 may be omitted.

The present disclosure provides a semiconductor device and a manufacturing method thereof, especially a semiconductor device for GaN HEMT. In this disclosure, a barrier structure is disposed between the tip drain portion (ie, the fingertip portion) of the drain structure and the gate structure to block the passage of the tip drain portion toward the source. Furthermore, the present disclosure disposes the blocking structure close to the gate structure and away from the drain structure, and connects the blocking structure to the source structure. Thereby, the barrier structure can be maintained at a shutdown potential that ensures the blocking of the transistor channel. In this way, the hot carriers generated and accumulated at the tip drain portion can be eliminated or reduced, and the hot carriers can be prevented from damaging the performance of the semiconductor device or causing damage to the semiconductor device.

The embodiments provided by the present disclosure can be easily integrated into the existing structure and manufacturing process without redesigning the structure and manufacturing process. In this way, considerable process costs and time can be saved. In addition, the embodiments of the present disclosure are performed by modulating the energy band without destroying the barrier layer/channel layer heterostructure in the epitaxial structure. Therefore, compared with the physical isolation method of completely destroying the barrier layer, Embodiments of the present disclosure will not cause additional damage to the device.

The foregoing text summarizes the features of various embodiments or examples, so that those with ordinary knowledge in the art can better understand the present disclosure. Those with ordinary skill in the art should understand that they can easily design or modify other processes and structures based on this disclosure to achieve the same purpose and/or achieve the same advantages as the embodiments or examples introduced herein. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the disclosure, and that various changes, substitutions and alterations can be made to the disclosure without departing from the spirit and scope of the disclosure. .

100,100A~100D,200,200A~200D: semiconductor device 101: Epitaxial structure 102:Substrate 103:Buffer layer 104: Channel layer 105:Barrier layer 106:Channel 110: Source structure 112: Horizontal source part 114:Vertical source part 116: Tip source part 120:Drain structure 122: Horizontal drain part 124: Vertical drain part 126: Tip drain part 130,130A: Gate structure 132,132A,132C: first gate part 134: Second gate part 136,136A: The third gate part 140,140A,140B,210,210A,210B: blocking structure 150: Epitaxial layer 152:Electrode layer 160,230: barrier layer 162,232:Metal layer 170,240: blocking groove 180: Gate groove 220: Connection structure A-A’,B-B’: line segment D1, D2: distance

The present disclosure can be better understood from the following embodiments and drawings. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale and are for illustration purposes only. Figure 1 is a top view of a portion or the entirety of an exemplary semiconductor device according to some embodiments of the present disclosure. Figure 2A is a cross-sectional view of a semiconductor device along line A-A' of Figure 1 according to some embodiments of the present disclosure. Figures 2B, 3, 4 and 5 are cross-sectional views of the semiconductor device along line segment B-B' in Figure 1 according to some embodiments of the present disclosure. FIG. 6 is a top view of a portion or the entirety of an exemplary semiconductor device according to some embodiments of the present disclosure. Figures 7, 8, 9 and 10 are cross-sectional views of a semiconductor device along line segment B-B' in Figure 6 according to some embodiments of the present disclosure. Figure 11 is a flowchart of a method for forming a semiconductor device according to some embodiments of the present disclosure.

100A:Semiconductor device

101: Epitaxial structure

102:Substrate

103:Buffer layer

104: Channel layer

105:Barrier layer

106:Channel

112: Horizontal source part

124: Vertical drain part

126: Tip drain part

130A: Gate structure

132A: First gate part

140A: Barrier structure

150: Epitaxial layer

152:Electrode layer

160:Barrier layer

162:Metal layer

B-B’: line segment

Claims (13)

A semiconductor device including: a substrate; A channel layer is provided above the above-mentioned substrate; A barrier layer is provided above the above-mentioned channel layer; a source structure disposed above the barrier layer, the source structure including a horizontal source portion and at least one vertical source portion; A drain structure disposed above the barrier layer, the drain including a horizontal drain portion and at least one vertical drain portion, wherein a tip source portion of the at least one vertical source portion points toward the horizontal drain portion , and a tip drain portion of the at least one vertical drain portion points toward the horizontal source portion; A gate structure is disposed above the barrier layer. The gate structure includes a first gate portion disposed between the tip drain portion and the horizontal source portion, and a first gate portion disposed on the at least one vertical drain portion. a second gate portion between the portion and the at least one vertical source portion; and A barrier structure is disposed above the barrier layer and between the tip drain portion and the first gate portion. The semiconductor device of claim 1, wherein the barrier structure includes a p-type gallium nitride layer disposed above the barrier layer, and a metal layer disposed above the p-type gallium nitride layer. The semiconductor device of claim 1 further includes a barrier groove, wherein the barrier groove is disposed in the barrier layer, and the barrier structure is disposed in the barrier groove. The semiconductor device of claim 1 further includes a gate recess, wherein the gate recess is disposed in the barrier layer, and the gate structure is disposed in the gate recess. The semiconductor device of claim 1, wherein the first gate portion is arc-shaped, and the barrier structure is also arc-shaped, and a first distance between the barrier structure and the first gate portion is smaller than the barrier A second distance between the structure and the tip drain portion. The semiconductor device of claim 1 further includes a connection structure, the connection structure connects the barrier structure to the source structure. The semiconductor device of claim 1 further includes a connection structure, the connection structure connects the barrier structure to a voltage source. A method of forming a semiconductor device, including: Provide an epitaxial structure. The epitaxial structure includes a substrate, a channel layer above the substrate, and a barrier layer above the channel layer; A source structure and a drain structure are formed above the barrier layer, wherein the source structure includes a horizontal source part and a vertical source part, and the drain structure includes a horizontal drain part and a vertical drain part. pole part; A gate structure is formed above the barrier layer. The gate structure includes a first gate part and a second gate part, wherein the first gate part is between the horizontal source part and the vertical drain part. between a tip drain portion of the portion, and the second gate portion is between the vertical source portion and the vertical drain portion; and A barrier structure is formed above the barrier layer and between the first gate portion and the tip drain portion. The method of forming a semiconductor device according to claim 8 further includes: Before forming the gate structure and the barrier structure, a p-type gallium nitride layer is epitaxially grown on the barrier layer; Patterning the p-type gallium nitride layer to form a first p-type gallium nitride layer; and A first metal layer is formed above the first p-type gallium nitride layer, wherein the first metal layer and the first p-type gallium nitride layer form the gate structure. The method of forming a semiconductor device according to claim 8 further includes: Before forming the gate structure and the barrier structure, a p-type gallium nitride layer is epitaxially grown on the barrier layer; Patterning the p-type gallium nitride layer to form a second p-type gallium nitride layer; and A second metal layer is formed above the second p-type gallium nitride layer, wherein the second metal layer and the second p-type gallium nitride layer form the barrier structure. The method of forming a semiconductor device according to claim 8, further comprising: before forming the gate structure and the barrier structure, digging into the barrier layer to form a first groove in the barrier layer, wherein the gate structure formed in the above-mentioned first groove. The method of forming a semiconductor device according to claim 8, further comprising: before forming the gate structure and the barrier structure, digging into the barrier layer to form a second groove in the barrier layer, wherein the barrier structure forms in the second groove mentioned above. The method of forming a semiconductor device according to claim 8, further comprising implanting fluorine ions in a first region and a second region of the barrier layer, wherein the first region is located under the gate structure, and the second region The area is located beneath the blocking structure described above.

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