TWI843526B - Semiconductor device and fabrication method thereof - Google Patents

Abstract

A semiconductor device includes a substrate having a first conductivity type and including an active region and a peripheral region, a trench disposed in the substrate and located in the active region, and a gate electrode disposed in the trench. A shielding doped region having a second conductivity type is disposed in the substrate and directly below the trench. A buried guard ring having the second conductivity type is disposed in the substrate and located in the peripheral region. The buried guard ring and the shielding doped region are disposed at the same depth in the substrate. In addition, a junction termination extension structure having the second conductivity type is disposed in the substrate, located directly above the buried guard ring and separated from the buried guard ring.

Description

Semiconductor device and method for manufacturing the same

The present disclosure relates to semiconductor technology, and more particularly to a semiconductor device including a trench-type power transistor with a terminal structure and a method for manufacturing the same.

In power electronic systems, power transistors are usually used as power components such as power switches and converters. Power transistors refer to transistors that work under high voltage and high current conditions. The most common power transistors are power diodes, metal-oxide-semiconductor field effect transistors (MOSFET), insulated-gate bipolar transistors (IGBT), etc. Power transistors usually need to be provided with terminal structures at the edges to prevent the electric field from gathering at the edges of the main pn junction, which causes the power transistor to be broken down at a relatively low breakdown voltage.

The terminal structure may include different forms such as field plates, floating guard rings, and junction terminal extensions. However, the known terminal structure usually requires a larger terminal edge width, that is, a larger die size, to achieve the high breakdown voltage required by the power transistor. In addition, the breakdown voltage of the power transistor is easily affected by the spacing width of the known floating guard rings. Therefore, for power transistors, the known terminal structure still cannot fully meet various requirements, such as the requirements for breakdown voltage, die size, process sensitivity, etc.

In view of this, the present disclosure proposes a semiconductor device and a manufacturing method thereof, including a junction terminal extension structure and a buried guard ring disposed in the peripheral area of a substrate to reduce the surface electric field at the end of the main junction and the edge of the terminal structure, and to extend the depletion region so that the terminal edge width of the semiconductor device can be greatly reduced to effectively reduce the chip size, and to reduce the sensitivity of the breakdown voltage of the semiconductor device to the spacing width of the buried guard ring, so as to facilitate the expansion of the process tolerance.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a trench, a gate electrode, a shielding doped region, a buried guard ring, and a junction terminal extension structure. The substrate has a first conductivity type and includes an active region and a peripheral region. The trench is disposed in the substrate and is located in the active region, and the gate electrode is disposed in the trench. The shielding doped region has a second conductivity type, is disposed in the substrate, and is located directly below the trench. The buried guard ring has a second conductivity type, is disposed in the substrate, and is located in the peripheral region, and the buried guard ring and the shielding doped region are at the same depth of the substrate. The junction terminal extension structure has a second conductive type, is disposed in the substrate, is located directly above the buried guard ring, and is separated from the buried guard ring.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising the following steps: providing a substrate, which includes an epitaxial layer of a first conductivity type, and includes an active region and a peripheral region; performing an ion implantation process on the epitaxial layer to form a shielding doped region in the active region, and forming a buried guard ring and a junction terminal extension structure in the peripheral region, wherein the junction terminal extension structure is located directly above the buried guard ring and separated from the buried guard ring, and the shielding doped region, the buried guard ring and the junction terminal extension structure all have a second conductivity type; forming a trench in the epitaxial layer and located in the active region; and forming a gate electrode in the trench.

In order to make the features of the present disclosure clear and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and layouts. The purpose of providing these embodiments is only for illustration and not for any limitation. For example, the description below of "a first feature is formed on or above a second feature" may mean "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, and are not used to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in the present disclosure, such as "below", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they themselves do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupled", "coupled", and "electrically connected" mentioned in the present disclosure include any direct and indirect electrical connection means. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

Although the invention disclosed herein is described below by means of specific embodiments, the inventive principles of the invention disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and the omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a semiconductor device of a trench power transistor including a termination structure and a manufacturing method thereof. The termination structure includes a junction termination extension (JTE) structure and a buried guard ring disposed in a peripheral region of a substrate, which effectively reduces the surface electric field at the main junction end and the edge of the termination structure of the semiconductor device and extends the overall depletion region, thereby significantly reducing the width of the terminal edge of the semiconductor device under the same breakdown voltage condition, thereby effectively reducing the chip size, and reducing the sensitivity of the breakdown voltage of the semiconductor device to the spacing width of the buried guard ring, thereby facilitating the expansion of the process tolerance. In addition, the buried guard ring and the shielding doped region directly below the trench can be formed simultaneously by the same ion implantation process using the same mask, thereby saving the number of masks and process steps, thereby reducing the manufacturing cost of the semiconductor device.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 includes a substrate 101 having a first surface 101F (e.g., front surface) and a second surface 101B (e.g., back surface) opposite to each other, and including a cell region 100A and a termination region 100P. In some embodiments, the composition of the substrate 101 is, for example, silicon carbide (SiC) to facilitate the manufacture of power transistors, such as metal oxide semiconductor field effect transistors (MOSFETs). The substrate 101 may include a drain contact region 103 disposed on the second surface 101B of the substrate, and the drain contact region 103 has a first conductivity type, such as an N-type heavily doped region (N ⁺ ). In addition, the substrate 101 further includes an epitaxial layer 105 formed on the drain contact region 103, and the epitaxial layer 105 has a first conductivity type, such as an N-type lightly doped SiC epitaxial layer (N ^- Epi). In one embodiment, the substrate 101 has a first conductivity type, such as an N-type SiC substrate. The semiconductor device 100 may include a trench gate MOSFET, wherein a trench 120 is disposed in the substrate 101 and is located in the active region 100A, a gate electrode 127 is disposed in the trench 120, and a gate dielectric layer 126 is disposed on the sidewalls and bottom surface of the trench 120 in a longitudinal direction and surrounds the gate electrode 127. The semiconductor device 100 further includes a well region 111 disposed in the substrate 101 and located in the active region 100A. The well region 111 has a second conductivity type, such as a P-type well region (PW), which is adjacent to the side of the trench 120 and surrounds the trench 120. A source contact region 117 is disposed in the well region 111 and located on the first surface 101F of the substrate. The source contact region 117 has a first conductivity type, such as an N-type heavily doped region (N ⁺ ). In addition, a bulk contact region 115 is also disposed in the well region 111 and adjacent to the source contact region 117. The bulk contact region 115 has a first conductivity type, such as a P-type heavily doped region (P ⁺ ). The source contact region 117 and the body contact region 115 are located on one side of the trench 120. In addition, a heavily doped region 116 having a first conductivity type, such as a P-type heavily doped region (P ⁺ ), is also disposed in the well region 111 and is located on the other side of the trench 120. An interlayer dielectric layer 130 is formed on the first surface 101F of the substrate 101, and vias 135 and 137 are formed in the interlayer dielectric layer 130, wherein the via 135 is electrically connected to the source contact region 117 and the body contact region 115, and the via 137 is electrically connected to the heavily doped region 116. The source electrode 136 is formed on the interlayer dielectric layer 130, and the source electrode 136 is electrically coupled to the source contact region 117 and the body contact region 115 through the via 135, and is electrically coupled to the heavily doped region 116 through the via 137. In some embodiments, during the operation of the semiconductor device 100, the source electrode 136 can be electrically coupled to the ground terminal, so that the source contact region 117, the body contact region 115 and the heavily doped region 116 are all electrically coupled to the ground terminal. In addition, the drain electrode 138 is formed on the second surface 101B of the substrate 101 to be electrically connected to the drain contact region 103.

Still referring to FIG. 1 , the semiconductor device 100 further includes a shielding doped region 107 disposed in the substrate 101, located in the active region 100A and directly below the trench 120, and the shielding doped region 107 has a second conductivity type, such as a P-type heavily doped region (P ⁺ ). In addition, according to some embodiments of the present disclosure, the semiconductor device 100 includes a buried guard ring 109 disposed in the substrate 101 and located in the peripheral region 100P, the buried guard ring 109 has a second conductivity type, such as a P-type heavily doped region, and the buried guard ring 109 and the shielding doped region 107 are substantially at the same depth P1 of the substrate 101. The buried guard ring 109 may include a plurality of laterally separated annular doping regions, for example, four annular doping regions 109-1, 109-2, 109-3 and 109-4 are spaced apart from each other along a first direction (eg, X-axis direction), but is not limited thereto. The buried guard ring 109 may include other numbers of annular doping regions. In a top view, the annular doped regions 109-1, 109-2, 109-3 and 109-4 all surround the active region 100A, and the annular doped regions 109-1, 109-2, 109-3 and 109-4 may each independently have a continuous or discontinuous ring shape on a plane (eg, XY plane). In one embodiment, the widths W1, W2, W3 and W4 of the annular doped regions 109-1, 109-2, 109-3 and 109-4 may be the same, and the spacing widths d1, d2 and d3 between the annular doped regions 109-1, 109-2, 109-3 and 109-4 may gradually increase along the first direction (e.g., the X-axis direction) from the active region 100A toward the peripheral region 100P. In another embodiment, the widths W1, W2, W3 and W4 of the annular doped regions 109-1, 109-2, 109-3 and 109-4 may be the same, and the spacing widths d1, d2 and d3 between the annular doped regions 109-1, 109-2, 109-3 and 109-4 may also be the same. In other embodiments, the widths W1, W2, W3 and W4 of the annular doped regions 109-1, 109-2, 109-3 and 109-4 may be different from each other, and the spacing widths d1, d2 and d3 between the annular doped regions 109-1, 109-2, 109-3 and 109-4 may also be different from each other. The widths of the multiple annular doping regions of the buried guard ring 109 and the spacing widths therebetween can be adjusted according to the electric field distribution of the semiconductor device 100, so as to effectively reduce the surface electric field of the peripheral region 100P of the semiconductor device 100, thereby increasing the breakdown voltage, so as to facilitate the semiconductor device 100 to operate at a high voltage. According to some embodiments of the present disclosure, the doping concentrations of the annular doping regions 109-1, 109-2, 109-3 and 109-4 of the buried guard ring 109 are all the same as the doping concentration of the shielding doping region 107. In addition, the shielding doped region 107 and the buried guard ring 109 are laterally separated in a first direction (eg, the X-axis direction), and the buried guard ring 109 and the shielding doped region 107 may have substantially the same thickness T2.

Still referring to FIG. 1 , the semiconductor device 100 further includes a junction termination extension (JTE) structure 113 disposed in the substrate 101, which is formed on the first surface 101F of the substrate and located in the peripheral region 100P. The junction termination extension structure 113 has a second conductivity type, such as a P-type doped region. In one embodiment, the doping concentration of the junction termination extension structure 113 may be lower than the doping concentration of the buried guard ring 109, and the junction termination extension structure 113 is located directly above the buried guard ring 109. Along the second direction (e.g., the Z-axis direction), the junction termination extension structure 113 and the buried guard ring 109 are separated from each other. In one embodiment, the junction termination extension structure 113 includes an inner doped region 113A and a plurality of laterally separated outer doped regions, for example, two outer doped regions 113B-1 and 113B-2 are separated from each other along a first direction (e.g., X-axis direction), but is not limited thereto. The junction termination extension structure 113 may include another number of outer doped regions, and the inner doped region 113A and these outer doped regions 113B-1 and 113B-2 have substantially the same doping concentration. From a top view, the inner doped region 113A and the laterally separated outer doped regions 113B-1 and 113B-2 of the junction terminal extension structure 113 are disposed on one side of the active region 100A, and the inner doped region 113A and the laterally separated outer doped regions 113B-1 and 113B-2 can each independently have a continuous or discontinuous strip shape along a third direction (e.g., the Y-axis direction). In addition, in some embodiments, the vertical projection areas of these laterally separated outer doped regions 113B-1 and 113B-2 are outside the vertical projection area of the buried guard ring 109, that is, the projection areas of the outer doped regions 113B-1 and 113B-2 on the XY plane are outside the projection area of the buried guard ring 109 on the XY plane. In addition, in one embodiment, the outermost edge of the inner doped region 113A is farther from the active region 100A than the outermost edge of the buried guard ring 109, that is, the distance between the edge of the inner doped region 113A adjacent to the outer doped region 113B-1 and the active region 100A is greater than the distance between the outer edge of the annular doped region 109-4 of the buried guard ring 109 and the active region 100A. According to an embodiment of the present disclosure, the outer doping regions 113B-1 and 113B-2 of the junction termination extension structure 113 can further reduce the surface electric field at the edge of the peripheral region 100P, which helps to reduce the sensitivity of the breakdown voltage to the doping concentration of the junction termination extension structure 113. Therefore, the doping concentration of the junction termination extension structure 113 can be lower than the doping concentration of the buried guard ring 109. In addition, in an embodiment, the thickness T1 of the junction termination extension structure 113 can be greater than the thickness T2 of the buried guard ring 109. During operation of the semiconductor device 100 , the buried guard ring 109 and the junction termination extension structure 113 may be electrically coupled to the source electrode 136 via other vias (not shown) penetrating the interlayer dielectric layer 130 and the epitaxial layer 105 , or may be electrically coupled to the ground via other wires (not shown).

According to some embodiments of the present disclosure, the depletion region generated by the junction terminal extension structure 113 combined with the depletion region generated by the buried protection ring 109 can extend and expand the overall depletion region to effectively reduce the electric field at the main junction end of the active region 100A, for example, reduce the electric field at the junction end of the P-type well region 111 and the N-type epitaxial layer 105 at the junction of the active region 100A and the peripheral region 100P, and effectively reduce the surface electric field of the peripheral region 100P. Therefore, under the condition of maintaining the same breakdown voltage, the width of the peripheral region 100P required by the semiconductor device 100 can be greatly shortened, that is, the short side width of the peripheral region 100P in the X-axis direction and the Y-axis direction can be greatly shortened, thereby achieving the effect of reducing the chip size.

In addition, according to some embodiments of the present disclosure, by combining the junction termination extension structure 113 and the buried guard ring 109, since the junction termination extension structure 113 is disposed on the first surface 101F of the substrate and the setting range of the junction termination extension structure 113 is wider than that of the buried guard ring 109, the sensitivity of the breakdown voltage to the spacing width between the multiple annular doped regions 109-1, 109-2, 109-3 and 109-4 of the buried guard ring 109 can be reduced, thereby expanding the process tolerance of manufacturing the semiconductor device 100. In addition, according to some embodiments of the present disclosure, the buried guard ring 109 can be manufactured simultaneously by using a photomask and an ion implantation process to form the shielding doped region 107, thereby saving the manufacturing cost of the semiconductor device 100 and simplifying the manufacturing process steps.

FIG. 2 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present disclosure. In addition to the device features included in the semiconductor device 100 of FIG. 1, the semiconductor device 100 of FIG. 2 further includes a plurality of trench isolation structures disposed in the substrate 101 and located in the peripheral region 100P, such as four trench isolation structures 131, 132, 133, and 134 shown in FIG. 2, but not limited thereto, the semiconductor device 100 may include other numbers of trench isolation structures. These trench isolation structures 131, 132, 133, and 134 are disposed correspondingly directly above the laterally separated annular doped regions 109-1, 109-2, 109-3, and 109-4. In a top view, the trench isolation structures 131, 132, 133, 134 all surround the active region 100A, and the trench isolation structures 131, 132, 133, 134 may each independently have a continuous or discontinuous ring shape on a plane (eg, XY plane). As shown in FIG. 2 , in one embodiment, the trench isolation structures 131, 132, 133, 134 penetrate the junction termination extension structure 113, for example, penetrate the inner doped region 113A of the junction termination extension structure 113, and extend downward to the annular doped regions 109-1, 109-2, 109-3, and 109-4. According to some embodiments of the present disclosure, the trench isolation structures 131, 132, 133, 134 have a plurality of trenches. The trenches can be made simultaneously with the trenches 120 of the active region 100A using the same photomask and in the same etching process, and the trenches of these trench isolation structures 131, 132, 133, 134 can be filled with a dielectric material layer 125 for forming a gate dielectric layer 126, and the bottom surfaces of these trench isolation structures 131, 132, 133, 134 and the bottom surface of the trench 120 located in the active region 100A can be at the same level L1. The details of other component features of the semiconductor device 100 of FIG. 2 can refer to the description of the semiconductor device 100 of FIG. 1, and will not be repeated here. According to one embodiment of the present disclosure, in the semiconductor device 100 of FIG. 2 , the doping concentration of the junction termination extension structure 113 may be the same as the doping concentration of the multiple annular doping regions 109-1, 109-2, 109-3, and 109-4 of the buried guard ring 109. In another embodiment, in the semiconductor device 100 of FIG. 2 , the doping concentration of the junction termination extension structure 113 may be lower than the doping concentration of the multiple annular doping regions 109-1, 109-2, 109-3, and 109-4 of the buried guard ring 109.

FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7 and FIG. 8 are cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Referring to FIG. 3, a wafer 102 is first provided, which includes a first epitaxial layer 105-1 of a first conductivity type deposited on a drain contact region 103. The first epitaxial layer 105-1 is, for example, an N-type lightly doped SiC epitaxial layer, and the drain contact region 103 is, for example, an N-type heavily doped region. The drain contact region 103 can be formed on the back side of the wafer 102 by an ion implantation process, and the first epitaxial layer 105-1 is formed by an epitaxial growth process. The wafer 102 includes an active region 100A and a peripheral region 100P. In step S101, a patterned hard mask 141 is formed on the first epitaxial layer 105-1 through photolithography and etching processes. The patterned hard mask 141 is composed of, for example, silicon oxide or silicon nitride. The patterned hard mask 141 has an opening 142 located in the active region 100A, a plurality of openings 144 located in the peripheral region 100P, a shielding portion 143 between the opening 142 and the opening 144, and a plurality of shielding portions 145 between the plurality of openings 144, wherein the opening 142 located in the active region 100A corresponds to a predetermined formation region of the shielding doped region, and the plurality of openings 142 located in the peripheral region 100P corresponds to a predetermined formation region of a plurality of laterally separated annular doped regions. Next, a first ion implantation process 140 is performed on the first epitaxial layer 105-1 through the opening 142 and the plurality of openings 144 of the patterned hard mask 141, so as to simultaneously form a shielding doping region 107 in the active region 100A and a buried protection ring 109 in the peripheral region 100P, wherein the buried protection ring 109 includes a plurality of laterally separated annular doping regions 109-1, 109-2, 109-3 and 109-4, and the shielding doping region 107 and these annular doping regions 109-1, 109-2, 109-3 and 109-4 all have a second conductivity type, such as a P-type heavily doped region. In some embodiments, the doping concentration of the shielding doped region 107 and the buried guard ring 109 is, for example, about 1E19 to 1E20 atoms/cm ³ .

According to some embodiments of the present disclosure, the shielding doping region 107 and the annular doping regions 109-1, 109-2, 109-3 and 109-4 of the buried protection ring 109 formed by the same first ion implantation process 140 have substantially the same doping concentration, and the shielding doping region 107 and the annular doping regions 109-1, 109-2, 109-3 and 109-4 are at substantially the same level, for example, the bottom surface of the shielding doping region 107 and the bottom surfaces of the annular doping regions 109-1, 109-2, 109-3 and 109-4 are at the same level L2. In addition, the widths W1, W2, W3 and W4 of the annular doped regions 109-1, 109-2, 109-3 and 109-4, as well as the spacing widths d1, d2 and d3 between the annular doped regions 109-1, 109-2, 109-3 and 109-4 can be adjusted according to the electric field distribution of the semiconductor device 100 by adjusting the widths of the multiple openings 144 of the patterned hard mask 141 and the widths of the multiple shielding portions 145, so that the buried guard ring 109 can effectively reduce the electric field of the peripheral region 100P, thereby increasing the breakdown voltage of the semiconductor device 100.

After forming the shielding doped region 107 and the buried guard ring 109, a stripping process, such as an acid soaking or an ashing process, can be used to remove the patterned hard mask 141. Thereafter, referring to FIG. 4, in step S103, a second epitaxial layer 105-2 is deposited on the first epitaxial layer 105-1 by an epitaxial growth process to cover the shielding doped region 107 and the buried guard ring 109. The second epitaxial layer 105-2 also has a first conductivity type, such as an N-type lightly doped SiC epitaxial layer. The first epitaxial layer 105-1 and the second epitaxial layer 105-2 can be collectively referred to as an epitaxial layer 105.

Next, referring to FIG. 4, in step S105, a patterned hard mask 151 is formed on the second epitaxial layer 105-2 through photolithography and etching processes, and the composition of the patterned hard mask 151 is, for example, silicon oxide or silicon nitride. Then, an ion implantation process 150 is performed on the second epitaxial layer 105-2 through the opening of the patterned hard mask 151 to form a well region 111 in the active region 100A, which has a second conductivity type, for example, a P-type well region. The well region 111 is formed directly above the shielding doped region 107, and the well region 111 and the shielding doped region 107 are separated from each other in the depth direction of the epitaxial layer 105. After the well region 111 is formed, the patterned hard mask 151 is removed by a stripping process.

Then, referring to FIG. 5, in step S107, another patterned hard mask 161 is formed on the second epitaxial layer 105-2 through photolithography and etching processes. The patterned hard mask 161 has a plurality of openings 162 and 163 located in the peripheral area 100P, wherein the opening 162 corresponds to the predetermined formation area of the inner doping region of the junction terminal extension structure, and the plurality of openings 163 correspond to the predetermined formation area of the plurality of laterally separated outer doping regions of the junction terminal extension structure. Next, a second ion implantation process 160 is performed on the second epitaxial layer 105-2 through the openings 162 and 163 of the patterned hard mask 161, so as to simultaneously form an inner doping region 113A of a junction termination extension structure 113 and a plurality of laterally separated outer doping regions 113B-1 and 113B-2 in the second epitaxial layer 105-2 of the peripheral region 100P, wherein the inner doping region 113A is adjacent to the well region 111 of the active region 100A. According to some embodiments of the present disclosure, the junction termination extension structure 113 is formed directly above the buried guard ring 109 and is separated from the buried guard ring 109 in the depth direction of the epitaxial layer 105. The inner doped region 113A and the plurality of outer doped regions 113B-1 and 113B-2 of the junction termination extension structure 113 all have the second conductivity type and the same doping concentration, for example, they are P-type doped regions. In one embodiment, the amount of dopant used in the second ion implantation process 160 is lower than the amount of dopant used in the first ion implantation process 140, so that the doping concentration of the junction termination extension structure 113 is lower than the doping concentration of the buried guard ring 109. The doping concentration of the junction termination extension structure 113 is, for example, about 1E17 to 1E18 atoms/ ^cm3 . In other embodiments, the amount of dopant used in the second ion implantation process 160 can be adjusted so that the doping concentration of the junction termination extension structure 113 is equal to or higher than the doping concentration of the buried guard ring 109. In addition, the width of the opening 162 of the patterned hard mask 161 and the number of the plurality of openings 163 can be adjusted according to the electric field distribution of the semiconductor device 100 to control the area range of the inner doped region 113A of the junction terminal extension structure 113 and the number of the plurality of outer doped regions 113B-1 and 113B-2, so that the junction terminal extension structure 113 can effectively reduce the surface electric field of the peripheral region 100P, thereby increasing the breakdown voltage of the semiconductor device 100. After the junction terminal extension structure 113 is formed, the patterned hard mask 161 is removed by a stripping process.

Then, referring to FIG. 6 , in step S109, a patterned hard mask 171 is formed on the second epitaxial layer 105-2 through photolithography and etching processes, and then an ion implantation process 170 is performed on the second epitaxial layer 105-2 through the opening of the patterned hard mask 171 to form a substrate contact region 115 and a heavily doped region 116 in the well region 111, both of which have a second conductivity type, such as a P-type heavily doped region. Thereafter, the patterned hard mask 171 is removed by a stripping process.

Next, referring to FIG. 6, in step S111, another patterned hard mask 181 is formed on the second epitaxial layer 105-2 through photolithography and etching processes, and then an ion implantation process 180 is performed on the second epitaxial layer 105-2 through the opening of the patterned hard mask 181 to form a source contact region 117 in the well region 111, which has a first conductivity type, such as an N-type heavily doped region, and the source contact region 117 is adjacent to the substrate contact region 115. Thereafter, the patterned hard mask 181 is removed by a stripping process.

Then, referring to FIG. 7 , in step S113, another patterned hard mask 191 is formed on the second epitaxial layer 105-2, and then an etching process is performed on the second epitaxial layer 105-2 of the active region 100A through the opening of the patterned hard mask 191 to form a trench 120 passing through the well region 111 and the second epitaxial layer 105-2 to reach the shielding doped region 107, wherein the source contact region 117 and the heavily doped region 116 are respectively located on both sides of the trench 120. Thereafter, the patterned hard mask 191 is removed by a stripping process. In addition, after removing the patterned hard mask 191, a sacrificial oxide layer can be formed on the sidewalls and bottom surface of the trench 120 using a thermal oxidation process, and then the sacrificial oxide layer can be removed using an acid soaking process to repair surface defects on the sidewalls and bottom surface of the trench 120 caused by the etching process, which is beneficial to improving the quality of the gate dielectric layer subsequently formed in the trench 120.

Next, referring to FIG. 7 , in step S115, a dielectric material layer 125, such as a silicon oxide layer, is first conformally deposited on the sidewalls and bottom surface of the trench 120 and the surface of the second epitaxial layer 105-2, wherein the dielectric material layer formed on the sidewalls and bottom surface of the trench 120 serves as a gate dielectric layer 126. Then, a conductive material, such as polysilicon, is fully deposited on the dielectric material layer 125, and the conductive material fills the trench 120 and covers the gate dielectric layer 126. Next, an etch-back process is performed to remove the conductive material outside the trench 120 to form a gate electrode 127 in the trench 120. In one embodiment, the top surface of the gate electrode 127 can be flush with or lower than the top surfaces of the source contact region 117 and the heavily doped region 116.

Then, referring to FIG. 8 , in step S117, an interlayer dielectric layer 130 is deposited all over the epitaxial layer 105, and a plurality of contact openings 155 and 157 are formed in the interlayer dielectric layer 130 by photolithography and etching processes, wherein the contact opening 155 exposes a portion of the source contact region 117 and a portion of the substrate contact region 115, and the contact opening 157 exposes a portion of the heavily doped region 116. In addition, other contact openings (not shown) may be formed in the interlayer dielectric layer 130 to subsequently form a plurality of contacts electrically coupled to the gate electrode 127, the junction termination extension structure 113, and the buried protection ring 109, respectively.

Next, referring to FIG. 8 , in step S119, a metal material may be first deposited longitudinally on the surface of the interlayer dielectric layer 130 and in the contact openings 155 and 157, and a rapid thermal annealing process may be used to allow the metal material to react with the material of the epitaxial layer to form a metal silicide. The unreacted metal material may then be removed to form a barrier layer (not shown) on the side walls and bottom surface of the contact openings 155 and 157. Then, a deposition process is used to deposit a conductive material on the interlayer dielectric layer 130, and the conductive material fills the contact openings 155 and 157 to form vias 135 and 137. The conductive material is then patterned using photolithography and etching processes to form a metal wire layer including a source electrode 136 on the interlayer dielectric layer 130, wherein the source electrode 136 is electrically coupled to the source contact region 117 and the substrate contact region 115 through the via 135, and is electrically coupled to the heavily doped region 116 through the via 137. In one embodiment, the metal material forming the barrier layer is, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) or other suitable diffusion barrier materials, and the conductive material of the vias 135, 137 and the source electrode 136 is, for example, aluminum copper (AlCu), aluminum (Al), copper (Cu) or other suitable conductive metal materials. In addition, in step S119, other vias and metal wires can be formed at the same time to electrically couple to the gate electrode 127, the junction terminal extension structure 113 and the buried guard ring 109, respectively, wherein the junction terminal extension structure 113 and the buried guard ring 109 can be further electrically coupled to the source electrode 136 or the ground terminal, so that the junction terminal extension structure 113 and the buried guard ring 109 can further reduce the surface electric field of the semiconductor device 100 to increase the breakdown voltage. Afterwards, a deposition process can be used to form a drain electrode 138 on the bottom surface of the drain contact region 103 to complete the semiconductor device 100 of FIG. 1.

FIG. 9 is a cross-sectional schematic diagram of an intermediate stage of a method for manufacturing the semiconductor device 100 of FIG. 2 according to another embodiment of the present disclosure. In this embodiment, before step S114 of FIG. 9, the steps of FIG. 3, FIG. 4, FIG. 5 and FIG. 6 may be performed first. After step S111 of FIG. 6 is performed, then, referring to FIG. 9, in step S114, a patterned hard mask 192 is formed on the second epitaxial layer 105-2, and then the second epitaxial layers of the active region 100A and the peripheral region 100P are simultaneously exposed to the light through the plurality of openings of the patterned hard mask 192. The crystal layer 105-2 is etched to form a trench 120 in the active region 100A, which passes through the well region 111 and the second epitaxial layer 105-2 and extends downward to the shielding doped region 107, and at the same time, a plurality of annular trenches 121, 122, 123, and 124 are formed in the peripheral region 100P. These annular trenches pass through the inner doped region 113A of the junction terminal extension structure 113 and the second epitaxial layer 105-2 and extend downward to the plurality of annular doped regions 109-1, 109-2, 109-3, and 109-4 of the buried protection ring 109. In this embodiment, the trench 120 is formed directly above the shielding doping region 107, and a plurality of annular trenches 121, 122, 123, and 124 are simultaneously formed directly above the buried protection ring 109. Thereafter, the patterned hard mask 192 is removed by a stripping process.

Next, referring to FIG. 9, in step S116, a dielectric material layer 125, such as a silicon oxide layer, is deposited on the sidewalls and bottom surface of the trench 120 and the surface of the epitaxial layer 105 in a longitudinal direction, and the dielectric material layer 125 fills a plurality of annular trenches 121, 122, 123, 124 to form a plurality of trench isolation structures 131, 132, 133, and 134, wherein the dielectric material layer formed on the sidewalls and bottom surface of the trench 120 serves as a gate dielectric layer 126. After step S116 in FIG. 9, steps S117 and S119 in FIG. 8 may be performed to complete the semiconductor device 100 in FIG. 2.

FIG. 10 is a schematic cross-sectional view of an intermediate stage of a method for manufacturing the semiconductor device 100 of FIG. 2 according to yet another embodiment of the present disclosure. In this embodiment, referring to the aforementioned FIGS. 3 and 4, before step S101 of forming the shielding doping region 107 and the buried protection ring 109, an epitaxial growth process is first performed to form an epitaxial layer 105 on the drain contact region 103. In this embodiment, there is no need to deposit the first epitaxial layer 105-1 and the second epitaxial layer 105-2 separately, and the epitaxial layer 105 can be formed using one epitaxial growth process. Thereafter, referring to the steps of FIG. 4 and FIG. 6, a well region 111, a source contact region 117, a substrate contact region 115, and a heavily doped region 116 are formed. In one embodiment, before step S104 of FIG. 10, a junction terminal extension structure 113 and a buried protection ring 109 have not been formed in the epitaxial layer 105 of the peripheral region 100P, and a shielding doped region 107 has not been formed in the epitaxial layer 105 of the active region 100A. Next, referring to FIG. 10 , in step S104, a patterned hard mask 192 is formed on the epitaxial layer 105, and then an etching process is performed on the epitaxial layer 105 in the active region 100A and the peripheral region 100P through the multiple openings of the patterned hard mask 192 to form a trench 120 in the active region 100A, which extends downward through the well region 111, and simultaneously form a plurality of annular trenches 121, 122, 123, 124 in the peripheral region 100P, and the bottom surface of the trench 120 and the bottom surfaces of the annular trenches 121, 122, 123, 124 can be at the same depth of the epitaxial layer 105. Thereafter, the patterned hard mask 192 is removed by a stripping process.

Next, referring to FIG. 10 , in step S106 , another patterned hard mask 193 is formed on the epitaxial layer 105 , which has a plurality of openings, respectively exposing the predetermined formation areas of the inner doped region 113A and a plurality of outer doped regions 113B-1 and 113B-2 of the trench 120 and the junction terminal extension structure 113 . Then, an ion implantation process 190 is performed on the epitaxial layer 105 through the multiple openings of the patterned hard mask 193 and the trench 120 and the multiple annular trenches 121, 122, 123, 124 to form a shielding doped region 107 directly below the trench 120 of the active region 100A and simultaneously in the multiple annular trenches of the peripheral region 100P. A plurality of annular doped regions 109-1, 109-2, 109-3 and 109-4 of the buried guard ring 109 are formed directly below the junction termination extension structure 113, and an inner doped region 113A and a plurality of outer doped regions 113B-1 and 113B-2 of the junction termination extension structure 113 are formed in the peripheral region 100P. In this embodiment, the shielding doped region 107, the junction termination extension structure 113 and the buried guard ring 109 can be formed by the same ion implantation process 190 and have substantially the same doping concentration. Thereafter, the patterned hard mask 193 is removed by a stripping process. After performing step S106 of FIG. 10, step S116 of FIG. 9 and steps S117 and S119 of FIG. 8 may be performed to complete the semiconductor device 100 of FIG. 2. In this embodiment, the epitaxial layer 105 may be formed by an epitaxial growth step, and the shielding doped region 107, the junction terminal extension structure 113 and the buried protection ring 109 may be formed simultaneously by the same ion implantation process, so as to reduce the process steps of the semiconductor device 100 of FIG. 2, thereby reducing the manufacturing cost.

According to some embodiments of the present disclosure, a junction terminal extension structure and a buried guard ring are combined in the peripheral region of a semiconductor device, so that the overall depletion region of the peripheral region can be extended and expanded to effectively reduce the electric field at the end of the main junction of the active region and the surface electric field of the peripheral region. Therefore, under the condition of maintaining the same breakdown voltage, the peripheral region width required by the semiconductor device can be greatly shortened. For example, compared with the peripheral region width required by the known terminal structure, the semiconductor device disclosed in the present disclosure can reduce the peripheral region width to less than one-fourth of the known width, thereby reducing the chip size.

In addition, according to some embodiments of the present disclosure, the buried guard ring and shielding doping region of the semiconductor device can be formed simultaneously by the same photomask and the same ion implantation process, thereby reducing the manufacturing cost of the semiconductor device. The above is only a preferred embodiment of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

100: semiconductor device 100A: active region 100P: peripheral region 101: substrate 101B: second surface 101F: first surface 102: wafer 103: drain contact region 105: epitaxial layer 105-1: first epitaxial layer 105-2: second epitaxial layer 107: shielding doping region 109: buried protection ring 109-1, 109-2, 109-3, 109-4: annular doping region 111: well region 113: junction terminal extension structure 113A: inner doping region 113B-1, 113B-2: outer doping region 115: substrate contact region 116: heavily doped region 117: source contact region 120: trench 121, 122, 123, 124: annular trench 125: dielectric material layer 126: gate dielectric layer 127: gate electrode 130: interlayer dielectric layer 131, 132, 133, 134: trench isolation structure 135, 137: via hole 136: source electrode 138: drain electrode 140: first ion implantation process 141, 151, 161, 171, 181, 191, 192, 193: patterned hard mask 142, 144, 162, 163: opening 143, 145: masking part 150, 170, 180, 190: ion implantation process 155, 157: contact opening 160: second ion implantation process W1, W2, W3, W4: width d1, d2, d3, d4: interval width T1, T2: thickness P1: depth L1, L2: horizontal height S101, S103, S104, S105, S106, S107, S109, S111, S113, S114, S115, S116, S117, S119: Steps

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to at the same time when reading this disclosure. Through the specific embodiments in this article and referring to the corresponding drawings, the specific embodiments of the disclosure are explained in detail, and the working principle of the specific embodiments of the disclosure is explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced. Figure 1 is a cross-sectional schematic diagram of a semiconductor device drawn according to an embodiment of the disclosure. Figure 2 is a cross-sectional schematic diagram of a semiconductor device drawn according to another embodiment of the disclosure. FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7 and FIG. 8 are cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 9 is a cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. FIG. 10 is a cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a semiconductor device according to yet another embodiment of the present disclosure.

100:Semiconductor devices

100A: Active zone

100P: Peripheral area

101: Base

101B: Second surface

101F: First surface

103: Drain contact area

105: Epitaxial layer

107: Shielding mixed area

109:Buried protective ring

109-1, 109-2, 109-3, 109-4: Ring-shaped doping area

111: Well area

113: Interface terminal extension structure

113A: medial mixed area

113B-1, 113B-2: Outer doping area

115: substrate contact area

116:Heavy mixing area

117: Source contact area

120: Groove

126: Gate dielectric layer

127: Gate electrode

130: Interlayer dielectric layer

135, 137: Conductive hole

136: Source electrode

138: Drain electrode

W1, W2, W3, W4: Width

d1, d2, d3, d4: interval width

T1, T2: thickness

P1: Depth

Claims (20)

A semiconductor device comprises: a substrate having a first conductivity type, including an active region and a peripheral region; a trench disposed in the substrate and located in the active region; a gate electrode disposed in the trench; a shielding doped region having a second conductivity type, disposed in the substrate and located directly below the trench; a buried guard ring having the second conductivity type, disposed in the substrate and located in the peripheral region, and the buried guard ring and the shielding doped region are at the same depth of the substrate; and a junction terminal extension structure having the second conductivity type, disposed in the substrate, located directly above the buried guard ring, and separated from the buried guard ring. A semiconductor device as described in claim 1, wherein the junction terminal extension structure includes an inner doping region and a plurality of laterally separated outer doping regions, and the inner doping region and the plurality of laterally separated outer doping regions have the same doping concentration. A semiconductor device as described in claim 2, wherein the vertical projection areas of the plurality of laterally separated outer doping regions are outside the vertical projection area of the buried guard ring. A semiconductor device as described in claim 2, wherein the outermost edge of the inner doped region is farther away from the active region than the outermost edge of the buried guard ring. A semiconductor device as described in claim 1, wherein the buried guard ring includes a plurality of laterally separated annular doping regions, and the doping concentrations of the plurality of laterally separated annular doping regions are the same as the doping concentration of the shielding doping region. A semiconductor device as described in claim 5, wherein the plurality of intervals between the plurality of laterally separated annular doped regions gradually increase in a direction from the active region to the peripheral region. A semiconductor device as described in claim 5, wherein the plurality of laterally separated annular doped regions have the same width. The semiconductor device as described in claim 5 further includes a plurality of trench isolation structures disposed in the substrate and located in the peripheral region, wherein the plurality of trench isolation structures are correspondingly disposed directly above the plurality of laterally separated annular doped regions. A semiconductor device as described in claim 8, wherein the plurality of trench isolation structures penetrate the junction terminal extension structure, and the bottom surfaces of the plurality of trench isolation structures and the bottom surface of the trench are at the same level. A semiconductor device as described in claim 1, wherein the doping concentration of the junction terminal extension structure is lower than the doping concentration of the buried guard ring. A semiconductor device as described in claim 1, wherein the thickness of the junction terminal extension structure is greater than the thickness of the buried guard ring. A semiconductor device as described in claim 1, wherein the shielding doped region and the buried guard ring are laterally separated, and the buried guard ring and the shielding doped region have the same thickness. A semiconductor device as described in claim 1, wherein the buried guard ring and the junction terminal extension structure are electrically coupled to a source electrode or a ground terminal. A method for manufacturing a semiconductor device, comprising: Providing a substrate, comprising an epitaxial layer having a first conductivity type, and comprising an active region and a peripheral region; Performing an ion implantation process on the epitaxial layer to form a shielding doped region in the active region, a buried guard ring and a junction terminal extension structure in the peripheral region, the junction terminal extension structure is located directly above the buried guard ring and separated from the buried guard ring, the shielding doped region, the buried guard ring and the junction terminal extension structure all have a second conductivity type; Forming a trench in the epitaxial layer, located in the active region; and Forming a gate electrode in the trench. A method for manufacturing a semiconductor device as described in claim 14, wherein the epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked in sequence from bottom to top, the second epitaxial layer covers the shielding doped region and the buried guard ring, and the junction terminal extension structure is formed in the second epitaxial layer. A method for manufacturing a semiconductor device as described in claim 14, wherein forming the junction terminal extension structure includes simultaneously forming an inner doping region and a plurality of laterally separated outer doping regions, and forming the buried protection ring includes simultaneously forming a plurality of laterally separated annular doping regions, the doping concentrations of the plurality of laterally separated annular doping regions are the same as the doping concentration of the shielding doping region, and the plurality of laterally separated annular doping regions and the shielding doping region are at the same level. A method for manufacturing a semiconductor device as described in claim 14, wherein the step of forming the trench also includes simultaneously forming a plurality of annular trenches in the epitaxial layer, located in the peripheral region, and the trench is formed directly above the shielding doping region, and the plurality of annular trenches are formed directly above the buried protective ring. A method for manufacturing a semiconductor device as described in claim 17, wherein the ion implantation process includes a first ion implantation process and a second ion implantation process, the shielding doping region and the buried guard ring are formed simultaneously by the first ion implantation process, the junction terminal extension structure is formed by the second ion implantation process, and the trench and the plurality of annular trenches are formed after the shielding doping region, the buried guard ring and the junction terminal extension structure are formed. A method for manufacturing a semiconductor device as described in claim 17, wherein the shielding doping region, the buried guard ring and the junction terminal extension structure are formed simultaneously by the ion implantation process, and the trench and the plurality of annular trenches are formed before forming the shielding doping region, the buried guard ring and the junction terminal extension structure. The method for manufacturing a semiconductor device as described in claim 17 also includes depositing a dielectric material layer, which is formed longitudinally on the side walls and bottom surface of the trench to form a gate dielectric layer, and the dielectric material layer fills the plurality of annular trenches to form a plurality of trench isolation structures.

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