TWI854618B - Semiconductor device and fabrication method thereof - Google Patents

Abstract

A semiconductor device includes a trench disposed in a substrate, a gate electrode disposed in the trench, a source contact region disposed on a first surface of the substrate, a drain contact region disposed on a second surface of the substrate, a heavily doped region disposed directly under the trench, and a current spreading layer disposed in the substrate to surround the bottom of the trench and the heavily doped region. The heavily doped region has a first conductivity type, and in a first direction, the width of the heavily doped region is smaller than the width of the trench. The current spreading layer has a second conductivity type and a graded doping concentration, where the graded doping concentration is gradually increased along the first direction from the heavily doped region toward the outside of the current spreading layer.

Description

Semiconductor device and method for manufacturing the same

This disclosure relates to semiconductor technology, and in particular to semiconductor devices including trench-type power transistors and methods for manufacturing the same.

In power electronics systems, power transistors are usually used as power components such as power switches and converters. Power transistors refer to transistors that work under high voltage and high current conditions. The most common power transistors are power metal-oxide-semiconductor field effect transistors (power MOSFETs), which include horizontal structures such as laterally-diffused MOS (LDMOS) field effect transistors (FETs), and vertical structures such as planar gate MOSFETs, trench gate MOSFETs, and MOSFETs. MOSFET), in which the gate is set in the trench. Compared with the planar gate MOSFET, the trench gate MOSFET has the advantages of reducing the size of the component unit and reducing the parasitic capacitance. However, the known trench gate MOSFET still cannot fully meet the requirements in various aspects, such as the requirements for on-state resistance (Ron), breakdown voltage and reliability.

In view of this, the present disclosure proposes a semiconductor device and a manufacturing method thereof, which reduces the width of the heavily doped region disposed directly below the trench-type gate as an electric field shielding structure to be smaller than the width of the trench, and allows the current spreading layer surrounding the trench bottom and the heavily doped region to have a laterally gradient doping concentration, so as to improve the breakdown voltage and reliability of the semiconductor device.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a trench, a gate electrode, a source contact region, a drain contact region, a heavily doped region, and a current spreading layer. The substrate has a first surface and a second surface, a trench is arranged in the substrate, a gate electrode is arranged in the trench, a source contact region is arranged on the first surface of the substrate, a drain contact region is arranged on the second surface of the substrate, a heavily doped region with a first conductivity type is arranged directly below the trench, and in a first direction, the width of the heavily doped region is smaller than the width of the trench, and a current spreading layer with a second conductivity type is arranged in the substrate and surrounds the bottom of the trench and the heavily doped region, and the current spreading layer has a gradient doping concentration, and along the first direction, the gradient doping concentration increases gradually from the heavily doped region to the outside.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising the following steps: providing a wafer, comprising a drain contact region, a first epitaxial layer and a second epitaxial layer, stacked in sequence from bottom to top; forming a patterned mask on the second epitaxial layer, the patterned mask comprising a plurality of openings, wherein the plurality of widths of the openings increase in sequence from the inside to the outside in a first direction; performing an ion implantation process on the second epitaxial layer through the openings of the patterned mask to form a plurality of doped regions; depositing A third epitaxial layer is deposited on the second epitaxial layer, and the doped regions and the second epitaxial layer form a current spreading layer, the current spreading layer has a gradient doping concentration, and the gradient doping concentration increases from the inside to the outside along the first direction; a source contact region is formed in the third epitaxial layer; a trench is formed, passing through the third epitaxial layer and reaching the current spreading layer; a heavily doped region is formed directly below the trench, and the width of the heavily doped region in the first direction is smaller than the width of the trench; and a gate electrode is formed in the trench.

In order to make the features of this disclosure clear and easy to understand, the following is a detailed description of the embodiments with the help of the attached drawings.

100:Semiconductor devices

100U: Repeat unit

101: First epitaxial layer

102: Second epitaxial layer

103: Drain contact area

105: Current dispersion layer

105-1: Inner area

105-2, 105-3, 105-4, 105-5: Area

105-6: Outer area

106: The third epitaxial layer

107: Well area

110: Base

110A: First surface

110B: Second surface

111: Source contact area

113: substrate contact area

115:Heavy mixing area

117: Gate dielectric layer

119: Gate electrode

120, 120-1, 120-2: Grooves

121: Contact opening

122: Interlayer dielectric layer

123: Barrier layer

124: Conductive hole

126: Source electrode

128: Drain electrode

130: Wafer

140, 150, 160, 180: Ion implantation process

141, 145, 161, 171: Patterned mask

142: Open mouth

143: Shielded part

151, 152, 153, 154, 155: Mixed areas

181: Spacer

L1, L2, L3: Width

H1: Depth

P1: Spacing

S101, S103, S105, S107, S109, S111, S113, S115, S117, S119: Steps

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to simultaneously when reading this disclosure. Through the specific embodiments in this article and reference to the corresponding drawings, the specific embodiments of this disclosure are explained in detail, and the working principles of the specific embodiments of this disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a schematic cross-sectional view of a portion of a semiconductor device according to an embodiment of the present disclosure, wherein the dimensions of some features are marked and two repeated units are included.

Figures 3, 4, 5, 6, 7, 8, 9 and 10 are cross-sectional schematic diagrams showing some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for limitation. For example, the description below of "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of semiconductor devices during use and operation. As the orientation of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupling", "coupling", and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

Although the invention disclosed herein is described below by means of specific embodiments, the inventive principle disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a semiconductor device including a trench power transistor and a manufacturing method thereof. One of the purposes of the present disclosure is to reduce the width of a heavily doped region disposed directly below the trench as an electric field shielding structure to be smaller than the width of the trench, and to provide a current spreading layer (CSL) surrounding the bottom of the trench and the heavily doped region with a laterally gradient doping concentration, so as to reduce the resistance of the junction field effect transistor (JFET) effect generated at the bottom of the trench, and at the same time effectively reduce the electric field strength at the bottom of the trench gate, thereby improving the breakdown voltage and reliability of the semiconductor device.

FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes a substrate 110 having a first surface 110A (e.g., a front surface) and a second surface 110B (e.g., a back surface) opposite to each other. The substrate 110 may include a drain contact region 103 disposed on the second surface 110B of the substrate, and the drain contact region 103 has a second conductivity type, such as an N-type heavily doped region (N ⁺ ). The substrate 110 further includes a first epitaxial layer 101 deposited on the drain contact region 103, and the first epitaxial layer 101 has a second conductivity type, such as an N-epitaxial layer. In addition, the semiconductor device 100 includes a source contact region 111 disposed on the first surface 110A of the substrate. The source contact region 111 has a second conductivity type, such as an N-type heavily doped region (N ⁺ ). In some embodiments, the substrate 110 is made of, for example, silicon carbide (SiC). As shown in FIG. 1 , the semiconductor device 100 further includes a trench 120 disposed in the substrate 110, a gate electrode 119 disposed in the trench 120, and a gate dielectric layer 117 disposed longitudinally on the sidewalls and bottom surface of the trench 120 and surrounding the gate electrode 119 to form a trench power transistor of the semiconductor device 100, such as a trench power metal oxide semiconductor field effect transistor (trench power MOSFET). In addition, the semiconductor device 100 includes a well region 107 disposed in the substrate 110 and adjacent to the side of the trench 120, the well region 107 having a first conductivity type, such as a P-type well region (PW), and a source contact region 111 disposed in the well region 107. The semiconductor device 100 further includes a bulk contact region 113 disposed in the well region 107 and adjacent to the source contact region 111, the bulk contact region 113 having a first conductivity type, such as a P-type heavily doped region (P ⁺ ). In addition, an interlayer dielectric layer 122 is formed on the first surface 110A of the substrate 110, and a via 124 is formed in the interlayer dielectric layer 122. The barrier layer 123 can be lined in the contact opening of the interlayer dielectric layer 122 and surround the via 124. The source electrode 126 is formed on the interlayer dielectric layer 122 and is electrically coupled to the source contact area 111 and the substrate contact area 113 through the via 124.

Still referring to FIG. 1 , the semiconductor device 100 further includes a heavily doped region 115 disposed directly below the trench 120 . The heavily doped region 115 has a first conductivity type, such as a P-type heavily doped region (P ⁺ ). The heavily doped region 115 can be used as an electric field shielding structure to reduce the electric field at the bottom of the trench gate. According to some embodiments of the present disclosure, in a first direction (such as the X-axis direction), the width of the heavily doped region 115 is smaller than the width of the trench 120 , and the bottom corner of the trench 120 will not be covered by the heavily doped region 115 . In addition, the semiconductor device 100 further includes a current spreading layer 105 disposed in the substrate 110, and the current spreading layer 105 surrounds the bottom of the trench 120 and the heavily doped region 115. The epitaxial layer 101 is located between the drain contact region 103 and the current spreading layer 105, and the current spreading layer 105 is located between the well region 107 and the epitaxial layer 101. According to some embodiments of the present disclosure, the current spreading layer 105 has a gradient doping concentration. Along a first direction (e.g., the X-axis direction), the opening size of the patterned ion distribution mask is adjusted to gradually change, so as to generate a corresponding gradient doping concentration, which gradually increases from the heavily doped region 115 to the outer side of the current spreading layer 105, that is, the current spreading layer 105 has a laterally graded doping concentration.

As shown in FIG. 1 , in one embodiment, the current spreading layer 105 may include a plurality of regions 105-1, 105-2, 105-3, 105-4, 105-5 and 105-6. The current spreading layer 105 has a second conductivity type (eg, N-type). That is, the regions 105-1 to 105-6 all have a second conductivity type (eg, N-type). Along a first direction (e.g., the X-axis direction), the doping concentrations of the regions 105-1 to 105-6 increase sequentially from the inner region 105-1 to the outer region 105-6, wherein the inner region 105-1 has the lowest doping concentration in the current spreading layer 105, and the outer region 105-6 has the highest doping concentration in the current spreading layer 105. In addition, the inner region 105-1 directly contacts the heavily doped region 115 and the bottom corner of the trench 120, and the gate dielectric layer 117 is located between the inner region 105-1 and the gate electrode 119. In addition, the lowest doping concentration of the inner region 105-1 is lower than the doping concentration of the first epitaxial layer 101, the highest doping concentration of the outer region 105-6 is higher than the doping concentration of the first epitaxial layer 101, and the doping concentrations of the other regions 105-2 to 105-5 are between the lowest doping concentration of the inner region 105-1 and the highest doping concentration of the outer region 105-6. In some embodiments, the doping concentration of the inner region 105-1 to the region 105-3 is, for example, in the range of about 1E15 to 1E16 atoms/ ^cm3 , and the doping concentration of the region 105-4 to the outer region 105-6 is, for example, in the range of about 1E16 to 1E17 atoms/ ^cm3 , but is not limited thereto. The number of regions of the current spreading layer 105 and the doping concentration range of each region can be adjusted according to electrical requirements to generate a laterally gradient doping concentration.

Generally speaking, in a known trench power MOSFET, a known shielding structure located below the bottom of the trench gate extends laterally to cover the bottom corner of the trench to reduce the electric field at the bottom corner of the trench. However, the known shielding structure also generates a junction field effect transistor (JFET) effect between the sidewall of the bottom corner of the trench and the well region, thereby generating a higher junction field effect transistor (JFET) resistance. In a trench power MOSFET, the conventional current spreading layer in contact with the shielding structure needs to have a much higher doping concentration than the epitaxial layer to reduce the resistance generated by the junction field effect transistor (JFET). However, a higher electric field is generated at the junction of the conventional current spreading layer with a higher doping concentration and the gate dielectric layer located on the sidewall of the trench, resulting in a decrease in the breakdown voltage of the conventional trench power MOSFET and the reliability of the gate dielectric layer.

According to some embodiments of the present disclosure, the width of the heavily doped region 115 serving as an electric field shielding structure in the semiconductor device 100 is smaller than the width of the trench 120, and the heavily doped region 115 does not extend laterally to the bottom corner of the trench 120. Therefore, the junction field effect transistor (JFET) effect generated at the bottom corner of the trench 120 can be greatly reduced, thereby reducing the resistance generated by the JFET. Furthermore, in the semiconductor device 100 of some embodiments of the present disclosure, the inner region 105-1 of the current spreading layer 105 has the lowest doping concentration, which is much lower than the doping concentration of the first epitaxial layer 101. Therefore, the inner region 105-1 of the second conductivity type with the lowest doping concentration can provide an electric field shielding effect similar to that of the heavily doped region 115 of the first conductivity type. In addition, the inner region 105-1 contacts the heavily doped region 115 and surrounds the bottom of the trench 120. The combination of the heavily doped region 115 with reduced width and the inner region 105-1 with reduced doping concentration of the current spreading layer 105 can effectively reduce the electric field at the bottom of the trench gate, thereby increasing the breakdown voltage of the semiconductor device 100 and improving the reliability of the gate dielectric layer 117. At the same time, the outer region 105-6 of the current spreading layer 105 has the highest doping concentration, which is much higher than the doping concentration of the first epitaxial layer 101. Therefore, the outer region 105-6 and other regions 105-5 and 105-4 with the second highest doping concentration can achieve the effect of spreading the current, effectively reducing the impedance, and thus reducing the on-resistance (Ron) of the semiconductor device 100. In addition, since the current spreading layer 105 has a laterally gradient doping concentration, it can avoid sudden changes in the electric field strength of the semiconductor device 100, thereby improving the reliability of the semiconductor device 100.

FIG. 2 is a cross-sectional schematic diagram of a portion of a semiconductor device 100 according to an embodiment of the present disclosure, which indicates the relevant dimensions of the heavily doped region 115 and the trench 120 of the semiconductor device 100, and FIG. 2 includes two repeating units 100U of the semiconductor device 100. Referring to FIG. 2, in a first direction (e.g., the X-axis direction), the heavily doped region 115 has a width L1, and the trench 120 has a width L2, and the width L1 of the heavily doped region 115 is smaller than the width L2 of the trench 120. In addition, the trench 120 has a depth H1, and the width L1 of the heavily doped region 115 can be adjusted according to the actual conditions of the depth H1 and the width L2 of the trench 120. For example, when the depth H1 of the trench 120 is greater, the width L1 of the heavily doped region 115 can be increased or decreased accordingly. In addition, in the first direction (for example, the X-axis direction), the width L1 of the heavily doped region 115 can be smaller than the width L3 of the gate electrode 119, and the heavily doped region 115 can provide sufficient electric field shielding effect to effectively reduce the electric field at the bottom of the gate 119. As shown in FIG. 2, a gate electrode 119 is disposed in a trench 120-1 of a repeating unit 100U of a semiconductor device 100, and another gate electrode 119 is disposed in a trench 120-2 of another adjacent repeating unit 100U. A plurality of repeating units 100U of the semiconductor device 100 are formed in the same substrate 110. In addition, there is a spacing P1 between the trench 120-1 and another adjacent trench 120-2, and the width L1 of the heavily doped region 115 can be adjusted according to the spacing P1. For example, when the spacing P1 is smaller, the width L1 of the heavily doped region 115 can be reduced accordingly.

FIG3, FIG4, FIG5, FIG6, FIG7, FIG8, FIG9 and FIG10 are cross-sectional schematic diagrams of some stages of a method for manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Referring to FIG3, a wafer 130 is first provided. In some embodiments, the wafer 130 may include a drain contact region 103, a first epitaxial layer 101 and a second epitaxial layer 102, which are stacked in sequence from bottom to top, and the drain contact region 103, the first epitaxial layer 101 and the second epitaxial layer 102 all have a second conductivity type (e.g., N-type), wherein the doping concentration of the second epitaxial layer 102 is higher than the doping concentration of the first epitaxial layer 101. In some embodiments, the composition of the wafer 130 is, for example, silicon carbide (SiC), wherein the drain contact region 103 is, for example, an N-type heavily doped region, and the second conductivity type (e.g., N-type) doping ions can be implanted on the back of the semiconductor substrate of the silicon carbide (SiC) through an ion implantation process to form the drain contact region 103. The first epitaxial layer 101 is, for example, an N-type doped silicon carbide (SiC) epitaxial layer, and the silicon carbide (SiC) epitaxial layer can be deposited on the drain contact region 103 through an epitaxial growth process, and the second conductivity type (N-type) doping ions can be added during the epitaxial growth to form the first epitaxial layer 101. The second epitaxial layer 102 is, for example, an N-type lightly doped silicon carbide (SiC) epitaxial layer. The silicon carbide (SiC) epitaxial layer can be deposited on the first epitaxial layer 101 through another epitaxial growth process, and doping ions of a second conductivity type (e.g., N-type) are added during the epitaxial growth to form the second epitaxial layer 102. The doping concentration of the second epitaxial layer 102 is higher than the doping concentration of the first epitaxial layer 101. In some embodiments, the doping concentration of the first epitaxial layer 101 is, for example, about 1E14 to 1E16 atoms/cm ³ , and the doping concentration of the second epitaxial layer 102 is, for example, about 1E15 to 1E17 atoms/cm ³ , but is not limited thereto.

Still referring to FIG. 3 , then, in step S101, a patterned mask 141 is formed on the second epitaxial layer 102. In one embodiment, the patterned mask 141 is a hard mask, which is composed of, for example, silicon oxide, and can be formed by depositing a hard mask material layer on the second epitaxial layer 102 and patterning the hard mask material layer using lithography and etching processes to form the patterned mask 141. The patterned mask 141 includes a plurality of openings 142, which respectively expose a plurality of regions of the second epitaxial layer 102, and these openings 142 located on the inner region and the outer region of the second epitaxial layer 102 have different widths. In a first direction (e.g., X-axis direction), the widths of the openings 142 increase from the inside to the outside, wherein the openings 142 located on the inside region of the second epitaxial layer 102 have the smallest width, and the openings 142 located on the outside region of the second epitaxial layer 102 have the largest width. In step S101, an ion implantation process 140 is performed on the second epitaxial layer 102 through the openings 142 of the patterned mask 141, and doping ions of a second conductivity type (e.g., N-type) are implanted into the second epitaxial layer 102 to form a plurality of doping regions 151, 152, 153, 154, 155 of the second conductivity type (e.g., N-type). These doped regions 151 to 155 have the same doping concentration, and these doped regions 151 to 155 are laterally separated from each other in the second epitaxial layer 102, these doped regions 151 to 155 located in the inner region and the outer region of the second epitaxial layer 102 have different widths, and the distances between these doped regions 151 to 155 located in the inner region and the outer region of the second epitaxial layer 102 are different. In addition, the patterned mask 141 includes a plurality of shielding portions 143, and these shielding portions 143 located on the inner region and the outer region of the second epitaxial layer 102 have different widths. In a first direction, the widths of these shielding portions 143 decrease sequentially from the inner side to the outer side, wherein the shielding portion 143 located on the inner region of the second epitaxial layer 102 has the largest width, and the shielding portion 143 located on the outer region of the second epitaxial layer 102 has the smallest width. After the ion implantation process 140, the patterned mask 141 can be removed by a stripping process, for example, by an ashing process or by immersing in a solvent to strip the patterned mask 141 from the second epitaxial layer 102.

Next, referring to FIG. 4 , in step S103, a third epitaxial layer 106 is deposited on the second epitaxial layer 102 (as shown in FIG. 3 ) through an epitaxial growth process, and the third epitaxial layer 106 has a first conductivity type (e.g., P-type). In one embodiment, the third epitaxial layer 106 is, for example, a P-type silicon carbide (SiC) epitaxial layer, and doping ions of the first conductivity type (e.g., P-type) may be added during the epitaxial growth to form the third epitaxial layer 106. Since the epitaxial growth process for depositing the third epitaxial layer 106 is performed at a high temperature, for example, at a temperature of about 1600° C. to 1700° C., after the third epitaxial layer 106 is deposited, the doping ions of the doping regions 151 to 155 shown in FIG. 3 will diffuse to form a plurality of regions 105-1, 105-2, 105-3, 105-4, 105-5 and 105-6 of the current spreading layer 105 shown in FIG. 4 . Referring to FIG. 3 and FIG. 4 at the same time, since the plurality of openings 142 and the plurality of shielding portions 143 of the patterned mask 141 have different widths on the inner and outer regions of the second epitaxial layer 102, the plurality of doped regions 151 to 155 formed in the second epitaxial layer 102 also have different widths, and the doped regions 151 to 155 are laterally separated from each other. The distance is also different. After the third epitaxial layer 106 is deposited, the doping ions of these doping regions 151 to 155 diffuse in the second epitaxial layer 102, wherein a portion of the second epitaxial layer 102 corresponding to the maximum width directly below the shielding portion 143 will generate an inner region 105-1 with the lowest doping concentration in the current distribution layer 105. The lowest doping concentration in the inner region 105-1 is The doping concentration is substantially the same as that of the second epitaxial layer 102. In addition, the doping region 151 with a smaller width and a larger distance from other doping regions will produce a region 105-2 with the second lowest doping concentration, and the doping region 155 with the largest width and directly below the opening 142 with the largest width will produce an outer region 105-2 with the highest doping concentration in the current spreading layer 105. 6, another doping region 154 with a second largest width and a smaller distance from other doping regions will produce a region 105-5 with the second highest doping concentration, thereby forming multiple regions 105-1 to 105-6 with gradually changing doping concentrations as shown in FIG. 4 to form a current spreading layer 105, and the doping concentrations of these regions 105-1 to 105-6 increase gradually from the inside to the outside.

According to an embodiment of the present disclosure, the second epitaxial layer 102 is subjected to an ion implantation process 140 using the patterned mask 141 of FIG. 3, and then the epitaxial growth process temperature of the third epitaxial layer 106 is used to diffuse the doping ions of the multiple doping regions 151 to 155 in the second epitaxial layer 102, thereby forming a current spreading layer 105 having a laterally gradient doping concentration from the doping regions 151 to 155 and the second epitaxial layer 102, wherein the gradient doping concentration increases gradually from the inside to the outside along a first direction (e.g., the X-axis direction).

Next, referring to FIG. 5 , in step S105, a patterned mask 145 is formed on the third epitaxial layer 106. In one embodiment, the patterned mask 145 is a hard mask, and its composition is, for example, silicon oxide. The patterned mask 145 can be formed by deposition, lithography, and etching processes. The patterned mask 145 includes a plurality of openings, which respectively expose the predetermined formation areas of the source contact region. In step S105, an ion implantation process 150 is performed on the third epitaxial layer 106 through the openings of the patterned mask 145, and doping ions of the second conductivity type (e.g., N-type) are implanted into the third epitaxial layer 106 to form a source contact region 111. Afterwards, the patterned mask 145 is removed using a stripping process.

Continuing to refer to FIG. 5, in step S107, another patterned mask 161 is formed on the third epitaxial layer 106. In one embodiment, the patterned mask 161 is a hard mask, which is composed of, for example, silicon oxide, and can be formed by deposition, lithography, and etching processes. The patterned mask 161 includes a plurality of openings, which respectively expose predetermined formation areas of the substrate contact area. In step S107, an ion implantation process 160 is performed on the third epitaxial layer 106 through the opening of the patterned mask 161 to implant doping ions of the first conductive type (e.g., P-type) into the third epitaxial layer 106 to form a substrate contact region 113. In one embodiment, the substrate contact region 113 is adjacent to the source contact region 111. Thereafter, the patterned mask 161 is removed by a stripping process.

Next, referring to FIG. 6 , in step S109, a patterned mask 171 is formed to cover the source contact region 111 and the substrate contact region 113. In one embodiment, the patterned mask 171 is a hard mask, and its composition is, for example, silicon oxide, and the patterned mask 171 can be formed by deposition, lithography, and etching processes. The patterned mask 171 includes a plurality of openings, which respectively expose predetermined formation areas of the trench. In step S109, the third epitaxial layer 106 shown in FIG. 5 is etched through the openings of the patterned mask 171 to form the trench 120, and the third epitaxial layer 106 located on the side of the trench 120 can be called the well region 107. In one embodiment, the trench 120 passes through the third epitaxial layer 106 and extends downward into the current spreading layer 105, and the bottom surface of the trench 120 is located at a depth position of the inner region 105-1. According to some embodiments of the present disclosure, the bottom of the trench 120 is surrounded by the inner region 105-1 having the lowest doping concentration in the current spreading layer 105.

Next, referring to FIG. 7 , in step S111, the patterned mask 171 is still retained on the source contact region 111 and the substrate contact region 113, and a spacer material layer is sequentially deposited on the sidewall and bottom surface of the trench 120 and on the surface of the patterned mask 171, and then, the spacer material layer on the top surface of the patterned mask 171 and on a portion of the bottom surface of the trench 120 is removed by an etching process to form a spacer 181 on the sidewall of the trench 120 and expose a portion of the bottom surface of the trench 120. In one embodiment, the spacer 181 is composed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Next, in step S111, using the patterned mask 171 and the spacer 181 as masks, an ion implantation process 180 is performed on the inner region 105-1 of the current spreading layer 105 through the trench 120, and doping ions of the first conductivity type (e.g., P-type) are implanted into the inner region 105-1 to form a heavily doped region 115 having the first conductivity type (e.g., P-type) located directly below the trench 120. In one embodiment, the doping concentration of the heavily doped region 115 is, for example, 1E17 to 1E19 atoms/cm ³ , but not limited thereto. The doping concentration of the heavily doped region 115 may be reduced to 1E16 to 1E18 atoms/cm ³ to reduce the resistance of the JFET effect between the bottom corner of the trench 120 and the well region 107 . According to some embodiments of the present disclosure, the width of the heavily doped region 115 can be controlled by adjusting the thickness of the spacer 181. When the thickness of the spacer 181 is larger, the width of the heavily doped region 115 is smaller, and in the first direction (X-axis direction), the width of the heavily doped region 115 is smaller than the width of the trench 120. In addition, the inner region 105-1 with the lowest doping concentration in the current spreading layer 105 surrounds the bottom corner of the trench 120 and the heavily doped region 115.

Then, referring to FIG. 8, in step S113, a stripping process is used to remove the patterned mask 171 and the spacer 181 to expose the source contact region 111, the substrate contact region 113, the sidewalls and bottom surface of the trench 120, and the heavily doped region 115. In one embodiment, when the patterned mask 171 and the spacer 181 have the same composition, such as silicon oxide, the patterned mask 171 and the spacer 181 can be removed simultaneously by the same stripping process. Afterwards, an annealing process can be performed to activate the doping ions in the source contact region 111, the substrate contact region 113, and the heavily doped region 115.

Still referring to FIG. 8 , then, in step S115, a material layer of a gate dielectric layer 117 is deposited longitudinally on the surface of the source contact region 111 and the body contact region 113, and on the sidewall and bottom surface of the trench 120. In one embodiment, the composition of the gate dielectric layer 117 is, for example, silicon oxide. Thereafter, a material layer of a gate electrode 119 is deposited on the material layer of the gate dielectric layer 117, which covers the source contact region 111 and the body contact region 113, and fills the trench 120. In one embodiment, the composition of the gate electrode 119 is, for example, polysilicon. Then, in one embodiment, an etching process can be used to remove the material layer of the gate electrode 119 covering the source contact region 111 and the body contact region 113, and the top surface of the gate electrode 119 formed in the trench 120 is substantially at the same level as the top surfaces of the source contact region 111 and the body contact region 113. In another embodiment, a chemical mechanical planarization process can also be used to remove the material layer of the gate electrode 119 covering the source contact region 111 and the body contact region 113, leaving the gate dielectric layer 117 and the gate electrode 119 in the trench 120, so that the top surface of the gate dielectric layer 117 and the top surface of the gate electrode 119 are substantially flush with the top surface of the source contact region 111 and the body contact region 113.

Next, referring to FIG. 9, in step S117, an interlayer dielectric layer 122 is deposited on the source contact region 111, the substrate contact region 113, the gate dielectric layer 117, and the gate electrode 119, and a plurality of contact openings 121 are formed in the interlayer dielectric layer 122 by photolithography and etching processes, each of which can expose a portion of the source contact region 111 and a portion of the substrate contact region 113. In some embodiments, the interlayer dielectric layer 122 is composed of, for example, silicon oxide or other suitable low-k dielectric materials. In one embodiment, when the material layer of the gate dielectric layer 117 remains on the surface of the source contact region 111 and the substrate contact region 113, the etching process for forming the contact opening 121 will also remove the material layer of the gate dielectric layer 117 located in the predetermined formation area of the contact opening 121.

Next, referring to FIG. 10 , in step S119, a barrier layer 123 is first deposited longitudinally on the sidewalls and bottom surface of the contact opening 121, and then a conductive material is filled in the contact opening 121 by a deposition and etching back process to form a via hole 124. Thereafter, a metal wiring layer including a source electrode 126 is formed on the interlayer dielectric layer 122 by a deposition, lithography and etching process, wherein the source electrode 126 is electrically coupled to the source contact region 111 and the substrate contact region 113 via the via hole 124. In addition, in step S119, other vias and metal wires may be formed to be electrically coupled to the heavily doped region 115, so that the heavily doped region 115 is electrically coupled to the source electrode 126 or the ground terminal, so that the heavily doped region 115 can further provide a better electric field shielding effect. In some embodiments, the barrier layer 123 is composed of, for example, tungsten (Ta), tungsten nitride (TaN), titanium (Ti), titanium nitride (TiN) or other suitable diffusion barrier materials, the via 124 is composed of, for example, tungsten (W), aluminum (Al), copper (Cu), aluminum copper (AlCu) or other suitable conductive materials, and the source electrode 126 is composed of, for example, aluminum copper (AlCu), aluminum (Al), copper (Cu) or other suitable conductive metal materials. In addition, when the size of the via 124 is small, for example, less than 0.6 micrometers (μm), tungsten (W) can be used to form the via 124. When the size of the via hole 124 is relatively large, for example, greater than 0.6 micrometers (μm), aluminum copper (AlCu) can be used to simultaneously form the via hole 124 and the source electrode 126. Afterwards, a deposition process is used to form the drain electrode 128 on the bottom surface of the drain contact region 103 located on the second surface 110B of the substrate 110 to complete the semiconductor device 100 shown in FIG. 1.

According to some embodiments of the present disclosure, a semiconductor device includes a heavily doped region located directly below a trench and having a width smaller than the trench width, and a current spreading layer surrounding the bottom corner of the trench and the heavily doped region and having a laterally gradient doping concentration. By combining the heavily doped region with a smaller width and the inner region with the lowest doping concentration in the current spreading layer, the resistance of the junction field effect transistor (JFET) effect between the bottom corner of the trench and the well region can be reduced, and the electric field at the bottom of the trench gate can be effectively reduced, thereby improving the breakdown voltage and reliability of the semiconductor device. In addition, those areas with higher doping concentration in the current spreading layer can achieve the effect of spreading the current to reduce the on-resistance (Ron) of the semiconductor device.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:Semiconductor devices

101: First epitaxial layer

103: Drain contact area

105: Current dispersion layer

105-1: Inner area

105-2, 105-3, 105-4, 105-5: Area

105-6: Outer area

107: Well area

110: Base

110A: First surface

110B: Second surface

111: Source contact area

113: substrate contact area

115:Heavy mixing area

117: Gate dielectric layer

119: Gate electrode

120: Groove

122: Interlayer dielectric layer

123: Barrier layer

124: Conductive hole

126: Source electrode

128: Drain electrode

Claims (18)

A semiconductor device comprises: a substrate having a first surface and a second surface; a trench disposed in the substrate; a gate electrode disposed in the trench; a source contact region disposed on the first surface of the substrate; a drain contact region disposed on the second surface of the substrate; a heavily doped region having a first conductivity type disposed directly below the trench; In a first direction, a width of the heavily doped region is smaller than a width of the trench; and a current spreading layer having a second conductivity type is disposed in the substrate and surrounds the bottom of the trench and the heavily doped region, the current spreading layer having a gradient doping concentration, and along the first direction, the gradient doping concentration increases gradually from the heavily doped region to the outside. A semiconductor device as described in claim 1, wherein the current spreading layer includes an inner region directly contacting the heavily doped region and the bottom corner of the trench, and the inner region has a minimum doping concentration in the current spreading layer. A semiconductor device as described in claim 2, wherein the substrate includes an epitaxial layer having the second conductivity type, located between the drain contact region and the current spreading layer, and the minimum doping concentration of the inner region is lower than a doping concentration of the epitaxial layer. A semiconductor device as described in claim 3, wherein the current spreading layer includes an outer region having a maximum doping concentration in the current spreading layer, and the maximum doping concentration of the outer region is higher than the doping concentration of the epitaxial layer. The semiconductor device as described in claim 2 further includes a gate dielectric layer disposed longitudinally on the sidewalls and bottom surface of the trench, surrounding the gate electrode, and the gate dielectric layer is located between the inner region and the gate electrode. A semiconductor device as claimed in claim 1, wherein in the first direction, the width of the heavily doped region is smaller than a width of the gate electrode. The semiconductor device as described in claim 1 further includes: a well region having the first conductivity type, disposed in the substrate and adjacent to the side of the trench; a substrate contact region having the first conductivity type, disposed in the well region and adjacent to the source contact region; and a source electrode electrically coupled to the source contact region and the substrate contact region. The semiconductor device as described in claim 1 further includes another trench disposed in the substrate, and another gate electrode disposed in the other trench, wherein there is a distance between the trench and the adjacent other trench, and the width of the heavily doped region decreases as the distance decreases. A method for manufacturing a semiconductor device includes: providing a wafer, comprising a drain contact region, a first epitaxial layer and a second epitaxial layer, stacked in sequence from bottom to top; forming a patterned mask on the second epitaxial layer, the patterned mask comprising a plurality of openings, wherein the plurality of widths of the plurality of openings increase in sequence from the inside to the outside in a first direction; performing an ion implantation process on the second epitaxial layer through the plurality of openings of the patterned mask to form a plurality of doped regions; depositing a third epitaxial layer on the second epitaxial layer; The plurality of doped regions and the second epitaxial layer form a current spreading layer, the current spreading layer having a gradient doping concentration, and the gradient doping concentration increases from the inside to the outside along the first direction; a source contact region is formed in the third epitaxial layer; a trench is formed, passing through the third epitaxial layer and reaching the current spreading layer; a heavily doped region is formed directly below the trench, and in the first direction, a width of the heavily doped region is smaller than a width of the trench; and a gate electrode is formed in the trench. A method for manufacturing a semiconductor device as described in claim 9, wherein the heavily doped region has a first conductivity type, the first epitaxial layer, the second epitaxial layer and the plurality of doped regions all have a second conductivity type, and the doping concentration of the second epitaxial layer is higher than the doping concentration of the first epitaxial layer. A method for manufacturing a semiconductor device as described in claim 9, wherein before depositing the third epitaxial layer, the plurality of doped regions are laterally separated from each other in the second epitaxial layer, and the plurality of doped regions have the same doping concentration, and after depositing the third epitaxial layer, the doping ions in the plurality of doped regions diffuse to form the gradient doping concentration of the current spreading layer. A method for manufacturing a semiconductor device as described in claim 9, wherein the patterned mask includes a plurality of shielding portions, and in the first direction, the plurality of widths of the plurality of shielding portions decrease sequentially from the inside to the outside, and an inner region having a minimum doping concentration in the current spreading layer is formed directly below the shielding portion having a maximum width. A method for manufacturing a semiconductor device as described in claim 12, wherein the minimum doping concentration of the inner region of the current spreading layer is the same as the doping concentration of the second epitaxial layer. A method for manufacturing a semiconductor device as described in claim 12, wherein the inner region having the lowest doping concentration surrounds the bottom corner of the trench and the heavily doped region. A method for manufacturing a semiconductor device as described in claim 9, wherein an outer region having a highest doping concentration in the current spreading layer is formed directly below the opening having a maximum width. The method for manufacturing a semiconductor device as described in claim 9, wherein forming the heavily doped region comprises: forming a spacer on the sidewall of the trench and exposing a portion of the bottom surface of the trench; and performing an ion implantation process on the current spreading layer through the exposed portion of the bottom surface of the trench to form the heavily doped region. The method for manufacturing a semiconductor device as described in claim 16 further includes: after forming the heavily doped region, removing the spacer; and after removing the spacer, forming a gate dielectric layer longitudinally on the sidewalls and bottom surface of the trench, wherein the gate electrode is formed on the gate dielectric layer. The method for manufacturing a semiconductor device as described in claim 9 further includes: forming a body contact region in the third epitaxial layer and adjacent to the source contact region; and forming a source electrode electrically coupled to the source contact region and the body contact region.

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