TWI841221B - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The gate structure includes an upper gate electrode, a capping layer on the upper gate electrode and a first dielectric layer partially disposed between the upper gate electrode and the capping layer.

Description

Semiconductor components

This application claims priority to U.S. Patent Application Nos. 17/844,961 and 17/845,871 (i.e., priority date is June 21, 2022), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device, and more particularly to a buried gate structure having a dielectric layer between an electrode and a capping layer.

A buried gate structure of a semiconductor device includes a gate dielectric layer and a gate electrode in a trench. The gate dielectric layer covers the surface of the trench, and the gate electrode partially fills the trench on the gate dielectric layer. The buried gate structure may be adjacent to (or at the same level as) an impurity region or a junction region in an active region of the semiconductor device.

Gate induced drain leakage (GIDL) may increase where the gate electrode and the impurity region overlap. GIDL releases the stored charge, thereby reducing the operating reliability of the semiconductor device. In addition, a portion of the buried gate structure of the semiconductor device may be disposed in an isolation region of the semiconductor device, which is called a passing gate. The passing gate may exacerbate the occurrence of GIDL.

The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present case.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a trench and a gate structure located in the trench. The gate structure includes a higher gate electrode, a capping layer located on the higher gate electrode, and a first dielectric layer partially disposed between the higher gate electrode and the capping layer.

Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a trench and a gate structure located in the trench. The gate structure includes a higher gate electrode and a capping layer located on the higher gate electrode. A distance between the capping layer and the substrate is greater than a distance between the higher gate electrode and the substrate.

Another aspect of the present disclosure provides a method for preparing a semiconductor device. The method includes forming a trench in a substrate and disposing a higher gate electrode in the trench. The method also includes disposing a first dielectric layer on the higher gate electrode in the trench and disposing a capping layer on the first dielectric layer in the trench.

Forming a thicker dielectric layer in the trench can reduce the effective electric field and thus reduce GIDL. Therefore, interference between word lines in different memory cells can be avoided. Data retention time can be extended and the operational reliability of semiconductor devices can be improved.

In addition, the gate structure also includes a lower gate electrode and a dielectric layer between the lower gate electrode and the substrate. The dielectric layer between the lower gate electrode and the substrate can have a constant thickness, which helps to optimize the subthreshold swing and reduce the threshold voltage. Therefore, the channel ions can be increased. For example, the number, amount, density, or flow of electrons between the doped regions can be increased. For example, assuming that the external resistance and the internal trap charge (or internal trap density) are constant, the channel ions can be increased by 20%, 40%, 60%, or more.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

Specific language will now be used to describe the embodiments or examples of the present disclosure shown in the drawings. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the embodiments, and any further application of the principles described herein, are considered to be within the scope of the present disclosure by one of ordinary skill in the art. The present disclosure may repeat reference symbols in different embodiments, but even if they share the same reference symbol, it does not necessarily mean that components of one embodiment are applicable to another embodiment.

It should be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the concept of this disclosure, the first element, component, region, layer, or part discussed below can be referred to as the second element, component, region, layer, or part.

The terms used herein are for the purpose of describing specific exemplary embodiments only and are not intended to limit the concepts of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a/an" and "the" also include the plural forms. It should be understood that the terms "comprises" and "comprising" used in this specification indicate the presence of the components, integers, steps, operations, elements, or components described, but do not exclude the presence or addition of one or more other components, integers, steps, operations, elements, components, or combinations thereof.

FIG. 1A is a schematic plan view of a semiconductor device 1 according to some embodiments of the present disclosure.

In some embodiments, the semiconductor device 1 may be disposed adjacent to a circuit. For example, the semiconductor device 1 may be disposed adjacent to a memory device such as a dynamic random access memory (DRAM) device.

1A , a semiconductor device 1 may include a plurality of active regions 10 a and an isolation region 10 i (or an isolation layer) formed on a substrate 10. The active region 10 a may be defined by the isolation region 10 i.

The semiconductor device 1 may also include a plurality of gate structures, such as gate structures 11, 12, 13, and 14. Each active region 10a may span two gate structures and may be divided into three doped regions by the two gate structures. For example, the active region 10a may be divided into a first doped region 101 disposed between the two gate structures 12 and 13 and a second doped region 102 located on both sides of the first doped region 101.

Each gate structure 11, 12, 13, and 14 may have a linear shape extending in any direction. Each gate structure 11, 12, 13, and 14 may be a buried gate buried in a trench passing through the active region 10a and the isolation region 10i. Each gate structure 11, 12, 13, and 14 may include one or more main gate portions (or main gates) buried in the active region 10a and one or more transmission gate portions (or transmission gates) buried in the isolation region 10i. For example, FIG1B (described further below) shows a transmission gate of gate structure 11, a main gate of gate structure 12, a main gate of gate structure 13, and a transmission gate of gate structure 14. FIG1C (described further below) shows a trench 10t2 (in which gate structure 12 is disposed) passing through one of the active region 10a and the isolation region 10i. A portion of the gate structure 12 above the active region 10a is the main gate.

As used herein, the term “main gate” refers to a gate configured to receive a voltage to address a memory cell, and the term “transfer gate” refers to a gate configured to receive a voltage to address an adjacent memory cell.

For example, gate structure 11 may be a transmission gate in one memory cell as shown in FIG1B , but become a primary gate in another memory cell. In some embodiments, gate structure 12 may be a primary gate in one memory cell as shown in FIG1B , but become a transmission gate in yet another memory cell.

Although both the main gate and the transfer gate are described above as parts or portions of the gate structure, the main gate and the transfer gate have different structures. For example, as shown in FIG. 1B , the trench 10t1 for the transfer gate portion of the gate structure 11 and the trench 10t2 for the main gate portion of the gate structure 12 have different depths. The trench 10t1 may be deeper than the trench 10t2.

FIG1B is a schematic cross-sectional view of the semiconductor device taken along line A-A' shown in FIG1A.

1B , the semiconductor device 1 may include a substrate 10 , and gate structures 11 , 12 , 13 , and 14 formed in the substrate 10 .

The substrate 10 may include a semiconductor substrate. In some embodiments, the substrate 10 may include, for example, silicon (Si), single crystal silicon, polycrystalline silicon, amorphous silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials. In some other embodiments, the substrate 10 may include a layered semiconductor, such as silicon/silicon germanium, silicon-on-insulator, or silicon germanium-on-insulator.

The active region 10a and the isolation region 10i may be formed in the substrate 10. The active region 10a may be defined by the isolation region 10i. In some embodiments, the isolation region 10i may include a shallow trench isolation (STI) structure. The STI structure may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (N ₂ OSi ₂ ), silicon nitride oxide (N ₂ OSi ₂ ), etc.

The first doped region 101 and the second doped region 102 may be formed in the active region 10a. In some embodiments, the first doped region 101 and the second doped region 102 may be disposed on or near the top surface of the active region 10a. The first doped region 101 and the second doped region 102 may be located on both sides of the trench 10t2.

The channel region CH may be formed between the first doped region 101 and the second doped region 102. The channel region CH may be located below the gate structure 12 and/or the gate structure 13.

In some embodiments, the first doped region 101 and the second doped region 102 may be doped with an N-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb). In some other embodiments, the first doped region 101 and the second doped region 102 may be doped with a P-type dopant such as boron (B) or indium (In). In some embodiments, the first doped region 101 and the second doped region 102 may be doped with dopants or impurity ions having the same conductivity type. In some embodiments, the first doped region 101 and the second doped region 102 may be doped with dopants or impurity ions having different conductivity types.

The bottom surfaces of the first doped region 101 and the second doped region 102 may be located at a predetermined depth from the top surface of the active region 10a. The first doped region 101 and the second doped region 102 may contact the sidewall of the trench 10t2. The bottom surfaces of the first doped region 101 and the second doped region 102 may be higher than the bottom surface of the trench 10t2. Similarly, the bottom surfaces of the first doped region 101 and the second doped region 102 may be higher than the bottom surface of the trench 10t1.

In some embodiments, the first doped region 101 and the second doped region 102 may be referred to as source/drain regions. In some embodiments, the first doped region 101 may include a bit line contact region and may be electrically connected to a bit line structure (such as the bit line structure 32 shown in FIG. 3 ). The second doped region 102 may include a storage node junction region and may be electrically connected to a memory element (such as the memory element 34 shown in FIG. 3 ).

The trench 10t1 in the isolation region 10i and the trench 10t2 in the active region 10a are spaces in which gate structures 11 and 12 may be formed. The gate structure 11 in the isolation region 10i may include a transfer gate. The gate structure 12 in the active region 10a may include a main gate.

The trench 10t2 may have a shallower depth than the trench 10t1. The bottoms of the trenches 10t1 and 10t2 may each have a curvature as shown in the embodiment of FIG. 1B. However, in some other embodiments, the bottoms of the trenches 10t1 and 10t2 may be flat or may have other shapes.

The gate structure 12 may include dielectric layers 12d1, 12d2, 12d3, gate electrodes 12e1, 12e2, and a capping layer 12c.

The dielectric layer 12d1 may be conformally formed on the bottom surface and sidewalls of the trench 10t2. The dielectric layer 12d1 may surround or cover a portion of the gate electrode 12e1. The dielectric layer 12d1 may separate the gate electrode 12e1 from the substrate 10.

A portion (eg, a sidewall or an extension) of the dielectric layer 12d1 may be disposed between the gate electrode 12e2 and the substrate 10. A portion (eg, a bottom or a base) of the dielectric layer 12d1 may be disposed between the gate electrode 12e1 and the substrate 10.

In some embodiments, the thickness t1 of the dielectric layer 12d1 may range from about 4.0 nanometers (nm) to about 6.0 nm.

In some embodiments, the dielectric layer 12d1 may have a constant thickness. For example, the thickness of the sidewall (or extension) of the dielectric layer 12d1 between the gate electrode 12e2 and the substrate 10 and the thickness of the bottom (or base) of the dielectric layer 12d1 between the gate electrode 12e1 and the substrate 10 may be substantially equal.

In some embodiments, the thickness of the sidewall (or extension) of the dielectric layer 12d1 between the gate electrode 12e2 and the substrate 10 and the thickness of the bottom (or base) of the dielectric layer 12d1 between the gate electrode 12e1 and the substrate 10 may both be approximately 4.0 nm, 5.0 nm, or 6.0 nm.

In some embodiments, the dielectric layer 12d1 may have different thicknesses. For example, the thickness of the sidewall (or extension) of the dielectric layer 12d1 between the gate electrode 12e2 and the substrate 10 may be greater than the thickness of the bottom (or base) of the dielectric layer 12d1 between the gate electrode 12e1 and the substrate 10. For example, the thickness of the sidewall (or extension) of the dielectric layer 12d1 between the gate electrode 12e2 and the substrate 10 may be less than the thickness of the bottom (or base) of the dielectric layer 12d1 between the gate electrode 12e1 and the substrate 10.

In some embodiments, the dielectric layer 12d1 may include _, for example, silicon oxide ( _SiO2 ), silicon nitride _{(Si3N4 )} , silicon oxynitride ( _N2OSi2 ), silicon nitride oxide ( _N2OSi2 ), a high-k material, or a combination thereof. Examples of high-k materials include dielectric materials having a higher dielectric constant than silicon _dioxide ( _SiO2 ), or dielectric materials having a dielectric constant higher than about 3.9. In some embodiments, the dielectric layer 12d1 may include at least one metal element, such as _HfO2 , HSO, _{La2O3 , LaAlO3} , _ZrO2 , _{ZrSiO4 , Al2O3} , or a combination thereof.

The dielectric layer 12d2 may be disposed on the gate electrode 12e1. The dielectric layer 12d2 may be partially disposed between the gate electrodes 12e1 and 12e2. For example, the dielectric layer 12d2 may have a base portion located between the gate electrodes 12e1 and 12e2 and an extension portion extending from the base portion to the top surface of the active region 10a.

In some embodiments, the thickness t2 of the dielectric layer 12d2 may range from about 1.5 nm to about 3.0 nm. In some embodiments, the thickness t2 of the dielectric layer 12d2 may be less than the thickness t1 of the dielectric layer 12d1.

In some embodiments, the dielectric layer 12d2 may have a constant thickness. For example, the thickness of the extension portion of the dielectric layer 12d2 and the thickness of the base portion of the dielectric layer 12d2 may be substantially equal.

In some embodiments, the thickness of the extension of dielectric layer 12d2 and the thickness of the base of dielectric layer 12d2 can both be approximately 1.5 nm, 3.0 nm, or other amounts between 1.5 nm and 3.0 nm.

In some embodiments, the dielectric layer 12d2 may have different thicknesses. For example, the thickness of the extension of the dielectric layer 12d2 may be greater than the thickness of the base of the dielectric layer 12d2. For example, the thickness of the extension of the dielectric layer 12d2 may be less than the thickness of the base of the dielectric layer 12d2.

The base of the dielectric layer 12d2 may directly contact the gate electrodes 12e1 and 12e2. The base of the dielectric layer 12d2 may be sandwiched between the gate electrodes 12e1 and 12e2. The base of the dielectric layer 12d2 may be covered or embedded by the gate electrodes 12e1 and 12e2.

The extension of the dielectric layer 12d2 may cover or contact a portion of the dielectric layer 12d1.

The extension of the dielectric layer 12d2 may be disposed between the gate electrode 12e2 and the dielectric layer 12d1 and between the dielectric layer 12d3 and the dielectric layer 12d1. The extension of the dielectric layer 12d2 may be separated from the substrate 10 through the dielectric layer 12d1. The extension of the dielectric layer 12d2 may be separated from the capping layer 12c through the dielectric layer 12d3.

The dielectric layer 12d2 may surround or cover a portion of the gate electrode 12e2. The dielectric layer 12d1 and the extension of the dielectric layer 12d2 may separate the gate electrode 12e2 from the substrate 10. Therefore, the distance between the gate electrode 12e2 and the substrate 10 (i.e., thickness t2 and thickness t1) may be greater than the distance between the gate electrode 12e1 and the substrate 10 (i.e., thickness t1). For example, the gate electrode 12e2 and the gate electrode 12e1 may be separated from the substrate 10 by different distances.

The dielectric layer 12d3 may be disposed on the gate electrode 12e2. The dielectric layer 12d3 may be partially disposed between the gate electrode 12e2 and the cover layer 12c. For example, the dielectric layer 12d3 may have a base portion located between the gate electrode 12e2 and the cover layer 12c and an extension portion extending from the base portion to the top surface of the active region 10a.

In some embodiments, the thickness t3 of the dielectric layer 12d3 may range from about 1.5 nm to about 3.0 nm. In some embodiments, the thickness t3 of the dielectric layer 12d3 may be less than the thickness t1 of the dielectric layer 12d1.

In some embodiments, the dielectric layer 12d3 may have a constant thickness. For example, the thickness of the extension portion of the dielectric layer 12d3 and the thickness of the base portion of the dielectric layer 12d3 may be substantially equal.

In some embodiments, the thickness of the extension of dielectric layer 12d3 and the thickness of the base of dielectric layer 12d3 can both be approximately 1.5 nm, 3.0 nm, or other amounts between 1.5 nm and 3.0 nm.

In some embodiments, the dielectric layer 12d3 may have different thicknesses. For example, the thickness of the extension of the dielectric layer 12d3 may be greater than the thickness of the base of the dielectric layer 12d3. For example, the thickness of the extension of the dielectric layer 12d3 may be less than the thickness of the base of the dielectric layer 12d3.

In some embodiments, the thickness t3 of the dielectric layer 12d3 and the thickness t2 of the dielectric layer 12d2 may be substantially equal. For example, the thickness t3 of the dielectric layer 12d3 and the thickness t2 of the dielectric layer 12d2 may both be approximately 1.5 nm, 3.0 nm, or other amounts between 1.5 nm and 3.0 nm.

For example, the thickness of the extension of the dielectric layer 12d3 and the thickness of the extension of the dielectric layer 12d2 may be substantially equal. For example, the thickness of the base of the dielectric layer 12d3 and the thickness of the base of the dielectric layer 12d2 may be substantially equal.

The base of the dielectric layer 12d3 may directly contact the gate electrode 12e2 and the capping layer 12c. The base of the dielectric layer 12d3 may be sandwiched between the gate electrode 12e2 and the capping layer 12c. The base of the dielectric layer 12d3 may be covered or buried by the gate electrode 12e2 and the capping layer 12c.

The extension of the dielectric layer 12d3 may cover or contact a portion of the dielectric layer 12d2.

The extension portion of the dielectric layer 12d3 may be disposed between the cover layer 12c and the dielectric layer 12d2. The extension portion of the dielectric layer 12d3 may be separated from the dielectric layer 12d1 by the dielectric layer 12d2.

The dielectric layer 12d3 may surround or cover a portion of the cover layer 12c.

The dielectric layer 12d1, the dielectric layer 12d2, and the dielectric layer 12d3 may separate the capping layer 12c from the substrate 10. Therefore, the distance between the capping layer 12c and the substrate 10 (i.e., thickness t3, thickness t2, and thickness t1) may be greater than the distance between the gate electrode 12e1 and the substrate 10 (i.e., thickness t1). Therefore, the distance between the capping layer 12c and the substrate 10 (i.e., thickness t3, thickness t2, and thickness t1) may be greater than the distance between the gate electrode 12e2 and the substrate 10 (i.e., thickness t2 and thickness t1). For example, the gate electrode 12e2, the gate electrode 12e1, and the capping layer 12c may be spaced apart from the substrate 10 at different distances.

Any two of the surface of the dielectric layer 12d1, the surface of the extension of the dielectric layer 12d2, the surface of the extension of the dielectric layer 12d3, the surface of the cover layer 12c, and the top surface of the active region 10a may be substantially coplanar.

The material constituting the dielectric layer 12d2 may be the same as or different from the material constituting the dielectric layer 12d1. Similarly, the material constituting the dielectric layer 12d3 may be the same as or different from the material constituting the dielectric layer 12d1.

In some embodiments, dielectric layer 12d2 and dielectric layer 12d1 may have the same material formed by different operations. Similarly, dielectric layer 12d3 and dielectric layer 12d1 may have the same material formed by different operations.

For example, the manufacturing technology of the dielectric layer 12d1 may include a thermal oxidation operation. The manufacturing technology of the dielectric layer 12d2 may include an atomic layer deposition (ALD) process. The manufacturing technology of the dielectric layer 12d3 may include an ALD process.

In some embodiments, dielectric layer 12d1 and dielectric layer 12d2 may have different densities, such as different particle densities. For example, the density of dielectric layer 12d1 may be lower than the density of dielectric layer 12d2. The density of dielectric layer 12d2 may be higher than the density of dielectric layer 12d1. For example, dielectric layer 12d2 may be denser than dielectric layer 12d1.

In some embodiments, dielectric layer 12d1 and dielectric layer 12d3 may have different densities, such as different particle densities. For example, the density of dielectric layer 12d1 may be lower than the density of dielectric layer 12d3. The density of dielectric layer 12d3 may be higher than the density of dielectric layer 12d1. For example, dielectric layer 12d3 may be denser than dielectric layer 12d1. In some embodiments, dielectric layer 12d2 and dielectric layer 12d3 may have the same density.

The gate electrode 12e1 may be disposed on the dielectric layer 12d1 and separated from the substrate 10 by the dielectric layer 12d1. The gate electrode 12e1 may be separated from the substrate 10 by a distance (ie, thickness t1). In some embodiments, the distance between the gate electrode 12e1 and the substrate 10 may range from about 4.0 nm to about 6.0 nm.

The gate electrode 12e1 may be surrounded or covered by the dielectric layer 12d1 and the dielectric layer 12d2. The gate electrode 12e1 may also be referred to as a lower gate electrode relative to the gate electrode 12e2.

In some embodiments, the gate electrode 12e1 may include a single layer of metal, a metal composite, or a conductive material layer. In some embodiments, the gate electrode 12e1 may include a metal-based material. For example, the gate electrode 12e1 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), a stack of the foregoing, or a combination of the foregoing.

The gate electrode 12e2 may be disposed on the dielectric layer 12d2 and separated from the gate electrode 12e1 by the dielectric layer 12d2. The gate electrode 12e2 may be separated from the substrate 10 by the dielectric layer 12d1 and the dielectric layer 12d2. The gate electrode 12e2 may be separated from the substrate 10 by a distance (i.e., thickness t1 and thickness t2). In some embodiments, the distance between the gate electrode 12e2 and the substrate 10 may range from about 5.5 nm to about 9.0 nm, such as about 7.0 nm or about 7.5 nm.

The gate electrode 12e2 may be spaced apart from the second doped region 102 by a distance (ie, thickness t1 and thickness t2). The gate electrode 12e2 may be spaced apart from the first doped region 101 by a distance (ie, thickness t1 and thickness t2).

The gate electrode 12e2 may be surrounded or covered by the dielectric layer 12d2 and the dielectric layer 12d3. The gate electrode 12e2 may also be referred to as a higher gate electrode relative to the gate electrode 12e1.

In some embodiments, the gate electrode 12e2 may include a single layer of metal, a metal composite, or a conductive material layer. In some embodiments, the gate electrode 12e2 may include polycrystalline silicon (poly-Si), titanium nitride (TiN), tungsten nitride (WN), or similar materials.

In some embodiments, the width w1 of the gate electrode 12e1 may be greater than the width w2 of the gate electrode 12e2.

In some embodiments, the gate electrodes 12e1 and 12e2 can be used as word lines. For example, the gate electrodes 12e1 and 12e2 can be used with a bit line (such as the bit line structure 32 shown in FIG. 3) to address a memory cell. For example, the gate electrode 12e2 can be used as a gate electrode of a transistor in a memory cell. The second doped region 102 and the first doped region 101 can serve as a drain region and a source region of the transistor. The second doped region 102 can be coupled to a capacitor or a memory element (such as the memory element 34 shown in FIG. 3) and the first doped region 101 can be coupled to a bit line (such as the bit line structure 32 shown in FIG. 3). The transistor can retain charge in the capacitor.

In some embodiments, the gate electrode 12e2 may have a low work function. In some embodiments, the gate electrode 12e1 may have a high work function. A high work function refers to a work function higher than the mid-gap work function of silicon. A low work function refers to a work function lower than the mid-gap work function of silicon. Specifically, the high work function may be higher than 4.5 eV, and the low work function may be lower than 4.5 eV.

In some embodiments, the gate electrodes 12e1 and 12e2 may be configured to receive different voltages. In some embodiments, the voltage applied to the gate electrode 12e1 may be greater than the voltage applied to the gate electrode 12e2. In some embodiments, the voltage difference between the gate electrodes 12e1 and 12e2 may be greater than 0.3 volts (V). In some embodiments, the gate electrodes 12e1 and 12e2 may be configured to address different memory cells.

The capping layer 12c may be disposed on the dielectric layer 12d3 and separated from the gate electrode 12e2 by the dielectric layer 12d3. The capping layer 12c may be separated from the substrate 10 by the dielectric layer 12d1, the dielectric layer 12d2, and the dielectric layer 12d3. The capping layer 12c may be separated from the substrate 10 by a distance (i.e., thickness t1, thickness t2, and thickness t3). In some embodiments, the distance between the capping layer 12c and the substrate 10 may range from about 7.0 nm to about 12.0 nm, such as about 10.0 nm or about 9.0 nm.

The cover layer 12c may be surrounded or covered by the dielectric layer 12d3. The cover layer 12c may contact an extension of the dielectric layer 12d3. The cover layer 12c may be separated from the dielectric layer 12d2 by the dielectric layer 12d3. The cover layer 12c may be used to protect the gate electrode 12e2. The cover layer 12c may have a surface substantially coplanar with the top surface of the active region 10a.

In some embodiments, the width w1 of the gate electrode 12e1 may be greater than the width w3 of the capping layer 12c. In some embodiments, the width w2 of the gate electrode 12e2 may be greater than the width w3 of the capping layer 12c. In other words, the width w3 of the capping layer 12c may be smaller than the width w2 of the gate electrode 12e2. The width w3 of the capping layer 12c may be smaller than the width w1 of the gate electrode 12e1.

In some embodiments, the capping layer 12c may include a dielectric material such as silicon oxide ( _SiO2 ), silicon _nitride ( _Si3N4 ), silicon oxynitride ( _N2OSi2 ), and silicon nitride oxide ( _N2OSi2 ). In some embodiments, the capping layer 12c may _include a silicon nitride liner and a spin-on-dielectric ( _SOD ) material.

The gate structure 11 may include dielectric layers 11d1, 11d2, 11d3, gate electrodes 11e1, 11e2, and a capping layer 11c. The structure of the gate structure 11 is similar to that of the gate structure 12, except that the gate structure 11 is disposed in the isolation region 10i.

Fig. 1C illustrates a schematic cross-sectional view of the semiconductor device along the line A-A' shown in Fig. 1A. The structure of Fig. 1C is similar to the structure of Fig. 1B except for the following differences.

In some embodiments, the thickness t3 of the dielectric layer 12d3 may be greater than the thickness t2 of the dielectric layer 12d2. For example, the thickness t3 of the dielectric layer 12d3 may be substantially twice the thickness t2 of the dielectric layer 12d2. For example, the thickness t3 of the dielectric layer 12d3 may be approximately 3.0 nm, while the thickness t2 of the dielectric layer 12d2 may be approximately 1.5 nm.

In some embodiments, the capping layer 12c may be spaced apart from the substrate 10 by a distance ranging from about 8.5 nm to about 10.5 nm.

Fig. 1D illustrates a schematic cross-sectional view of the semiconductor device along the line A-A' shown in Fig. 1A. The structure of Fig. 1D is similar to the structure of Fig. 1B, except for the following differences.

In some embodiments, the thickness t2 of the dielectric layer 12d2 may be greater than the thickness t3 of the dielectric layer 12d3. For example, the thickness t2 of the dielectric layer 12d2 may be substantially twice the thickness t3 of the dielectric layer 12d3. For example, the thickness t2 of the dielectric layer 12d2 may be approximately 3.0 nm, and the thickness t3 of the dielectric layer 12d3 may be approximately 1.5 nm.

In some embodiments, the capping layer 12c may be spaced apart from the substrate 10 by a distance ranging from about 8.5 nm to about 10.5 nm.

FIG. 1E is a schematic cross-sectional view of the semiconductor device taken along line B-B' shown in FIG. 1A.

1E, the trench 10t2 extends through one of the active region 10a and the isolation region 10i. The trench 10t2 may have a fin structure in which the active region 10a protrudes more than the isolation region 10i. In other words, the depth of the transmission gate across the isolation region 10i is greater than the depth of the main gate across the active region 10a. Therefore, the trench 10t2 for the gate structure 12 has different depths for the main gate region and the transmission gate region.

The fin structure can increase the channel width and improve the electrical characteristics. In some embodiments, the fin structure can be omitted.

FIG2 is a schematic cross-sectional view of a semiconductor device 2 according to some embodiments of the present disclosure. The semiconductor device 2 of FIG2 is similar to the semiconductor device 1 of FIG1 , except for the following differences.

The gate structure 12 of the semiconductor device 2 further includes a barrier layer 12b1 disposed between the dielectric layer 12d1 and the gate electrode 12e1. The barrier layer 12b1 may be conformally formed on the surface of the dielectric layer 12d1. The base of the dielectric layer 12d2 may be disposed on the barrier layer 12b1. The base of the dielectric layer 12d2 may contact the barrier layer 12b1.

In some embodiments, the barrier layer 12b1 may include a metal-based material. The barrier layer 12b1 may include a metal nitride. The barrier layer 12b1 may include titanium nitride (TiN) or tantalum nitride (TaN).

The gate structure 12 of the semiconductor device 2 further includes a barrier layer 12b2 disposed between the dielectric layer 12d2 and the gate electrode 12e2. The barrier layer 12b2 may be disposed on a base of the dielectric layer 12d2.

The distance between the barrier layer 12b2 and the substrate 10 (ie, thickness t1 and thickness t2) may be greater than the distance between the barrier layer 12b1 and the substrate 10 (ie, thickness t1). For example, the barrier layer 12b2 and the barrier layer 12b1 may be at different distances from the substrate 10.

The barrier layers 12b1 and 12b2 may include the same or different materials. In some embodiments, the barrier layer 12b2 may include a metal-based material. The barrier layer 12b2 may include a metal nitride. The barrier layer 12b2 may include titanium nitride (TiN) or tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof.

FIG3 is a schematic cross-sectional view of a semiconductor device 3 according to some embodiments of the present disclosure. The semiconductor device 3 of FIG3 is similar to the semiconductor device 1 of FIG1 , except for the following differences.

The semiconductor device 3 may further include an isolation layer 30, contact plugs 31, 33, a bit line structure 32, and a memory device 34.

The isolation layer 30 may be a single layer or multiple layers. The isolation layer 30 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (N ₂ OSi ₂ ), silicon nitride oxide (N ₂ OSi ₂ ), etc. The isolation layer 30 may be used to isolate adjacent contact plugs 33 from each other.

The contact plug 31 may be electrically connected to the bit line structure 32 and the first doped region 101. The bit line structure 32 may include a bit line 32a, a bit line hard mask layer 32b, and a spacer 32c. The bit line 32a may include at least one material selected from polysilicon (poly-Si), metal silicide, metal nitride, and metal. The bit line hard mask layer 32b may include silicon oxide or silicon nitride. The spacer 32c may include a dielectric material. The spacer 32c may contact the dielectric layer 12d1, the dielectric layer 12d2, and/or the dielectric layer 12d3.

The contact plug 33 may be electrically connected to the memory element 34 and the second doped region 102 .

In some embodiments, the contact plugs 31 and 33 may include a suitable conductive material. For example, the contact plugs 31 and 33 may include tungsten (W), copper (Cu), aluminum (Al), silver (Ag), alloys thereof, or combinations thereof.

The memory element 34 may be a capacitor. Therefore, the memory element 34 may include a storage node in contact with the contact plug 33. The storage node may have a cylindrical or columnar shape. A capacitor dielectric layer may be formed on the surface of the storage node.

As DRAM devices become more highly integrated, it becomes more difficult to isolate the main gate in a memory cell (such as the electrode of gate structure 12) from the pass gate in an adjacent memory cell (such as the electrode of gate structure 11). For example, when the pass gate is turned on, an inversion layer can be created, which can expand the source/drain junction, thereby generating an internal electric field. The internal electric field can accelerate GIDL.

By forming a thicker dielectric layer (i.e., dielectric layers 12d1, 12d2, and 12d3) between the cap layer and the substrate, the effective electric field can be reduced and thus the GIDL can be reduced. Therefore, interference between word lines in different memory cells can be avoided, data retention time can be extended, and the operational reliability of the semiconductor device can be improved.

In addition, the dielectric layer (e.g., dielectric layer 12d1) between the lower gate electrode and the substrate can have a constant thickness, which helps to optimize the subthreshold swing and reduce the threshold voltage. Therefore, the channel ions (e.g., the channel ions in the channel region CH) can be increased. For example, the number, amount, density, or flow of electrons between doped regions can be increased. For example, assuming that the external resistance and the internal trap charge (or internal trap density) are constant, the channel ions can be increased by 20%, 40%, 60%, or more.

FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G, FIG. 4H, FIG. 4I, FIG. 4J, FIG. 4K, FIG. 4L, FIG. 4M, FIG. 4N, FIG. 4O, and FIG. 4P illustrate various stages of a method for preparing a semiconductor device according to some embodiments of the present disclosure. At least some of these figures have been simplified to better understand various aspects of the present disclosure. In some embodiments, the semiconductor device 3 in FIG. 3 can be prepared by the following operations described with reference to FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G, FIG. 4H, FIG. 4I, FIG. 4J, FIG. 4K, FIG. 4L, FIG. 4M, FIG. 4N, FIG. 4O, and FIG. 4P.

As shown in FIG. 4A , an isolation region 10i is formed in a substrate 10. An active region 10a is defined by the isolation region 10i. The isolation region 10i may be formed by an STI (shallow trench isolation) process. For example, after forming a liner layer (not shown) on the substrate 10, the liner layer and the substrate 10 are etched using an isolation mask (not shown) to define an isolation trench. The isolation trench is filled with a dielectric material to form the isolation region 10i.

A wall oxide, a liner, and a gap-filling dielectric may be sequentially formed as the isolation region 10i. The manufacturing technique of the liner may include stacking silicon oxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ). The gap-filling dielectric may include a SOD material. In another embodiment of the present disclosure, silicon nitride may be used as a gap-filling dielectric in the isolation region 10i. The isolation trench may be filled with a dielectric material by a chemical vapor deposition (CVD) process. In addition, a planarization process such as chemical-mechanical polishing (CMP) may be additionally performed.

Referring to FIG. 4B , a plurality of trenches 10t1 and 10t2 may then be formed in the substrate 10. Each of the trenches 10t1 and 10t2 may have a linear shape intersecting the active region 10a and the isolation region 10i. The manufacturing technique of each of the trenches 10t1 and 10t2 may include an etching process of the substrate 10 using a hard mask layer 40 as an etching mask. The hard mask layer 40 may be formed on the substrate 10 and have a linear opening. The hard mask layer 40 may include a material having etching selectivity to the substrate 10. Each of the trenches 10t1 and 10t2 may be formed shallower than the isolation trenches. In some embodiments, the bottom edge of each of the trenches 10t1 and 10t2 may have a curvature.

The active region 10a and the isolation region 10i may be etched simultaneously to form trenches 10t1 and 10t2. In some embodiments, due to the etching selectivity between the active region 10a and the isolation region 10i, the isolation region 10i is etched deeper than the active region 10a. Therefore, the gate trench may have a fin structure in which the active region 10a protrudes more than the isolation region 10i in the gate trench.

4C, a dielectric layer d1 may be formed on the surface of each of the trenches 10t1 and 10t2. Before forming the dielectric layer d1, the inner surface of each of the trenches 10t1 and 10t2 damaged by the etching process may be restored. For example, a sacrificial oxide may be formed by a thermal oxidation process, and then the sacrificial oxide may be removed.

The manufacturing technique of the dielectric layer d1 may include a thermal oxidation process, such as an in situ steam generation (ISSG) oxidation process. In some embodiments, the manufacturing technique of the dielectric layer d1 may include a deposition process, such as a CVD process or an ALD process.

4D, a barrier layer bl may be formed on the dielectric layer d1 and the hard mask layer 40. The barrier layer bl may be conformally formed on the surface of the dielectric layer d1. The barrier layer bl may be formed by an ALD or CVD process.

4E, a conductive layer e1 may be formed on the barrier layer bl. The conductive layer e1 may be formed on the barrier layer b1 to fill each of the trenches 10t1 and 10t2. The conductive layer e1 may include a low-resistance metal material. The conductive layer e1 may include tungsten (W). The manufacturing technology of the conductive layer e1 may include a CVD or ALD process.

4F, a recess process may be performed. The recess process may be performed by a dry etching process (eg, an etch-back process). The manufacturing technology of the barrier layers 11b1 and 12b1 may include performing an etch-back process on the barrier layer bl. The manufacturing technology of the gate electrodes 11e1 and 12e1 may include performing an etch-back process on the conductive layer e1.

The barrier layer 11b1 and the gate electrode 11e1 may be formed inside the trench 10t1. Top surfaces of the barrier layer 11b1 and the gate electrode 11e1 may be substantially coplanar or located at the same level. The barrier layer 12b1 and the gate electrode 12e1 may be formed inside the trench 10t2. Top surfaces of the barrier layer 12b1 and the gate electrode 12e1 may be substantially coplanar or located at the same level.

In some embodiments, a planarization process may be performed in advance to expose the top surface of the hard mask layer 40, and then an etch-back process may be performed.

After forming the barrier layer 12b1 and the gate electrode 12e1, a surface 12d1s of the dielectric layer 12d1 may be partially exposed.

4G, a dielectric layer d2 may be formed on the barrier layer 12b1 and the gate electrode 12e1. The dielectric layer d2 may directly contact the barrier layer 12b1 and the gate electrode 12e1. The dielectric layer d2 may directly contact the surface 12d1s of the dielectric layer 12d1. The manufacturing technology of the dielectric layer d2 may include ALD or CVD.

4H, a barrier layer b2 may be formed on the dielectric layer d2. The dielectric layer d2 may be disposed between the barrier layer b2 and the gate electrode 12e1. The barrier layer b2 may be formed non-conformally. The manufacturing technology of the non-conformal barrier layer b2 may include physical vapor deposition (PVD).

Referring to FIG. 4I , a portion of the barrier layer b2 may be removed to expose a portion of the dielectric layer d2. For example, the barrier layer b2 may be subjected to an etching process. Thus, the barrier layer 11b1 and (Note: Please confirm) the barrier layer 11b2 may remain on the bottom surface of the dielectric layer d2.

Referring to FIG. 4J, a conductive layer e2 may be formed on the barrier layer 11b1, (Note: Please confirm) the barrier layer 11b2 and the dielectric layer d2. The conductive layer e2 may fill each trench. The conductive layer e2 may include a material having a low work function. The conductive layer e2 may include polycrystalline silicon having a low work function, such as polycrystalline silicon doped with N-type impurities. The manufacturing technology of the conductive layer e2 may include CVD or ALD.

Referring to FIG. 4K , a recess process may be performed. The recess process may be performed by a dry etching process (eg, an etch-back process). The manufacturing technology of the gate electrodes 11e2 and 12e2 may include performing an etch-back process on the conductive layer e2. After the gate electrode 12e2 is formed, the surface d2s of the dielectric layer d2 may be partially exposed.

4L, a dielectric layer d3 may be formed on the gate electrode 12e2. The dielectric layer d3 may directly contact the gate electrode 12e2. The dielectric layer d3 may directly contact the surface d2s of the dielectric layer d2. The manufacturing technology of the dielectric layer d3 may include ALD or CVD.

4M, capping layers 11c and 12c may be formed on the dielectric layer d3.

4N , the capping layers 11c and 12c may be planarized and the hard mask layer 40 may be removed to expose the top surfaces of the dielectric layers 12d1, 12d2, and 12d3. Through the above series of processes, the buried gate structures 11, 12, 13, and 14 may be formed.

4O , a doping process of impurities is performed by implantation or other doping techniques, thereby forming a first doping region 101 and a second doping region 102 in the substrate 10 .

In some embodiments, the first doped region 101 and the second doped region 102 may be formed after the other operations described. For example, the first doped region 101 and the second doped region 102 may be formed after one of the operations of FIG. 4A , FIG. 4B , FIG. 4C , FIG. 4D , FIG. 4E , FIG. 4F , FIG. 4G , FIG. 4H , FIG. 4I , FIG. 4J , FIG. 4K , FIG. 4L , and FIG. 4M .

4P , an isolation layer 30 may be formed on the top surface of the structure from FIG. 4N , for example, by ALD, CVD, PVD, remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), coating, etc. The isolation layer 30 may be patterned to define the locations of contact plugs 31 , 33 formed in subsequent operations. The contact plug 31 may be disposed on the first doped region 101. The contact plug 33 may be disposed on the second doped region 102. Then, the bit line structure 32 may be electrically connected to the contact plug 31. The memory element 34 may be electrically connected to the contact plug 33.

In some embodiments, after forming the memory element 34, a wiring layer (not shown) may be formed on the memory element 34. For example, the wiring layer may have a multi-layer wiring structure including a plurality of wiring layers and interlayer insulating films.

FIG. 5 is a flow chart illustrating a method 50 for fabricating a semiconductor device according to some embodiments of the present disclosure.

In some embodiments, the method 50 may include step S51 of forming a trench in a substrate. For example, as shown in FIG. 4B , a plurality of trenches 10 t 1 and 10 t 2 may be formed in the substrate 10 .

In some embodiments, the method 50 may include step S52 of disposing a lower barrier layer in the trench. For example, as shown in FIG. 4D , a barrier layer bl may be formed on the dielectric layer d1 and the hard mask layer 40. The barrier layer bl may be disposed in the trenches 10t1 and 10t2.

In some embodiments, method 50 may include step S53, disposing a lower gate electrode on the lower barrier layer in the trench. For example, as shown in FIG. 4E , a conductive layer e1 may be formed on the barrier layer bl. For example, as shown in FIG. 4F , gate electrodes 11e1 and 12e1 may be formed by performing an etching back process on the conductive layer e1. In some embodiments, barrier layers 11b1 and 12b1 may be formed by performing an etching back process on the barrier layer bl.

In some embodiments, method 50 may include step S54 of providing a lower dielectric layer on the lower gate electrode in the trench. For example, as shown in FIG. 4G , a dielectric layer d2 may be formed on the barrier layer 12b1 and the gate electrode 12e1. Similarly, a dielectric layer d2 may be formed on the barrier layer 11b1 and the gate electrode 11e1.

In some embodiments, method 50 may include step S55, providing a higher barrier layer on the lower dielectric layer in the trench. For example, as shown in FIG. 4H, barrier layer b2 may be formed on dielectric layer d2. For example, as shown in FIG. 4I, barrier layer 11b1 and (Note: Please confirm) barrier layer 11b2 may remain on the bottom surface of dielectric layer d2.

In some embodiments, method 50 may include step S56, setting a higher gate electrode on the lower dielectric layer in the trench. For example, as shown in FIG. 4J, a conductive layer e2 may be formed on the barrier layer 11b1, (Note: Please confirm) barrier layer 11b2, and dielectric layer d2. For example, as shown in FIG. 4K, gate electrodes 11e2 and 12e2 may be formed by performing an etching back process on the conductive layer e2.

In some embodiments, method 50 may include step S57 of disposing a higher dielectric layer on the higher gate electrode in the trench. For example, as shown in FIG. 4L , a dielectric layer d3 may be formed on the gate electrode 12e2.

In some embodiments, method 50 may include step S58 of disposing a capping layer on the higher dielectric layer in the trench. For example, as shown in FIG. 4M , capping layers 11c and 12c may be formed on dielectric layer d3. In FIG. 4N , capping layers 11c and 12c may be planarized and hard mask layer 40 may be removed to expose the top surfaces of dielectric layers 12d1, 12d2, and 12d3.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a trench and a gate structure located in the trench. The gate structure includes a higher gate electrode, a capping layer located on the higher gate electrode, and a first dielectric layer partially disposed between the higher gate electrode and the capping layer.

Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a trench and a gate structure located in the trench. The gate structure includes a higher gate electrode and a capping layer located on the higher gate electrode. A distance between the capping layer and the substrate is greater than a distance between the higher gate electrode and the substrate.

Another aspect of the present disclosure provides a method for preparing a semiconductor device. The method includes forming a trench in a substrate and disposing a higher gate electrode in the trench. The method also includes disposing a first dielectric layer on the higher gate electrode in the trench and disposing a capping layer on the first dielectric layer in the trench.

Forming a thicker dielectric layer in the trench can reduce the effective electric field and thus reduce GIDL. Therefore, interference between word lines in different memory cells can be avoided. Data retention time can be extended and the operational reliability of semiconductor devices can be improved.

In addition, the gate structure also includes a lower gate electrode and a dielectric layer between the lower gate electrode and the substrate. The dielectric layer between the lower gate electrode and the substrate can have a constant thickness, which helps to optimize the subthreshold swing and reduce the threshold voltage. Therefore, the channel ions can be increased. For example, the number, amount, density, or flow of electrons between the doped regions can be increased. For example, assuming that the external resistance and the internal trap charge (or internal trap density) are constant, the channel ions can be increased by 20%, 40%, 60%, or more.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure as defined by the scope of the patent application. For example, many of the above processes can be implemented in different ways, and other processes or combinations of the above processes can be used to replace many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the process, machine, manufacture, material composition, means, method and step in the specification. A person skilled in the art can understand from the disclosure of this disclosure that the existing or future developed process, machine, manufacture, material composition, means, method or step that has the same function or achieves substantially the same result as the corresponding embodiment described herein can be used according to this disclosure. Accordingly, such process, machine, manufacture, material composition, means, method or step is included in the scope of the patent application of this application.

1: semiconductor element 2: semiconductor element 3: semiconductor element 10: substrate 10a: active region 10i: isolation region 10t1: trench 10t2: trench 11: gate structure 11b1: barrier layer 11b2: barrier layer 11c: cover layer 11d1: dielectric layer 11d2: dielectric layer 11d3: dielectric layer 11e1: gate electrode 11e2: gate electrode 12: gate structure 12b1: barrier layer 12b2: barrier layer 12c: cover layer 12d1: dielectric layer 12d1s: surface 12d2: dielectric layer 12d3: dielectric layer 12e1: gate electrode 12e2: gate electrode 13: gate structure 14: gate structure 30: isolation layer 31: contact plug 32: bit line structure 32a: bit line 32b: bit line hard mask layer 32c: spacer 33: contact plug 34: memory element 40: hard mask layer 50: method 101: first doping region 102: second doping region A- A’: line B- B’: line b1: barrier layer b2: barrier layer CH: channel region d1: dielectric layer d2: dielectric layer d2s: surface d3: dielectric layer e1: conductive layer e2: conductive layer S51: step S52: step S53: step S54: step S55: step S56: step S57: step S58: step t1: thickness t2: thickness t3: thickness w1: width w2: width w3: width

A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims when considered in conjunction with the drawings, wherein like figure labels represent like elements throughout the drawings. FIG. 1A illustrates a plan view schematic diagram of a semiconductor element in some embodiments of the present disclosure. FIG. 1B illustrates a cross-sectional schematic diagram of a semiconductor element drawn along line A-A’ shown in FIG. 1A. FIG. 1C illustrates a cross-sectional schematic diagram of a semiconductor element drawn along line A-A’ shown in FIG. 1A. FIG. 1D illustrates a cross-sectional schematic diagram of a semiconductor element drawn along line A-A’ shown in FIG. 1A. FIG. 1E illustrates a cross-sectional schematic diagram of a semiconductor element drawn along line B-B’ shown in FIG. 1A. FIG. 2 illustrates a cross-sectional schematic diagram of a semiconductor element in some embodiments of the present disclosure. FIG3 illustrates a schematic cross-sectional view of a semiconductor element of some embodiments of the present disclosure. FIG4A illustrates one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. FIG4B illustrates one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. FIG4C illustrates one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. FIG4D illustrates one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. FIG4E illustrates one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. FIG4F illustrates one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. FIG4G illustrates one or more stages of a method for preparing a semiconductor element of some embodiments of the present disclosure. FIG. 4H illustrates one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 4I illustrates one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 4J illustrates one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 4K illustrates one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 4L illustrates one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 4M illustrates one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 4N illustrates one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 4O illustrates one or more stages of a method for preparing a semiconductor element according to some embodiments of the present disclosure. FIG. 4P illustrates one or more stages of a method for preparing a semiconductor device according to some embodiments of the present disclosure. FIG. 5 illustrates a flow chart of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

1:Semiconductor components

10: Substrate

10a: Active area

10i: Isolation area

10t1: Groove

10t2: Groove

11: Gate structure

11c: Covering layer

11d1: Dielectric layer

11d2: Dielectric layer

11d3: Dielectric layer

11e1: Gate electrode

11e2: Gate electrode

12: Gate structure

12c: Covering layer

12d1: Dielectric layer

12d2: Dielectric layer

12d3: Dielectric layer

12e1: Gate electrode

12e2: Gate electrode

13: Gate structure

14: Gate structure

101: First mixed area

102: Second mixed area

b1: Barrier layer

CH: Channel area

t1: thickness

t2: thickness

t3:Thickness

w1: width

w2: width

w3:width

Claims (19)

A semiconductor device includes: a substrate having a trench; and a gate structure located in the trench, wherein the gate structure includes: a higher gate electrode; a cover layer located on the higher gate electrode; and a first dielectric layer partially disposed between the higher gate electrode and the cover layer. A semiconductor device as described in claim 1, wherein a distance between the cover layer and the substrate is greater than a distance between the higher gate electrode and the substrate, and a width of the cover layer is smaller than a width of the higher gate electrode. A semiconductor device as described in claim 1, wherein the gate structure further comprises: a lower gate electrode separated from the higher gate electrode; and a second dielectric layer partially disposed between the higher gate electrode and the lower gate electrode. A semiconductor device as described in claim 3, wherein the higher gate electrode is disposed between the first dielectric layer and the second dielectric layer. A semiconductor device as described in claim 3, wherein a thickness of the first dielectric layer and a thickness of the second dielectric layer are substantially equal. A semiconductor device as described in claim 5, wherein the thickness of the first dielectric layer and the thickness of the second dielectric layer are between about 1.5 nanometers (nm) and about 3.0 nm. A semiconductor device as described in claim 3, wherein a thickness of the first dielectric layer is substantially twice a thickness of the second dielectric layer, and the thickness of the first dielectric layer is approximately 3.0 nm and the thickness of the second dielectric layer is approximately 1.5 nm. A semiconductor device as described in claim 3, wherein a thickness of the second dielectric layer is substantially twice a thickness of the first dielectric layer, and the thickness of the second dielectric layer is approximately 3.0 nm and the thickness of the first dielectric layer is approximately 1.5 nm. A semiconductor device as described in claim 3, wherein the gate structure further comprises: a third dielectric layer disposed between the substrate and the lower gate electrode, wherein the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer. A semiconductor device as described in claim 9, wherein a thickness of the third dielectric layer is substantially constant, and the thickness of the third dielectric layer is approximately 4.0 nm. A semiconductor device as described in claim 1, wherein the gate structure is disposed in an active region of the substrate. A semiconductor device as described in claim 1, wherein the gate structure is disposed in an isolation region of the substrate. A semiconductor device comprises: a substrate having a trench; and a gate structure located in the trench, wherein the gate structure comprises: a higher gate electrode; and a capping layer located on the higher gate electrode; wherein a distance between the capping layer and the substrate is greater than a distance between the higher gate electrode and the substrate; wherein the capping layer is separated from the substrate by a first dielectric layer, a second dielectric layer, and a third dielectric layer. A semiconductor device as described in claim 13, wherein the distance between the cover layer and the substrate is between about 7.0 nm and 12.0 nm. A semiconductor device as described in claim 14, wherein the first dielectric layer separates the capping layer from the higher gate electrode, the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer, a thickness of the third dielectric layer is substantially constant, and the thickness of the third dielectric layer is greater than a thickness of the first dielectric layer. A semiconductor device as described in claim 15, wherein the thickness of the third dielectric layer is greater than the thickness of the second dielectric layer. A semiconductor device as described in claim 14, wherein the gate structure further comprises: a lower gate electrode separated from the higher gate electrode. A semiconductor device as described in claim 17, wherein the second dielectric layer separates the lower gate electrode from the higher gate electrode. A semiconductor device as described in claim 17, wherein the third dielectric layer separates the lower gate electrode from the substrate.