TWI871633B - Semiconductor device having buried gate structure - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The gate structure includes a lower gate electrode and an upper gate electrode over the lower gate electrode. The gate structure also includes a first barrier layer disposed between the lower gate electrode and the upper gate electrode. The gate structure also includes a first dielectric layer disposed between the lower gate electrode and the upper gate electrode. The first dielectric layer is adjacent to the first barrier layer.

Description

Semiconductor device with buried gate structure

This application claims priority to U.S. Patent Application Nos. 17/861,282 and 17/861,743 (i.e., the priority date is "July 11, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device, and more particularly to a buried gate structure having a dielectric layer and a barrier layer between two electrodes.

A buried gate structure of a semiconductor element includes a gate dielectric layer and a gate electrode in a trench. The gate dielectric layer covers the surface of the trench, and the gate electrode partially fills the trench on the gate dielectric layer. The buried gate structure may be adjacent to (or on the same layer as) an impurity region or a junction region in an active region of the semiconductor element.

The gate induced drain leakage (GIDL) characteristic affects the performance of the semiconductor device. In a conventional process, the gate dielectric layer (or a sidewall dielectric) of the buried gate structure may inevitably be consumed, and the effective electric field near the gate electrode may become larger. This leads to the occurrence of GIDL. GIDL will discharge the stored charge, thereby deteriorating the operational reliability of the semiconductor device.

The above "prior art" description is only to provide background technology, and does not admit that the above "prior art" description discloses the subject matter of this disclosure, does not constitute the prior art of this disclosure, and any description of the above "prior art" should not be regarded as any part of this case.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate and a gate structure. The substrate has a trench and the gate structure is located in the trench. The gate structure includes a lower gate electrode and an upper gate electrode. The upper gate electrode is located on the lower gate electrode. The gate structure also includes a first barrier layer disposed between the lower gate electrode and the upper gate electrode. The gate structure also includes a first dielectric layer disposed between the lower gate electrode and the upper gate electrode. The first dielectric layer is adjacent to the first barrier layer.

Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate and a gate structure. The substrate has a trench and the gate structure is located in the trench. The gate structure includes a lower gate electrode and a lower dielectric layer. The lower dielectric layer is located between the lower gate electrode and the substrate. The gate structure also includes a first barrier layer located on the lower gate electrode. The first barrier layer is separated from the lower dielectric layer.

Another aspect of the present disclosure provides a method for preparing a semiconductor element. The preparation method includes forming a trench in a substrate and disposing a lower gate electrode in the trench. The preparation method also includes disposing a first dielectric layer on the lower gate electrode in the trench and partially removing the first dielectric layer to expose a portion of the lower gate electrode.

Forming a protective layer before setting a barrier layer can prevent the gate dielectric layer (or a sidewall dielectric) from being damaged or consumed. Therefore, the effective electric field can be reduced, and thus the GIDL can be reduced. The data retention time can be extended, and the operational reliability of the semiconductor device can also be improved.

In addition, a remaining portion of the protection layer can be adjacent to the barrier layer. By using a protection layer having a low dielectric constant (e.g., less than the dielectric constant of the sidewall dielectric), the effective electric field between the lower gate electrode and the upper gate electrode can be further reduced, which helps to reduce GIDL while maintaining good device performance.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

1:Semiconductor components

2: Semiconductor components

3: Semiconductor components

4: Semiconductor components

10: Base

10a: Active zone

10i: Isolation area

10t1: Groove

10t2: Groove

11: Gate structure

11b1: Barrier layer

11b2: Barrier layer

11c: Sealing layer

11d1: Dielectric layer

11d2: Dielectric layer

11e1: Gate electrode

11e2: Gate electrode

12: Gate structure

12b1: Barrier layer

12b2: Barrier layer

12b2u: Upper surface

12b2w: Lower surface

12c: Sealing layer

12d1: Dielectric layer

12d1s: side wall (surface)

12d2: Dielectric layer

12d2s: curved surface

12d2u: Upper surface

12d2w: Lower surface

12e1: Gate electrode

12e1u:Partial

12e2: Gate electrode

13: Gate structure

14: Gate structure

30: Isolation layer

31: Contact plug

32: Bit line structure

32a: Bit line

32b: Bit line hard mask layer

32c: Interstitial

33: Contact plug

34: Memory elements

40: Hard mask layer

60: Preparation method

101: First mixed area

102: Second mixed area

A-A': line

b1: barrier layer

B-B': line

C: Dashed frame

d1: dielectric layer

d2: Dielectric layer

e1: conductive layer

e2: Conductive layer

S61: Step

S62: Step

S63: Step

S64: Steps

S65: Step

S66: Step

S67: Step

t1: thickness

When referring to the embodiments and the drawings together with the scope of the patent application, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

FIG. 1A is a plan view illustrating semiconductor devices of some embodiments of the present disclosure.

FIG1B is a cross-sectional view of the semiconductor element along the line AA' in FIG1A.

FIG1C is a cross-sectional view of the semiconductor element along the BB' line in FIG1A.

FIG2A is a cross-sectional view illustrating a semiconductor device of some embodiments of the present disclosure.

FIG2B is a partial enlarged view of the semiconductor element in FIG2A illustrating some embodiments of the present disclosure.

FIG3 is a cross-sectional view illustrating semiconductor devices of some embodiments of the present disclosure.

FIG4 is a cross-sectional view illustrating semiconductor devices of some embodiments of the present disclosure.

FIG5A is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5B is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5C is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5D is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5E is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5F is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5G is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5H is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5I is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 5I' is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5J is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5K is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 5L is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 5M is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5N is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 5O is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG5P is a cross-sectional view illustrating an intermediate stage of a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG6 is a flow chart illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

The embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally be made by a person of ordinary skill in the art to which the present disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numerals.

It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the first element, component, region, layer, or part discussed below can be referred to as the second element, component, region, layer, or part without departing from the teachings of the present inventive concept.

The terms used herein are only used to describe specific embodiments and are not intended to be limited to the concepts of the present invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprise" and "include", when used in this specification, indicate the presence of the features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof.

FIG. 1A is a plan view of a semiconductor device 1 illustrating some embodiments of the present disclosure. FIG. 1B is a cross-sectional view of the semiconductor device 1 along the line AA' in FIG. 1A. FIG. 1C is a cross-sectional view of the semiconductor device 1 along the line BB' in FIG. 1A.

In some embodiments, the semiconductor element 1 can be disposed adjacent to a circuit. For example, the semiconductor element 1 can be disposed adjacent to a memory element, such as a dynamic random access memory (DRAM) element or the like.

Referring to FIG. 1A , the semiconductor device 1 may include a plurality of active regions 10a and an isolation region 10i (or an isolation layer) formed on a substrate 10. The active region 10a may be defined by the isolation region 10i.

The semiconductor element 1 may also include a plurality of gate structures, such as gate structures 11, 12, 13 and 14. Each active region 10a may pass through two gate structures and may be divided into three doped regions by the two gate structures. For example, the active region 10a may be divided into a first doped region 101 (disposed between gate structures 12 and 13) and a second doped region 102 (located on both sides of the first doped region 101).

The gate structures 11, 12, 13 and 14 may each have a line type extending in any direction. The gate structures 11, 12, 13 and 14 may each be a buried gate buried in a trench that passes through the active region 10a and the isolation region 10i. The gate structures 11, 12, 13 and 14 may each include one or more main gate portions (or main gates) buried in the active region 10a and one or more transmission gate portions (or transmission gates) buried in the isolation region 10i. For example, FIG. 1B shows a transmission gate of gate structure 11, a main gate of gate structure 12, a main gate of gate structure 13, and a transmission gate of gate structure 14. FIG. 1C shows that trench 10t2 (in which gate structure 12 is disposed) passes through one of active region 10a and isolation region 10i. The portion of gate structure 12 on active region 10a is a main gate.

As used in this disclosure, the term "main gate" refers to a gate configured to receive a voltage to address a memory cell, and the term "transfer gate" refers to a gate configured to receive a voltage to address an adjacent memory cell.

For example, gate structure 11 may be a transfer gate in one memory cell shown in FIG. 1B , but may become a main gate in another memory cell. In some embodiments, gate structure 12 may be a main gate in one memory cell shown in FIG. 1B , but may become a transfer gate in another memory cell.

Although the main gate and the transmission gate are described above as components or parts of the gate structure, the main gate and the transmission gate have different structures. For example, as shown in FIG. 1B , the depth of the trench 10t1 used for the transmission gate portion of the gate structure 11 is different from the depth of the trench 10t2 used for the main gate portion of the gate structure 12. The trench 10t1 can be deeper than the trench 10t2.

Referring to FIG. 1B , the semiconductor element 1 may include a substrate 10 , and gate structures 11 , 12 , 13 , and 14 formed in the substrate 10 .

The substrate 10 may include a semiconductor substrate. In some embodiments, the substrate 10 may include, for example, silicon (Si), single crystal silicon, polycrystalline silicon, amorphous silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V or II-VI semiconductor materials. In some other embodiments, the substrate 10 may include a layered semiconductor, such as silicon/silicon germanium, silicon-on-insulator, or silicon germanium-insulator.

An active region 10a and an isolation region 10i may be formed in the substrate 10. The active region 10a may be defined by the isolation region 10i. In some embodiments, the isolation region 10i may include a shallow trench isolation (STI) structure. The STI structure may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (N ₂ OSi ₂ ), silicon nitride oxide (N ₂ OSi ₂ ), etc.

A first doped region 101 and a second doped region 102 may be formed in the active region 10a. In some embodiments, the first doped region 101 and the second doped region 102 may be disposed on or near the top surface of the active region 10a. The first doped region 101 and the second doped region 102 may be located on both sides of the trench 10t2.

In some embodiments, the first doped region 101 and the second doped region 102 may be doped with an N-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). In some other embodiments, the first doped region 101 and the second doped region 102 may be doped with a P-type dopant, such as boron (B) or indium (In). In some embodiments, the first doped region 101 and the second doped region 102 may be doped with dopants or impurity ions having the same conductivity type. In some embodiments, the first doped region 101 and the second doped region 102 may be doped with dopants or impurity ions having different conductivity types.

The bottom surfaces of the first doped region 101 and the second doped region 102 may be located at a predetermined depth from the top surface of the active region 10a. The first doped region 101 and the second doped region 102 may contact the sidewall of the trench 10t2. The bottom surfaces of the first doped region 101 and the second doped region 102 may be higher than the bottom surface of the trench 10t2. Similarly, the bottom surfaces of the first doped region 101 and the second doped region 102 may be higher than the bottom surface of the trench 10t1.

In some embodiments, the first doped region 101 and the second doped region 102 may be referred to as source or drain regions. In some embodiments, the first doped region 101 may include a bit line contact region and may be electrically connected to a bit line structure (such as the bit line structure 32 shown in FIG. 4 ). The second doped region 102 may include a storage node junction region and may be electrically connected to a memory element (such as the memory element 34 shown in FIG. 4 ).

The trench 10t1 in the isolation region 10i and the trench 10t2 in the active region 10a are spaces in which gate structures 11 and 12 may be formed. The gate structure 11 in the isolation region 10i may include a transmission gate. The gate structure 12 in the active region 10a may include a main gate.

The groove 10t2 may have a shallower depth than the groove 10t1. The bottoms of the grooves 10t1 and 10t2 may each have an arc, as shown in the embodiment of FIG. 1B. However, in some other embodiments, the bottoms of the grooves 10t1 and 10t2 may be planes or other shapes.

The gate structure 12 may include dielectric layers 12d1, 12d2, gate electrodes 12e1, 12e2, a barrier layer 12b2 and a capping layer 12c.

The dielectric layer 12d1 may be conformally formed on the bottom surface and sidewalls of the trench 10t2. The dielectric layer 12d1 may surround or cover a portion of the gate electrode 12e1. The dielectric layer 12d1 may separate the gate electrode 12e1 from the substrate 10.

A sidewall 12d1s (or an extension portion) of the dielectric layer 12d1 may be disposed between the gate electrode 12e2 and the substrate 10. A bottom (or a base portion) of the dielectric layer 12d1 may be disposed between the gate electrode 12e1 and the substrate 10.

For example, the sidewall 12d1s may extend from the gate electrode 12e1 to the gate electrode 12e2. For example, the sidewall 12d1s may extend from the gate electrode 12e1 to the capping layer 12c. The sidewall 12d1s may contact the gate electrode 12e2. The sidewall 12d1s may contact the capping layer 12c. The sidewall 12d1s may be an inner surface of the trench 10t2.

During an etch-back operation on the barrier layer 12b2 (such as the operation illustrated in FIG. 5J ), the sidewalls 12d1s of the dielectric layer 12d1 may be protected. For example, the sidewalls 12d1s of the dielectric layer 12d1 may not be etched, consumed, or damaged during the etch-back operation on the barrier layer 12b2.

In some embodiments, the sidewall 12d1s of the dielectric layer 12d1 may have a substantially vertical profile. For example, the sidewall 12d1s of the dielectric layer 12d1 may be substantially perpendicular to the top surface of the active region 10a. For example, the sidewall 12d1s of the dielectric layer 12d1 may be substantially perpendicular to the upper surface 12b2u of the barrier layer 12b2. For example, the sidewall 12d1s of the dielectric layer 12d1 may be substantially perpendicular to the upper surface 12d2u of the dielectric layer 12d2.

In some embodiments, the dielectric layer 12d1 may have a constant thickness. For example, the thickness t1 of the sidewall 12d1s (or the extension portion) of the dielectric layer 12d1 between the gate electrode 12e2 and the substrate 10 and the bottom (or the base portion) of the dielectric layer 12d1 between the gate electrode 12e1 and the substrate 10 may be substantially equal.

In some embodiments, the thickness t1 of the sidewall 12d1s (or the extension portion) of the dielectric layer 12d1 between the gate electrode 12e2 and the substrate 10 and the bottom (or the base portion) of the dielectric layer 12d1 between the gate electrode 12e1 and the substrate 10 may be greater than about 3.6 nanometers (nm), such as about 4.0nm, 5.0nm or 6.0nm.

Any two of the surface of the dielectric layer 12d1, the surface of the capping layer 12c, and the top surface of the active region 10a may be substantially coplanar.

In some embodiments, the dielectric layer 12d1 may include, for example, _silicon oxide ( _SiO2 ), silicon nitride ( _Si3N4 ), silicon oxynitride ( _N2Osi2 ), silicon nitride oxide ( _N2Osi2 ), _a high-k material, or a combination thereof. The high-k material includes, for example, a dielectric material having a dielectric constant greater than that _of silicon dioxide ( _SiO2 ), or a dielectric material having a dielectric constant greater than about 3.9. In some embodiments, the dielectric layer 12d1 may include at least one metal element, such as ferrite (HfO2), silicon-doped ferrite (HSO), laminar oxide (La2O3), laminar aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium [ortho] silicate (ZrSiO4), aluminum oxide (Al2O3), or a combination thereof.

The barrier layer 12b2 may be disposed between the gate electrodes 12e1 and 12e2. The barrier layer 12b2 may be sandwiched between the gate electrodes 12e1 and 12e2. The barrier layer 12b2 may be covered or embedded by the gate electrodes 12e1 and 12e2. The barrier layer 12b2 may directly contact the gate electrodes 12e1 and 12e2.

The barrier layer 12b2 may be separated from the dielectric layer 12d1. The barrier layer 12b2 may be separated from the dielectric layer 12d1 through the dielectric layer 12d2. From the cross-sectional view shown in FIG. 1B , the barrier layer 12b2 may be disposed between two portions of the dielectric layer 12d2.

In some embodiments, the barrier layer 12b2 may include a metal-based material. The barrier layer 12b2 may include a metal nitride. The barrier layer 12b2 may include titanium nitride (TiN) or tantalum nitride (TaN).

The dielectric layer 12d2 may be disposed between the gate electrodes 12e1 and 12e2. The dielectric layer 12d2 may be sandwiched between the gate electrodes 12e1 and 12e2. The dielectric layer 12d2 may be covered or embedded by the gate electrodes 12e1 and 12e2. The dielectric layer 12d2 may directly contact the gate electrodes 12e1 and 12e2.

The dielectric layer 12d2 may separate the barrier layer 12b2 from the dielectric layer 12d1. The dielectric layer 12d2 may be disposed adjacent to the barrier layer 12b2. The dielectric layer 12d2 may contact the barrier layer 12b2.

From the cross-sectional view shown in FIG. 1B , the dielectric layer 12d2 may contact two sides of the barrier layer 12b2. In some embodiments, the dielectric layer 12d2 may surround the barrier layer 12b2. For example, the dielectric layer 12d2 may completely surround the barrier layer 12b2 and prevent the barrier layer 12b2 from contacting the sidewall 12d1s of the dielectric layer 12d1.

In some embodiments, the upper surface 12d2u of the dielectric layer 12d2 and the upper surface 12b2u of the barrier layer 12b2 may be substantially coplanar. For example, the upper surface 12d2u of the dielectric layer 12d2 and the upper surface 12b2u of the barrier layer 12b2 may form a plane.

In some embodiments, the lower surface 12d2w of the dielectric layer 12d2 and the lower surface 12b2w of the barrier layer 12b2 may be substantially coplanar. For example, the lower surface 12d2w of the dielectric layer 12d2 and the lower surface 12b2w of the barrier layer 12b2 may form a plane.

In some embodiments, a thickness of the dielectric layer 12d2 and a thickness of the barrier layer 12b2 may be substantially equal.

During the etching back operation of the barrier layer 12b2 (such as the operation illustrated in FIG. 5J ), the dielectric layer 12d2 can prevent the sidewalls 12d1s of the dielectric layer 12d1 from being etched, consumed or damaged. Therefore, the dielectric layer 12d2 can serve as a protective layer or a passivation layer for the dielectric layer 12d1.

In some embodiments, the dielectric layer 12d2 and the barrier layer 12b2 may include different nitrides. For example, the barrier layer 12b2 may include TiN and the dielectric layer 12d2 may include a nitride other than TiN.

In some embodiments, a dielectric constant of dielectric layer 12d2 may be different from a dielectric constant of dielectric layer 12d1. For example, a dielectric constant of dielectric layer 12d2 may be smaller than a dielectric constant of dielectric layer 12d1.

In some embodiments, the manufacturing techniques of the dielectric layer 12d2 and the dielectric layer 12d1 may include different processes. For example, the manufacturing technique of the dielectric layer 12d1 may include a thermal oxidation process. The manufacturing technique of the dielectric layer 12d2 may include an atomic layer deposition (ALD) process.

In some embodiments, dielectric layer 12d1 and dielectric layer 12d2 may have different densities, such as different particle densities. For example, a density of dielectric layer 12d1 may be less than a density of dielectric layer 12d2. A density of dielectric layer 12d2 may be greater than a density of dielectric layer 11d1. For example, a density of dielectric layer 12d2 may be greater than a density of dielectric layer 12d1.

The gate electrode 12e1 can be disposed on the dielectric layer 12d1 and separated from the substrate 10 by the dielectric layer 12d1. The gate electrode 12e1 can be separated from the substrate 10 by a certain distance (for example, thickness t1).

The gate electrode 12e1 may be covered by the lower surface 12d2w of the dielectric layer 12d2 and the lower surface 12b2w of the barrier layer 12b2. The gate electrode 12e1 may contact the lower surface 12d2w of the dielectric layer 12d2 and the lower surface 12b2w of the barrier layer 12b2. The gate electrode 12e1 may also be referred to as a lower gate electrode relative to the gate electrode 12e2.

In some embodiments, the gate electrode 12e1 may include a single layer of metal, a metal composite material, or a plurality of conductive material layers. In some embodiments, the gate electrode 12e1 may include a metal base material. For example, the gate electrode 12e1 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), a stack thereof, or a combination thereof.

The gate electrode 12e2 may be disposed on the upper surface 12d2u of the dielectric layer 12d2 and the upper surface 12b2u of the barrier layer 12b2. The gate electrode 12e2 may contact the upper surface 12d2u of the dielectric layer 12d2 and the upper surface 12b2u of the barrier layer 12b2. The gate electrode 12e2 may be spaced a certain distance from the substrate 10 (e.g., thickness t1).

The gate electrode 12e2 may be covered or surrounded by the dielectric layer 12d1 and the capping layer 12c. The gate electrode 12e2 may also be referred to as an upper gate electrode relative to the gate electrode 12e1.

In some embodiments, the gate electrode 12e2 may include a single layer of metal, a metal composite material, or multiple layers of conductive material. In some embodiments, the gate electrode 12e2 may include polycrystalline silicon (poly-Si), titanium nitride (TiN), tungsten nitride (WN), or similar materials.

In some embodiments, the gate electrodes 12e1 and 12e2 can be used as word lines. For example, the gate electrodes 12e1 and 12e2 can be used together with bit lines (such as the bit line structure 32 shown in FIG. 4) to address memory cells. For example, the gate electrode 12e2 can be used as a gate electrode of a transistor in a memory cell. The second doped region 102 and the first doped region 101 can be used as a drain region and a source region of the transistor. The second doped region 102 can be coupled to a capacitor or a memory element (such as the memory element 34 shown in FIG. 4 ), and the first doped region 101 can be coupled to a bit line (such as the bit line structure 32 shown in FIG. 4 ). The transistor can retain the charge in the capacitor.

In some embodiments, the gate electrode 12e2 may have a low work function. In some embodiments, the gate electrode 12e1 may have a high work function. The high work function refers to a work function greater than a mid-gap work function of silicon. The low work function refers to a work function less than the mid-gap work function of silicon. Specifically, the high work function may be greater than 4.5 eV, and the low work function may be less than 4.5 eV.

The capping layer 12c may be disposed on the gate electrode 12e2. The capping layer 12c may contact the sidewall 12d1s of the dielectric layer 12d1. The capping layer 12c may be separated from the substrate 10 through the dielectric layer 12d1. The capping layer 12c may be used to protect the gate electrode 12e2. The capping layer 12c may have a surface substantially coplanar with the top surface of the active region 10a.

In some embodiments, the capping layer 12c may include a dielectric material such as _silicon oxide ( _SiO2 ), silicon nitride ( _Si3N4 ), silicon oxynitride ( _N2Osi2 ) and silicon _nitride oxide (N2Osi2). In some embodiments, the capping layer 12c may include a silicon nitride pad and a spin-on dielectric (SOD) material.

The gate structure 11 may include dielectric layers 11d1, 11d2, gate electrodes 11e1, 11e2, a barrier layer 11b2, and a capping layer 11c. The structure of the gate structure 11 is similar to the structure of the gate structure 12, except that the gate structure 11 is disposed in the isolation region 10i.

Referring to FIG. 1C , the trench 10t2 extends through one of the active region 10a and the isolation region 10i. The trench 10t2 may have a fin-like structure in which the active region 10a protrudes more than the isolation region 10i. In other words, the depth of the transmission gate (through the isolation region 10i) is greater than the depth of the main gate (through the active region 10a). Therefore, the trench 10t2 for the gate structure 12 has different depths for the main gate region and the transmission gate region.

The fin structure can increase the channel width and improve the electrical characteristics. In some embodiments, the fin structure can be omitted.

FIG. 2A is a cross-sectional view of a semiconductor device 2 according to some embodiments of the present disclosure. FIG. 2B is a partial enlarged view of a semiconductor device 2 in a dashed frame C according to some embodiments of the present disclosure. The semiconductor device 2 of FIG. 2A is similar to the semiconductor device 1 of FIG. 1B , except for the differences described below.

The dielectric layer 12d2 of the semiconductor element 2 has a curved surface 12d2s extending between the upper surface 12d2u and the lower surface 12d2w. For example, the curved surface 12d2s may have a smoothly curved shape. For example, the curved surface 12d2s may have a circular shape.

The arc surface 12d2s may be covered by the barrier layer 12b2. For example, an interface between the barrier layer 12b2 and the dielectric layer 12d2 may be curved. For example, a portion of the barrier layer 12b2 may be located between the dielectric layer 12d2 and the gate electrode 12e2 in a direction substantially perpendicular to the top surface of the active region 10a.

For example, a width of the barrier layer 12b2 may gradually taper from the gate electrode 12e2 to the gate electrode 12e1. For example, a width of the barrier layer 12b2 may vary. For example, a width of the barrier layer 12b2 adjacent to the top surface of the active region 10a may be greater than a width of the barrier layer 12b2 away from the top surface of the active region 10a.

FIG. 3 is a cross-sectional view of a semiconductor device 3 according to some embodiments of the present disclosure. The semiconductor device 3 of FIG. 3 is similar to the semiconductor device 1 of FIG. 1B , except for the differences described below.

The gate structure 12 of the semiconductor element 3 further includes a barrier layer 12b1 disposed between the dielectric layer 12d1 and the gate electrode 12e1. The barrier layer 12b1 may be conformally formed on the surface of the dielectric layer 12d1. The lower surface 12d2w of the dielectric layer 12d2 may contact the barrier layer 12b1.

The barrier layer 12b2 may be spaced apart from the barrier layer 12b1. The barrier layer 12b2 and the barrier layer 12b1 may be spaced apart from the substrate 10 at different distances.

The barrier layers 12b1 and 12b2 may include the same material or different materials. In some embodiments, the barrier layer 12b1 may include a metal-based material. The barrier layer 12b1 may include a metal nitride. The barrier layer 12b1 may include titanium nitride (TiN) or tantalum nitride (TaN).

FIG. 4 is a cross-sectional view of a semiconductor device 4 according to some embodiments of the present disclosure. The semiconductor device 4 of FIG. 4 is similar to the semiconductor device 1 of FIG. 1B , except for the differences described below.

The semiconductor element 4 may also include an isolation layer 30, contact plugs 31, 33, a bit line structure 32 and a memory element 34.

The isolation layer 30 may be a single layer or multiple layers. The isolation layer 30 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (N ₂ Osi ₂ ), silicon nitride oxide (N ₂ Osi ₂ ), etc. The isolation layer 30 may be used to isolate adjacent contact plugs 33 .

The contact plug 31 can electrically connect the bit line structure 32 and the first doped region 101. The bit line structure 32 may include a bit line 32a, a bit line hard mask layer 32b, and a spacer 32c. The bit line 32a may include at least one material selected from a polysilicon (poly-Si), a metal silicide, a metal nitride, and a metal. The bit line hard mask layer 32b may include silicon oxide or silicon nitride. The spacer 32c may include a dielectric material.

The contact plug 33 can electrically connect the memory element 34 and the second doped region 102.

In some embodiments, the contact plugs 31 and 33 may include a suitable conductive material. For example, the contact plugs 31 and 33 may include tungsten (W), copper (Cu), aluminum (Al), silver (Ag), alloys thereof, or combinations thereof.

The memory element 34 may be a capacitor. Therefore, the memory element 34 may include a storage node that contacts the contact plug 33. The storage node may have a cylindrical shape or a columnar shape. A capacitor dielectric layer may be formed on the surface of the storage node.

In a conventional process, during the etching back operation of the barrier layer (such as the operation illustrated in FIG. 5J ), the gate dielectric layer or the sidewall dielectric (such as the dielectric layer 12d1) of the buried gate structure (such as the gate structure 12) may be inevitably consumed and the effective electric field near the gate electrode (such as an electrode of the gate structure 12) may become larger, which leads to the occurrence of GIDL.

Forming a protective layer (such as dielectric layer 12d2) before setting a barrier layer (such as barrier layer 12b2) can prevent the gate dielectric layer or the sidewall dielectric (such as dielectric layer 12d1) from being damaged or consumed. Therefore, the effective electric field can be reduced, and thus GIDL can be reduced. The data retention time can be extended, and the operational reliability of the semiconductor device can also be improved.

In addition, a remaining portion of the protection layer can be adjacent to the barrier layer. By using a protection layer with a low dielectric constant (e.g., less than the dielectric constant of the sidewall dielectric), the effective electric field between the lower gate electrode and the upper gate electrode can be further reduced, which helps to reduce GIDL while maintaining good device performance.

Figures 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, 5L, 5M, 5N, 5O, and 5P respectively illustrate intermediate stages of methods for preparing semiconductor devices of some embodiments of the present disclosure. At least some of these figures have been simplified for better understanding of various aspects of the present disclosure. In some embodiments, the semiconductor device 4 in Figure 4 can be prepared by the following operations with respect to Figures 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, 5L, 5M, 5N, 5O, and 5P.

As shown in FIG. 5A , an isolation region 10i is formed in the substrate 10. The active region 10a is defined by the isolation region 10i. The manufacturing technology of the isolation region 10i can be through an STI (shallow trench isolation) process. For example, after forming a pad (not shown) on the substrate 10, an isolation mask (not shown) is used to etch the pad and the substrate 10 to define an isolation trench. The isolation trench is filled with a dielectric material, thereby forming the isolation region 10i.

A wall oxide, a liner and a gap filling dielectric may be sequentially formed as the isolation region 10i. The manufacturing technology of the liner may include stacking silicon oxide (SiO2) and silicon nitride (Si3N4). The gap filling dielectric may include a SOD material. In another embodiment of the present disclosure, in the isolation region 10i, silicon nitride may be used as the gap filling dielectric. Through a chemical vapor deposition (CVD) process, the isolation trench may be filled with a dielectric material. In addition, a planarization process such as a chemical mechanical polishing (CMP) may be performed separately.

Referring to FIG. 5B , a plurality of trenches 10t1 and 10t2 may then be formed in the substrate 10. Each of the trenches 10t1 and 10t2 may have a line shape passing through the active region 10a and the isolation region 10i. The manufacturing technology of each of the trenches 10t1 and 10t2 may include an etching process performed on the substrate 10 using a hard mask layer 40 as an etching mask. The hard mask layer 40 may be formed on the substrate 10 and have a linear opening. The hard mask layer 40 may include a material having an etching selectivity to the substrate 10. Each of the trenches 10t1 and 10t2 may be formed to be shallower than the isolation trench. In some embodiments, the bottom edge of each of the grooves 10t1 and 10t2 may have a curvature.

The active region 10a and the isolation region 10i may be etched simultaneously to form trenches 10t1 and 10t2. In some embodiments, due to an etching selectivity between the active region 10a and the isolation region 10i, the isolation region 10i is etched deeper than the active region 10a. Therefore, the gate trench may have a fin-like structure in which the active region 10a protrudes more than the isolation region 10i in the gate trench.

Referring to FIG. 5C , a dielectric layer d1 may be formed on the surface of each of the trenches 10t1 and 10t2. Before forming the dielectric layer d1, the inner surface of each of the trenches 10t1 and 10t2 that is damaged in the etching process may be restored. For example, a sacrificial oxide may be formed by a thermal oxidation process and then removed.

The manufacturing technology of the dielectric layer d1 may include a thermal oxidation process. In some embodiments, the manufacturing technology of the dielectric layer d1 may include a deposition process, such as a CVD process or an ALD process.

Referring to FIG. 5D , a barrier layer b1 may be formed on the dielectric layer d1 and the hard mask layer 40. The barrier layer b1 may be conformally formed on the surface of the dielectric layer d1. The manufacturing technology of the barrier layer b1 may include an ALD or CVD process.

Referring to FIG. 5E , a conductive layer e1 may be formed on the barrier layer b1. The conductive layer e1 may be formed on the barrier layer b1 to fill each of the trenches 10t1 and 10t2. The conductive layer e1 may include a low-resistance metal material. The conductive layer e1 may include tungsten (W). The manufacturing technology of the conductive layer e1 may include a CVD or ALD process.

Referring to FIG. 5F , a recess process may be performed. The recess process may include a dry etching process, such as an etch-back process. The manufacturing technology of the barrier layers 11b1 and 12b1 may include performing the etch-back process on the barrier layer b1. The manufacturing technology of the gate electrodes 11e1 and 12e1 may include performing the etch-back process on the conductive layer e1.

A barrier layer 11b1 and a gate electrode 11e1 may be formed in the trench 10t1. The top surfaces of the barrier layer 11b1 and the gate electrode 11e1 may be substantially coplanar or may be at the same level. A barrier layer 12b1 and a gate electrode 12e1 may be formed in the trench 10t2. The top surfaces of the barrier layer 12b1 and the gate electrode 12e1 may be substantially coplanar or may be at the same level.

In some embodiments, a planarization process may be performed in advance to expose the top surface of the hard mask layer 40, and then the etch back process may be performed.

After forming the barrier layer 12b1 and the gate electrode 12e1, the sidewall 12d1s of the dielectric layer 12d1 may be partially exposed.

Referring to FIG. 5G , a dielectric layer d2 may be formed on the barrier layer 12b1 and the gate electrode 12e1. The dielectric layer d2 may directly contact the barrier layer 12b1 and the gate electrode 12e1. The dielectric layer d2 may directly contact the sidewall 12d1s of the dielectric layer 12d1. The manufacturing technology of the dielectric layer d2 may include ALD or CVD. In some embodiments, the thickness of the dielectric layer d2 may vary with the depth of the trench. For example, the dielectric layer d2 may be thicker at a deeper position.

Referring to FIG. 5H , a portion of the dielectric layer d2 may be removed to expose a portion 12e1u of the gate electrode 12e1. In some embodiments, the removal technique of the dielectric layer d2 includes an anisotropic etching operation. The dielectric layer 12d2 may be formed in the trench 10t2 and the dielectric layer 11d2 may be formed in the trench 10t1. In some embodiments, the remaining dielectric layer d2 may have a substantially vertical profile (as shown in FIG. 1B ) or a curved profile (as shown in FIG. 2B ).

Referring to FIG. 5I , a barrier layer 12b2 may be formed on a portion 12e1u of the gate electrode 12e1. The barrier layer 12b2 may be formed by physical vapor deposition (PVD).

The barrier layer 12b2 may fill up the trench 10t2. However, in some other embodiments, as shown in FIG. 5I', the barrier layer 12b2 may not fill up the trench 10t2. The top surface of the barrier layer 12b2 may be lower than the top surface of the dielectric layer 12d2.

Referring to FIG. 5J , a portion of the barrier layer 12b2 and a portion of the dielectric layer 12d2 may be removed to expose the sidewall 12d1s of the dielectric layer 12d1. An upper surface 12d2u of the dielectric layer 12d2 and an upper surface 12b2u of the barrier layer 12b2 may be formed. The manufacturing technology of the upper surface 12d2u and the upper surface 12b2u may include performing the etching back process on the dielectric layer 12d2 and the barrier layer 12b2.

During the etching back operation, the dielectric layer 12d2 can prevent the sidewalls 12d1s of the dielectric layer 12d1 from being etched, consumed or damaged. Therefore, the dielectric layer 12d2 can serve as a protective layer or a passivation layer for the dielectric layer 12d1.

Referring to FIG. 5K , a conductive layer e2 may be formed on the barrier layer 11b2, the dielectric layer 11d2, the barrier layer 12b2, and the dielectric layer 12d2. The conductive layer e2 may fill each trench. The conductive layer e2 may include a material having a low work function. The conductive layer e2 may include a polycrystalline silicon having a low work function, for example, polycrystalline silicon doped with N-type impurities. The manufacturing technology of the conductive layer e2 may include CVD or ALD.

Referring to FIG. 5L , a recess process may be performed. The recess process may include a dry etching process, such as an etch-back process. The manufacturing technology of the gate electrodes 11e2 and 12e2 may include performing the etch-back process on the conductive layer e2.

Referring to FIG. 5M , capping layers 11c and 12c may be formed on gate electrodes 11e2 and 12e2, respectively.

Referring to FIG. 5N , the capping layers 11c and 12c may be planarized and the hard mask layer 40 may be removed to expose the top surfaces of the dielectric layers 11d1 and 12d1. Through the above series of processes, buried gate structures 11, 12, 13 and 14 may be formed.

Referring to FIG. 5O , a doping process is performed by implantation or other doping techniques. Thus, a first doping region 101 and a second doping region 102 are formed in the substrate 10 .

In some embodiments, the first doping region 101 and the second doping region 102 may be formed after other operations described. For example, the first doping region 101 and the second doping region 102 may be formed after one of the operations in FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D, FIG. 5E, FIG. 5F, FIG. 5G, FIG. 5H, FIG. 5I, FIG. 5J, FIG. 5K, FIG. 5L, FIG. 5M, and FIG. 5N.

Referring to FIG. 5P , an isolation layer 30 may be formed on the top surface of the structure of FIG. 5N by, for example, ALD, CVD, PVD, remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), coating, etc. The isolation layer 30 may be patterned to define locations where contact plugs 31, 33 are formed in subsequent operations. The contact plug 31 may be disposed on the first doped region 101. The contact plug 33 may be disposed on the second doped region 102. Then, the bit line structure 32 may be electrically connected to the plug 31. The memory element 34 may be electrically connected to the plug 33.

In some embodiments, after the memory element 34 is formed, a wiring layer (not shown) may be formed on the memory element 34. For example, the wiring layer may have a multi-layer wiring structure including a plurality of wiring layers and interlayer insulating films.

FIG6 is a flow chart illustrating a method 60 for preparing a semiconductor device according to some embodiments of the present disclosure.

In some embodiments, the preparation method 60 may include step S61, forming a trench in a substrate. For example, as shown in FIG. 5B , a plurality of trenches 10t1 and 10t2 are formed in the substrate 10.

In some embodiments, the preparation method 60 may include step S62, setting a gate electrode in the trench. For example, as shown in FIG. 5E, a conductive layer e1 is formed in the trenches 10t1 and 10t2. For example, as shown in FIG. 5F, the manufacturing technology of the gate electrodes 11e1 and 12e1 may include performing the etching back process on the conductive layer e1.

In some embodiments, the preparation method 60 may include step S63, disposing a dielectric layer on the lower gate electrode in the trench. For example, as shown in FIG. 5G , a dielectric layer d2 may be formed on the gate electrode 12e1. Similarly, a dielectric layer d2 may be formed on the gate electrode 11e1.

In some embodiments, the preparation method 60 may include step S64, partially removing the dielectric layer to expose a portion of the lower gate electrode. For example, as shown in FIG. 5H, a portion of the dielectric layer d2 is removed to expose a portion 12e1u of the gate electrode 12e1.

In some embodiments, the preparation method 60 may include step S65, providing a barrier layer on the portion of the lower gate electrode. For example, as shown in FIG. 5I , a barrier layer 12b2 is formed on the portion 12e1u of the gate electrode 12e1.

In some embodiments, the preparation method 60 may include step S66, partially removing the dielectric layer and the barrier layer. For example, as shown in FIG. 5J, a portion of the barrier layer 12b2 and a portion of the dielectric layer 12d2 may be removed.

In some embodiments, the preparation method 60 may include step S67, providing an upper gate electrode on the dielectric layer in the trench. For example, as shown in FIG. 5K, the conductive layer e2 may fill each trench. As shown in FIG. 5L, the manufacturing technology of the gate electrodes 11e2 and 12e2 may include performing the etching back process on the conductive layer e2.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate and a gate structure. The substrate has a trench and the gate structure is located in the trench. The gate structure includes a lower gate electrode and an upper gate electrode. The upper gate electrode is located on the lower gate electrode. The gate structure also includes a first barrier layer disposed between the lower gate electrode and the upper gate electrode. The gate structure also includes a first dielectric layer disposed between the lower gate electrode and the upper gate electrode. The first dielectric layer is adjacent to the first barrier layer.

Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate and a gate structure. The substrate has a trench and the gate structure is located in the trench. The gate structure includes a lower gate electrode and a lower dielectric layer. The lower dielectric layer is located between the lower gate electrode and the substrate. The gate structure also includes a first barrier layer located on the lower gate electrode. The first barrier layer is separated from the lower dielectric layer.

Another aspect of the present disclosure provides a method for preparing a semiconductor device. The preparation method includes forming a trench in a substrate and disposing a lower gate electrode in the trench. The preparation method also includes disposing a first dielectric layer on the lower gate electrode in the trench and partially removing the first dielectric layer to expose a portion of the lower gate electrode.

Forming a protective layer before setting a barrier layer can prevent the gate dielectric layer (or a sidewall dielectric) from being damaged or consumed. Therefore, the effective electric field can be reduced, and thus the GIDL can be reduced. The data retention time can be extended, and the operational reliability of the semiconductor device can also be improved.

In addition, a remaining portion of the protection layer can be adjacent to the barrier layer. By using a protection layer with a low dielectric constant (e.g., less than the dielectric constant of the sidewall dielectric), the effective electric field between the lower gate electrode and the upper gate electrode can be further reduced, which helps to reduce GIDL while maintaining good device performance.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined by the scope of the patent application. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacturing, material compositions, means, methods and steps described in the specification. A person skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

1:Semiconductor components

10: Base

10a: Active zone

10i: Isolation area

10t1: Groove

10t2: Groove

11: Gate structure

11b2: Barrier layer

11c: Sealing layer

11d1: Dielectric layer

11d2: Dielectric layer

11e1: Gate electrode

11e2: Gate electrode

12: Gate structure

12b2: Barrier layer

12b2u: Upper surface

12b2w: Lower surface

12c: Sealing layer

12d1: Dielectric layer

12d1s: Side wall

12d2: Dielectric layer

12d2u: Upper surface

12d2w: Lower surface

12e1: Gate electrode

12e2: Gate electrode

13: Gate structure

14: Gate structure

101: First mixed area

102: Second mixed area

t1: thickness

Claims (18)

A semiconductor element comprises: a substrate having a trench; and a gate structure in the trench, wherein the gate structure comprises: a lower gate electrode; an upper gate electrode on the lower gate electrode; a first barrier layer disposed between the lower gate electrode and the upper gate electrode; and a first dielectric layer disposed between the lower gate electrode and the upper gate electrode; wherein the first dielectric layer is adjacent to the first barrier layer; wherein an upper surface of the first barrier layer and an upper surface of the first dielectric layer are substantially coplanar. A semiconductor device as described in claim 1, wherein the first barrier layer is in contact with the lower gate electrode and the upper gate electrode. A semiconductor device as described in claim 2, wherein the first dielectric layer contacts the lower gate electrode and the upper gate electrode. A semiconductor device as described in claim 1, wherein the first barrier layer and the first dielectric layer include different nitrides. A semiconductor device as described in claim 1, wherein the lower surface of the first barrier layer and the lower surface of the first dielectric layer are substantially coplanar. The semiconductor device as described in claim 1 further includes: a second dielectric layer disposed between the lower gate electrode and the substrate. A semiconductor device as described in claim 6, wherein the first barrier layer is separated from the second dielectric layer by the first dielectric layer. A semiconductor device as described in claim 6, wherein the second dielectric layer includes a sidewall between the upper gate electrode and the substrate. A semiconductor device as described in claim 8, wherein the sidewall of the second dielectric layer is substantially perpendicular to an upper surface of the first barrier layer. A semiconductor device as described in claim 1, wherein the first dielectric layer includes a curved surface. A semiconductor device as described in claim 10, wherein the arcuate surface of the first dielectric layer is covered by the first barrier layer. The semiconductor device as described in claim 1 further includes: a second barrier layer disposed between the lower gate electrode and the substrate. A semiconductor device as described in claim 12, wherein the second barrier layer is in contact with the first dielectric layer. A semiconductor device comprises: a substrate having a trench; and a gate structure in the trench, wherein the gate structure comprises: a lower gate electrode; a lower dielectric layer between the lower gate electrode and the substrate; and a first barrier layer on the lower gate electrode; wherein the first barrier layer is spaced apart from the lower dielectric layer; wherein an upper surface of the first barrier layer and an upper surface of the upper dielectric layer are substantially coplanar. A semiconductor device as described in claim 14, wherein the lower dielectric layer includes a side wall, and the side wall is substantially perpendicular to an upper surface of the first barrier layer. The semiconductor device as described in claim 14 further includes: an upper dielectric layer that separates the first barrier layer from the lower dielectric layer. A semiconductor device as described in claim 16, wherein the first barrier layer and the upper dielectric layer include different nitrides. A semiconductor device as described in claim 16, wherein the lower gate electrode is covered by the first barrier layer and the upper dielectric layer.