TWI892595B - Method of forming semiconductor structure - Google Patents

Abstract

The disclosure provides a method of forming a semiconductor structure. A method of forming a semiconductor structure includes forming a dielectric stack over a conductive layer, wherein forming the dielectric stack includes forming a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer in sequence. A bottom electrode layer is formed in the dielectric stack, wherein the bottom electrode layer has a first critical dimension in the first support layer. The bottom electrode layer and the third support are etched to form a first hole exposing the second sacrificial layer. The second sacrificial layer is removed through the first hole. The second support layer is etched to form a second hole exposing the first sacrificial layer. The first sacrificial layer is removed through the second hole. The bottom electrode layer is trimmed such that the bottom electrode layer has a second critical dimension between the first support layer and the second support layer that is smaller than the first critical dimension.

Description

Method for forming semiconductor structure

The present disclosure relates to a method of forming a semiconductor structure.

Capacitors can be used in a variety of different semiconductor circuits. For example, capacitors can be used in dynamic random access memory (DRAM) memory circuits or any other type of memory circuit. DRAM memory circuits are manufactured by replicating millions of identical circuit elements (called DRAM cells) on a single semiconductor wafer. A DRAM cell is an addressable location that can store a bit of data (binary digit). In its most common form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor.

However, existing capacitors face numerous challenges due to process limitations. For example, excessively large critical dimensions of the capacitor's lower electrode layer can cause the capacitor to short-circuit. Therefore, improvements to capacitor manufacturing processes and the development of improved semiconductor structures are desired.

The present invention discloses a method for forming a semiconductor structure.

According to some embodiments of the present disclosure, a method for forming a semiconductor structure includes forming a dielectric stack on a conductive layer, wherein the dielectric stack comprises sequentially forming a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer, and a third supporting layer. A bottom electrode layer is formed in the dielectric stack. The second sacrificial layer is removed. The first sacrificial layer is removed. After removing the second sacrificial layer and the first sacrificial layer, the bottom electrode layer is trimmed.

In some embodiments of the present disclosure, the lower electrode layer is trimmed so that the lower electrode layer has a first critical dimension in the first supporting layer, and the lower electrode layer has a second critical dimension between the first supporting layer and the second supporting layer that is smaller than the first critical dimension.

In some embodiments of the present disclosure, the lower electrode layer is trimmed so that the lower electrode layer has a third critical dimension smaller than the first critical dimension between the second supporting layer and the third supporting layer.

In some embodiments of the present disclosure, the second critical size is substantially equal to the third critical size.

In some embodiments of the present disclosure, the lower electrode layer is trimmed so that the lower electrode layer has a fourth critical dimension greater than the second critical dimension in the second supporting layer.

In some embodiments of the present disclosure, the lower electrode layer is trimmed so that the lower electrode layer has a fifth critical dimension that is no greater than the second critical dimension in the third supporting layer.

In some embodiments of the present disclosure, trimming the lower electrode layer is performed by performing a wet etching process.

In some embodiments of the present disclosure, a wet etching process is performed using an alkaline etching solution.

In some embodiments of the present disclosure, the wet etching process time is in the range of 15 seconds to 30 seconds.

In some embodiments of the present disclosure, the method of forming a semiconductor structure further includes forming a high-k dielectric layer along the sidewalls of the lower electrode layer after trimming the lower electrode layer, and forming an upper electrode layer along the sidewalls of the high-k dielectric layer.

According to the above-mentioned embodiments of the present disclosure, by trimming the lower electrode layer, the critical dimension of the lower electrode layer can be controlled or reduced (for example, the second critical dimension of the lower electrode layer between the first supporting layer and the second supporting layer is smaller than the first critical dimension in the first supporting layer), thereby preventing the capacitor from short-circuiting.

It should be understood that both the foregoing general description and the following detailed description are merely exemplary and are intended to provide further explanation of the present disclosure.

The following diagrams illustrate various embodiments of the present disclosure. For the sake of clarity, numerous practical details are included in the following description. However, it should be understood that these practical details should not be construed as limiting the present disclosure. In other words, these practical details are not essential to some embodiments of the present disclosure and, therefore, should not be construed as limiting the present disclosure. Furthermore, to simplify the diagrams, some commonly used structures and components are depicted in simplified schematic form. Furthermore, for ease of viewing, the dimensions of the components in the diagrams are not drawn to scale.

As used herein, "about," "approximately," or "substantially" should generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. The numerical values given herein are approximate, meaning that unless expressly stated, the meaning of the term "about," "approximately," or "substantially" can be inferred.

Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," and the like may be used in some embodiments of the present disclosure to describe the relationship of one element or feature to another element or feature as depicted in the figures. These spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The element may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used in some embodiments of the present disclosure interpreted accordingly.

Figures 1 through 11 illustrate cross-sectional views of various intermediate stages of a method for forming a semiconductor structure according to some embodiments of the present disclosure. Referring to Figure 1 , a dielectric stack DS is formed on a conductive layer 112. Specifically, the conductive layer 112 is first formed on a substrate 110, followed by the dielectric stack DS formed on the conductive layer 112. Forming the dielectric stack DS on the conductive layer 112 includes forming a first supporting layer 120 on the conductive layer 112, forming a first sacrificial layer 130 on the first supporting layer 120, forming a second supporting layer 140 on the first sacrificial layer 130, forming a second sacrificial layer 150 on the second supporting layer 140, and forming a third supporting layer 160 on the second sacrificial layer 150. In other words, the dielectric stack DS includes the first supporting layer 120, the first sacrificial layer 130, the second supporting layer 140, the second sacrificial layer 150, and the third supporting layer 160 formed in sequence.

In some embodiments, conductive layer 112 contacts first support layer 120 of dielectric stack DS. Conductive layer 112 may comprise tungsten (W) or other suitable metals. In some embodiments, substrate 110 includes interconnect structures comprising contacts, transistors, or other similar components. Thus, capacitors (e.g., capacitor Ca in Figures 10 and 11 ) subsequently formed in dielectric stack DS are connected to other components (e.g., transistors) in substrate 110.

In some embodiments, the first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 are arranged from bottom to top and are spaced apart from each other. In some embodiments, the first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 are formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or a similar deposition method. The first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 include a nitride, such as silicon nitride. In some embodiments, the first sacrificial layer 130 and the second sacrificial layer 150 are formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar deposition methods. The first sacrificial layer 130 and the second sacrificial layer 150 comprise an oxide. The first sacrificial layer 130 and the second sacrificial layer 150 can be made of different materials. When forming the first sacrificial layer 130, a dopant is doped into the first sacrificial layer 130. The dopant comprises boron, phosphorus, or a combination thereof. For example, the first sacrificial layer 130 is made of borophospho-silicate glass (BPSG), which is silicon oxide doped with boron and phosphorus. In some embodiments, the second sacrificial layer 150 is made of silane (SiH ₄ ) oxide or other suitable oxide materials.

Referring to FIG. 2 , dielectric stack DS is etched to form opening 170 in dielectric stack DS. Specifically, opening 170 is formed in first supporting layer 120, first sacrificial layer 130, second supporting layer 140, second sacrificial layer 150, and third supporting layer 160. In some embodiments, opening 170 extends from third supporting layer 160 downward to conductive layer 112, exposing conductive layer 112. Opening 170 may expose sidewall DS1 of dielectric stack DS. In some embodiments, etching dielectric stack DS to form opening 170 is performed by performing a dry etching process. For example, dry etching gases such as hydrogen (H ₂ ) and nitrogen (N ₂ ) may be selected for the dry etching process.

Referring to FIG. 2 and FIG. 3 , a conductive material is filled into the opening 170 to form a lower electrode layer 180 in the opening 170 and above the third support layer 160. The lower electrode layer 180 covers the top surface 161 of the third support layer 160 and contacts the sidewall DS1 of the dielectric stack DS and the top surface of the conductive layer 112. In some embodiments, the lower electrode layer 180 is formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a similar deposition method.

In some embodiments, the bottom electrode layer 180 has a first critical dimension W1 within the dielectric stack DS. Specifically, as shown in FIG2 and FIG3 , the opening 170 has a first critical dimension (width) W1 extending parallel to the length of the substrate 110 within the dielectric stack DS. Therefore, the bottom electrode layer 180 also has the first critical dimension W1 within the dielectric stack DS. The bottom electrode layer 180 has the first critical dimension W1 within the first supporting layer 120, the first sacrificial layer 130, the second supporting layer 140, the second sacrificial layer 150, and the third supporting layer 160. That is, the lower electrode layer 180 has substantially the same critical dimensions in the first supporting layer 120, the first sacrificial layer 130, the second supporting layer 140, the second sacrificial layer 150, and the third supporting layer 160. It should be understood that the "critical dimension" of the lower electrode layer 180 in the present disclosure can be interchangeably referred to as the width of the lower electrode layer 180. In some embodiments, the lower electrode layer 180 includes titanium nitride (TiN) or other suitable conductive materials.

Referring to FIG. 4 , the lower electrode layer 180 and the third supporting layer 160 are etched to form a first hole H1 and expose the second sacrificial layer 150. In some embodiments, forming the first hole H1 further includes etching a portion of the second sacrificial layer 150. As a result, the remaining second sacrificial layer 150 has a stepped profile (i.e., an exposed top surface and exposed sidewalls perpendicular to the exposed top surface). In some embodiments, forming the first hole H1 is performed by a dry etching process. The etching gas used to form the first hole H1 may include a gas composed of carbon (C) and fluorine (F), such as carbon tetrafluoride ( _CF4 ).

Referring to Figures 4 and 5 , the second sacrificial layer 150 of the dielectric stack DS is removed through the first hole H1. In some embodiments, an etching process is performed to remove the entire second sacrificial layer 150. For example, the second sacrificial layer 150 is removed using a wet etching process, wherein the etching solution of the wet etching process includes a fluoride-based solution, such as hydrofluoric acid (HF). After the second sacrificial layer 150 is removed, a space S1 is formed between the second supporting layer 140 and the third supporting layer 160.

Referring to Figures 5 and 6 , the second supporting layer 140 is etched to form a second hole H2 in the second supporting layer 140 and expose the first sacrificial layer 130. In some embodiments, forming the second hole H2 further includes etching a portion of the first sacrificial layer 130. As a result, the remaining first sacrificial layer 130 has an inverted U-shaped profile (i.e., an exposed bottom surface and exposed sidewalls connected to the exposed bottom surface). In some embodiments, forming the second hole H2 is performed by a dry etching process. The etching gas used to form the second hole H2 may include a gas composed of carbon (C) and fluorine (F), such as carbon tetrafluoride ( _CF4 ).

In some embodiments, as shown in Figures 5 and 6, after forming the second hole H2 in the second supporting layer 140, the portion of the lower electrode layer 180 located above the third supporting layer 160 is removed. As a result, the top surface 161 of the third supporting layer 160 is exposed, and the top surface 181 of the lower electrode layer 180 is substantially coplanar with the top surface 161 of the third supporting layer 160. In some embodiments, the removal of the portion of the lower electrode layer 180 located above the third supporting layer 160 is performed by a dry etching process. In some embodiments, the removal of the portion of the lower electrode layer 180 located above the third supporting layer 160 and the formation of the second hole H2 are performed using a single dry etching process.

Referring to Figures 6 and 7 , the first sacrificial layer 130 of the dielectric stack DS is removed via the second hole H2. In some embodiments, an etching process is performed to remove the entire first sacrificial layer 130. For example, the first sacrificial layer 130 is removed using a wet etching process, wherein the etching solution of the wet etching process includes a fluoride-based solution, such as hydrofluoric acid (HF). After the first sacrificial layer 130 is removed, a space S2 is formed between the second supporting layer 140 and the first supporting layer 120, and the space S1 and the space S2 are connected via the second hole H2 in the second supporting layer 140. The first supporting layer 120 , the second supporting layer 140 , and the third supporting layer 160 are connected via the bottom electrode layer 180 .

Referring to Figures 6 to 8 , after removing the first sacrificial layer 130, the lower electrode layer 180 is trimmed. Specifically, the lower electrode layer 180 is trimmed to reduce its critical dimension (width) within the dielectric stack DS. A portion 183 of the lower electrode layer 180 between the first support layer 120 and the second support layer 140 has a second critical dimension W2, which is smaller than the first critical dimension W1 of a portion 182 of the lower electrode layer 180 within the first support layer 120. This prevents short circuits in subsequently formed capacitors (e.g., capacitor Ca in Figures 10 and 11 ).

In some embodiments, the lower electrode layer 180 is trimmed so that a portion 186 of the lower electrode layer 180 between the second supporting layer 140 and the third supporting layer 160 has a third critical dimension W3 that is smaller than the first critical dimension W1. In some embodiments, the third critical dimension W3 is substantially equal to the second critical dimension W2. In some other embodiments, the third critical dimension W3 is greater than the second critical dimension W2.

In some embodiments, a portion 185 of the lower electrode layer 180 in the second supporting layer 140 has a fourth critical dimension W4 that is larger than the second critical dimension W2. The fourth critical dimension W4 may be substantially equal to the first critical dimension W1. In some embodiments, a portion 187 of the lower electrode layer 180 contacting the third supporting layer 160 has a fifth critical dimension W5, wherein the fifth critical dimension W5 is not greater than (e.g., smaller than or substantially equal to) the second critical dimension W2 and/or the third critical dimension W3. In some embodiments, portion 189 of lower electrode layer 180 has a minimum critical dimension W6, wherein portion 189 of lower electrode layer 180 is located between portion 187 contacting third supporting layer 160 and portion 186 above second supporting layer 140 .

As shown in FIG. 7 , before trimming the lower electrode layer 180, portions 183 and 186 of the lower electrode layer 180 both have a first critical dimension W1. In the step of FIG. 8 (i.e., trimming the lower electrode layer 180), the critical dimensions of portions 183 and 186 of the lower electrode layer 180 are reduced. Specifically, portion 183 of the lower electrode layer 180 is reduced to have a second critical dimension W2, and portion 186 of the lower electrode layer 180 is reduced to have a third critical dimension W3. Furthermore, in some embodiments, the critical dimensions of portions 187 and 189 of the lower electrode layer 180 are reduced. Thus, by trimming the lower electrode layer 180, the critical dimension of the lower electrode layer 180 can be reduced to prevent short circuits in subsequently formed capacitors (e.g., capacitor Ca in Figures 10 and 11). For example, the second critical dimension W2 and/or the third critical dimension W3 of the lower electrode layer 180 range from approximately 19 nm to approximately 26 nm, while the first critical dimension of the lower electrode layer 180 ranges from approximately 27 nm to approximately 30 nm.

In some embodiments, trimming the lower electrode layer 180 involves performing a wet etching process. The wet etching process may utilize an alkaline etching solution. For example, the alkaline etching solution may include a combination of hydrogen hydroxide, hydrogen peroxide, and water _{(i.e., NH₄OH:H₂O₂ : H₂O} , also known as APM), wherein the ratio of hydrogen hydroxide, hydrogen peroxide, and water may be 1:8:60. In some embodiments, the wet etching process for trimming the lower electrode layer 180 lasts for a time ranging from approximately 15 seconds to approximately 30 seconds. If the wet etching process time is less than 15 seconds, the critical size of the lower electrode layer 180 may be too large, thereby causing a short circuit in the subsequently formed capacitor. If the wet etching process time is greater than 30 seconds, the critical size of the lower electrode layer 180 may be too small, thereby causing the capacitance value of the capacitor to be too low.

Referring to FIG. 9 , after trimming the lower electrode layer 180 , a high-k dielectric layer (high-k dielectric layer) 190 is formed. Specifically, the high-k dielectric layer 190 is formed along the sidewalls 180S of the lower electrode layer 180 . Furthermore, the high-k dielectric layer 190 may be formed along the sidewalls, top, and bottom surfaces of the second support layer 140 , the sidewalls, top, and bottom surfaces of the third support layer 160 , and the top surface of the first support layer 120 . In some embodiments, the high-k dielectric layer 190 is conformally deposited along the sidewalls 180S of the lower electrode layer 180, for example, by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or a similar deposition method. In some embodiments, a lowermost surface 191 of the high-k dielectric layer 190 contacts a surface 180T of the lower electrode layer 180 in the first supporting layer 120 and a top surface of the first supporting layer 120. In other words, the lowermost surface 191 of the high-k dielectric layer 190 at least partially overlaps with a surface 180T of the lower electrode layer 180 in the first supporting layer 120.

In some embodiments, high-k dielectric layer 190 includes ferrite (HfO). In various examples, high-k dielectric layer 190 includes metal oxide (e.g., _HfSiO2 , ZnO, _ZrO2 , _Ta2O5 , _Al2O3 , or _{the like} ), metal nitride, or a combination thereof.

Referring to FIG. 10 , after forming the high-k dielectric layer 190, an upper electrode layer 200 is formed along the sidewalls 193 of the high-k dielectric layer 190. The upper electrode layer 200 is located above the horizontal surface of the high-k dielectric layer 190. Thus, a capacitor Ca comprising the lower electrode layer 180, the high-k dielectric layer 190, and the upper electrode layer 200 is defined within the dielectric stack DS. Because the lower electrode layer 180 is trimmed before forming the high-k dielectric layer 190, the critical dimensions of the lower electrode layer 180 can be reduced, thereby preventing short circuiting of the capacitor Ca. In some embodiments, the top electrode layer 200 is conformally deposited along the sidewalls 193 of the high-k dielectric layer 190 by, for example, atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like.

The top electrode layer 200 may include titanium nitride (TiN) or other suitable conductive materials. In some embodiments, the top electrode layer 200 and the bottom electrode layer 180 include the same material, such as TiN. In some embodiments, the top electrode layer 200 and the bottom electrode layer 180 include different materials, such as the bottom electrode layer 180 including TiSiN and the top electrode layer 200 including TiN.

Referring to Figures 10 and 11 , semiconductor layer 210 is formed in space S1 between first supporting layer 120 and second supporting layer 140, space S2 between second supporting layer 140 and third supporting layer 160, first hole H1 in third supporting layer 160, and second hole H2 in second supporting layer 140. Semiconductor layer 210 may completely fill space S1, space S2, first hole H1, and second hole H2 in dielectric stack DS. Semiconductor layer 210 may also contact and cover upper electrode layer 200 above third supporting layer 160.

In some embodiments, the semiconductor structure includes a plurality of supporting layers (i.e., a first supporting layer 120, a second supporting layer 140, and a third supporting layer 160) and a capacitor Ca. The first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 are arranged from bottom to top and are separated from each other. In other words, the third supporting layer 160 is located on the second supporting layer 140, and the second supporting layer 140 is located on the first supporting layer 120. The capacitor Ca contacts the sidewall 123 of the first supporting layer 120 , the sidewall 143 of the second supporting layer 140 , and the sidewall 163 of the third supporting layer 160 . Capacitor Ca includes a lower electrode layer 180 extending from the first supporting layer 120 to the third supporting layer 160, a high-k dielectric layer 190 along sidewalls 180S of lower electrode layer 180, and an upper electrode layer 200 along sidewalls 193 of high-k dielectric layer 190. Lower electrode layer 180 has a first critical dimension W1 within first supporting layer 120, and lower electrode layer 180 has a second critical dimension W2 between first supporting layer 120 and second supporting layer 140 that is smaller than first critical dimension W1. It should be noted that capacitor Ca in FIG. 11 is illustrative and is not limited to the structure shown in FIG. For example, capacitor Ca includes other layers.

In summary, the second critical dimension W2 of the lower electrode layer 180 of the capacitor Ca in the semiconductor structure disclosed herein between the first supporting layer 120 and the second supporting layer 140 is smaller than the first critical dimension W1 in the first supporting layer 120. This can reduce the critical dimension of the capacitor Ca, thereby preventing the capacitor Ca from short-circuiting.

Although the present disclosure has disclosed the embodiments in detail above, other embodiments are also possible and are not intended to limit the present disclosure. Therefore, the spirit and scope of the appended patent claims should not be limited to the description of the embodiments of the present disclosure.

Anyone skilled in the art may make various changes or substitutions without departing from the spirit and scope of this disclosure. Therefore, all such changes or substitutions should be included in the scope of protection of the patent application attached to this disclosure.

110: Substrate 112: Conductive layer 120: First support layer 123, 143, 163, 180S, 193, DS1: Sidewalls 130: First sacrificial layer 140: Second support layer 150: Second sacrificial layer 160: Third support layer 161, 181: Top surface 170: Opening 180: Lower electrode layer 180T: Surface 182, 183, 185, 186, 187, 189: Portion 190: High-k dielectric layer 191: Lowermost surface 200: Upper electrode layer 210: Semiconductor layer Ca: Capacitor DS: Dielectric stack H1: First hole H2: Second hole S1, S2: Space W1: First critical dimension W2: Second critical dimension W3: Third critical dimension W4: Fourth critical dimension W5: Fifth critical dimension W6: Minimum critical dimension

To facilitate understanding of the above and other objects, features, advantages, and embodiments of the present disclosure, the accompanying drawings are described as follows: Figures 1 through 11 illustrate cross-sectional views of various intermediate stages of a method for forming a semiconductor structure according to some embodiments of the present disclosure.

Domestic Storage Information (Please enter in order by institution, date, and number) None International Storage Information (Please enter in order by country, institution, date, and number) None

110:Substrate

112:Conductive layer

120: First support layer

123, 143, 163, 180S, 193: Sidewall

140: Second support layer

160: The third support layer

180: Lower electrode layer

190: High-k dielectric layer

200: Upper electrode layer

210: Semiconductor layer

Ca:Capacitor

DS: Dielectric Stack

W1: First critical size

W2: Second critical size

Claims (9)

A method for forming a semiconductor structure comprises: forming a dielectric stack on a conductive layer, wherein forming the dielectric stack comprises sequentially forming a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer, and a third supporting layer; forming a lower electrode layer in the dielectric stack; removing the second sacrificial layer; removing the first sacrificial layer; and After removing the second sacrificial layer and the first sacrificial layer, the lower electrode layer is trimmed, wherein the lower electrode layer is trimmed so that the lower electrode layer has a first critical dimension in the first supporting layer and a second critical dimension between the first supporting layer and the second supporting layer that is smaller than the first critical dimension. The method of claim 1, wherein the lower electrode layer is trimmed so that the lower electrode layer has a third critical dimension smaller than the first critical dimension between the second supporting layer and the third supporting layer. The method of claim 2, wherein the second critical size is substantially equal to the third critical size. The method of claim 1, wherein the lower electrode layer is trimmed so that the lower electrode layer has a fourth critical dimension greater than the second critical dimension in the second supporting layer. The method of claim 1, wherein the lower electrode layer is trimmed so that the lower electrode layer has a fifth critical dimension not greater than the second critical dimension in the third supporting layer. The method of claim 1, wherein trimming the lower electrode layer comprises performing a wet etching process. The method of claim 6, wherein the wet etching process is performed using an alkaline etching solution. The method of claim 6, wherein the wet etching process lasts for a period of time in a range of 15 seconds to 30 seconds. The method of claim 1 further comprises: After trimming the lower electrode layer, forming a high-k dielectric layer along a sidewall of the lower electrode layer; and forming an upper electrode layer along a sidewall of the high-k dielectric layer.