TWI841295B - Micro light-emitting diode display system - Google Patents

Abstract

A micro light-emitting diode (uLED) display system includes a driver and a first row of uLED ICs. The driver includes a clock and data recovery (CDR) unit, a frequency division unit and a generation unit. The CDR unit receives a data signal embedded with a clock signal and outputs the clock signal and data signal respectively. The frequency division unit is coupled to the CDR unit and used for receiving the clock signal and outputting a first clock signal and a second clock signal respectively. The generation unit is coupled to the CDR unit and the frequency division unit and used for generating row data signals and shift clock signals according to the data signal, the first clock signal and the second clock signal respectively. The first row of uLED ICs includes multiple uLED ICs connected in series to sequentially transmit the row data signals and shift clock signals.

Description

Micro-luminescent diode display system

The present invention relates to a micro-light emitting diode (uLED), and more particularly to a micro-light emitting diode display system.

Generally speaking, the micro-LED display system includes a plurality of micro-LED integrated circuits, and each column of the micro-LED integrated circuits includes a plurality of micro-LED integrated circuits (uICs) connected in series, and each micro-LED integrated circuit drives a plurality of micro-LEDs (uLEDs).

However, since traditional micro-LED integrated circuits all need to be equipped with a phase-locked loop (PLL) and a large number of wiring is required between adjacent micro-LED integrated circuits and between the micro-LED integrated circuit and the panel, the circuit cost and area required for the traditional micro-LED display system are difficult to reduce, and further solutions are needed.

Therefore, the present invention proposes a micro-luminescent diode display system to effectively solve the above problems encountered by the prior art.

A preferred specific embodiment of the present invention is a micro-luminescent diode display system. In this embodiment, the micro-luminescent diode display system includes a driver and a first row of micro-luminescent diode integrated circuits. The driver includes a clock data recovery unit, a frequency division unit, and a generation unit. The clock data recovery unit receives a data signal embedded with a clock signal and outputs a clock signal and a data signal respectively. The frequency division unit is coupled to the clock and data recovery units to receive the clock signal and output a first clock signal and a second clock signal respectively. The generating unit is coupled to the clock data recovery unit and the frequency dividing unit to generate a row data signal and a shift clock signal according to the data signal, the first clock signal and the second clock signal. The first row micro-LED integrated circuit includes a plurality of micro-LED integrated circuits connected in series to sequentially transmit the row data signal and the shift clock signal.

In one embodiment, the generating unit further generates an enabling signal according to the data signal, the first clock signal and the second clock signal, and the enabling signal is sequentially transmitted by the plurality of micro-LED integrated circuits connected in series.

In one embodiment, the driver further includes a decoding unit and a frequency division unit. The decoding unit is coupled to the clock data recovery unit and the frequency division unit, and is used to decode the data signal and the first clock signal and then output them. The storage unit is coupled between the decoding unit and the generation unit, and is used to store the data signal and the first clock signal for access by the generation unit. The storage unit is a bit frame buffer.

In one embodiment, the driver further includes a control unit and a temporary storage unit. The control unit is coupled to the storage unit to control the read/write operation of the storage unit. The temporary storage unit is coupled to the decoding unit to temporarily store the relevant parameter settings required to generate the column data signal, the second clock signal, the shift clock signal and the enable signal.

In one embodiment, each micro-LED integrated circuit is respectively coupled to a plurality of micro-LEDs and generates a pulse width modulation control signal according to an enable signal, a column data signal and a shift clock signal to control whether the plurality of micro-LEDs emit light.

In one embodiment, if the storage unit includes a first storage area, a second storage area, and a third storage area and the data signal includes a first bit frame, a second bit frame, and a third bit frame, during a first time to a second time, the control unit writes the first bit frame to the first storage area; during a second time to a third time, the control unit writes the second bit frame to the second storage area; during a third time to a fourth time, the control unit writes the third bit frame to the third storage area and reads the third bit frame from the first storage area. The control unit reads the first bit frame from the second storage area and outputs it; during the fourth time to the fifth time, the control unit reads the second bit frame from the second storage area and outputs it; during the fifth time to the sixth time, the control unit reads and outputs the first bit frame from the first storage area; during the sixth time to the seventh time, the control unit reads the third bit frame from the third storage area and outputs it; during the seventh time to the eighth time, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area and outputs it.

In one embodiment, if the storage unit includes a first storage area, a second storage area, and a third storage area and the data signal includes a first bit frame, a second bit frame, and a third bit frame, during the first time to the third time, the control unit writes the first bit frame to the first storage area; during the third time to the fifth time, the control unit writes the second bit frame to the second storage area; during the fifth time to the sixth time, the control unit writes the third bit frame to the third storage area and reads the first bit frame from the first storage area and outputs it; during the sixth time to the seventh time, the control unit continues to write the third bit frame to the third storage area. The control unit writes the third bit frame into the third storage area and reads the second bit frame from the second storage area and outputs it; during the seventh time to the eighth time, the control unit reads and outputs the first bit frame from the first storage area; during the eighth time to the ninth time, the control unit reads the third bit frame from the third storage area and outputs it; during the ninth time to the tenth time, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area and outputs it; during the tenth time to the eleventh time, the control unit continues to write the third bit frame into the third storage area and reads the second bit frame from the second storage area and outputs it.

In one embodiment, if the storage unit includes a first storage area, a second storage area, and a third storage area and the data signal includes a first bit frame, a second bit frame, and a third bit frame, during the first time to the fourth time, the control unit writes the first bit frame to the first storage area; during the fourth time to the seventh time, the control unit writes the second bit frame to the second storage area; during the seventh time to the eighth time, the control unit writes the third bit frame to the third storage area and reads the first bit frame from the first storage area and outputs it; during the eighth time to the ninth time, the control unit continues to write the third bit frame to the third storage area and reads the second bit frame from the second storage area and outputs it; during the ninth time to the tenth time During the period of 10 hours to 11 hours, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area and outputs it; during the period of 10 hours to 11 hours, the control unit reads the third bit frame from the third storage area and outputs it; during the period of 11 hours to 12 hours, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area The first bit frame is read and then output; during the period from the twelfth hour to the thirteenth hour, the control unit continues to write the third bit frame into the third storage area and read the second bit frame from the second storage area and then output; during the period from the thirteenth hour to the fourteenth hour, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area and then output.

In one embodiment, the micro-LED display system further includes a second row of micro-LED integrated circuits, which includes a plurality of micro-LED integrated circuits connected in series to sequentially transmit an enable signal, a row data signal, and a shift clock signal, wherein the rising edge of the enable signal transmitted by the second row of micro-LED integrated circuits is later than the rising edge of the enable signal transmitted by the first row of micro-LED integrated circuits.

In one embodiment, the generating unit further generates a token signal according to the data signal, the first clock signal and the second clock signal, and the token signal is transmitted sequentially by the plurality of micro-LED integrated circuits connected in series.

In one embodiment, the driver further includes a decoding unit and a storage unit. The decoding unit is coupled to the clock data recovery unit and the frequency division unit, and is used to receive the data signal and the first clock signal for decoding and output. The storage unit is coupled between the decoding unit and the generation unit, and is used to store the decoded data signal and the first clock signal for access by the generation unit, and the storage unit is a line buffer.

In one embodiment, the driver further includes a control unit and a temporary storage unit. The control unit is coupled to the storage unit to control the read/write operation of the storage unit. The temporary storage unit is coupled to the decoding unit to temporarily store the relevant parameter settings required to generate the column data signal, the second clock signal, the shift clock signal and the token signal.

In one embodiment, each micro-LED integrated circuit is respectively coupled to a plurality of micro-LEDs and generates a pulse width modulation control signal according to a token signal, a row data signal and a shift clock signal to control the plurality of micro-LEDs to emit light.

Compared to the prior art, the micro-LED display system of the present invention includes a plurality of columns of micro-LED integrated circuits, and each micro-LED integrated circuit connected in series in each column of micro-LED integrated circuits does not need to be provided with a phase-locked loop (PLL), and the number of connections between adjacent micro-LED integrated circuits and the number of connections between the micro-LED integrated circuits and the panel can be reduced, thereby achieving the substantial effect of significantly reducing the overall circuit cost and area of the micro-LED display system.

The present invention discloses a micro-luminescent diode display system, which at least includes a driver and a first row of micro-luminescent diode integrated circuits. The driver at least includes a clock data recovery unit, a frequency division unit and a generation unit. The first row of micro-luminescent diode integrated circuits includes a plurality of micro-luminescent diode integrated circuits connected in series. The clock data recovery unit receives a data signal embedded with a clock signal and outputs a clock signal and a data signal respectively. The frequency division unit is coupled to the clock and data recovery unit to receive the clock signal and output a first clock signal and a second clock signal respectively. The generating unit is coupled to the clock data recovery unit and the frequency dividing unit, and is used to generate a column data signal and a shift clock signal according to the data signal, the first clock signal and the second clock signal. The plurality of micro-LED integrated circuits connected in series are used to sequentially transmit the column data signal and the shift clock signal.

Next, the micro-luminescent diode display system of the present invention will be described in detail with the following different specific embodiments.

According to the first preferred embodiment of the present invention, there is a micro-LED display system. Please refer to FIG1 and FIG2, which respectively show a driver of the LED display system and a first row of micro-LED integrated circuits in the first preferred embodiment of the present invention.

As shown in FIG1 , the driver DR of the LED display system includes a clock data recovery unit CDR, a frequency division unit DIV, a decoding unit DEC, a temporary storage unit REG, a storage unit SRAM (BFB), a control unit CON, and a generation unit GEN. The clock data recovery unit CDR is coupled to the frequency division unit DIV and the decoding unit DEC respectively. The decoding unit DEC is coupled to the temporary storage unit REG and the storage unit SRAM (BFB) respectively. The control unit CON is coupled to the storage unit SRAM (BFB). The storage unit SRAM (BFB) is coupled to the generation unit GEN.

The clock data recovery unit CDR receives the data signal DAT embedded with the clock signal CLK and outputs the clock signal CLK and the data signal DAT respectively. The frequency division unit DIV is used to receive the clock signal CLK and output the first clock signal DCLK and the second clock signal GCLK respectively. The decoding unit DEC is used to decode the data signal DAT and the first clock signal DCLK and then output them. The temporary storage unit REG is used to temporarily store the relevant parameter settings required for generating the column data signal CD, the second clock signal GCLK, the shift clock signal SC and the enable signal EN. The storage unit SRAM (BFB) is used to store the data signal DAT and the first clock signal DCLK for access by the generation unit GEN. The storage unit SRAM (BFB) is a bit-frame buffer. The control unit CON is used to control the read/write operation of the storage unit SRAM (BFB). The generation unit GEN is used to generate an enable signal EN, a column data signal CD and a shift clock signal SC according to the data signal DAT, the first clock signal DCLK and the second clock signal GCLK.

As shown in FIG. 2 , the first row of micro-LED integrated circuits of the LED display system includes a plurality of micro-LED integrated circuits uICs connected in series to sequentially transmit the enable signal EN, the row data signal CD and the shift clock signal SC provided by the generation unit GEN of the driver DR through the mechanism of token-in TKI and token-out TKO, but not limited thereto.

In practical applications, each micro-LED integrated circuit uIC is coupled to a plurality of micro-LEDs (uLEDs) and can generate a pulse width modulation control signal (PWM) according to an enable signal EN, a column data signal CD and a shift clock signal SC to control whether the plurality of micro-LEDs emit light.

Please refer to FIG3 , which shows a schematic diagram of the micro-LED integrated circuit in FIG2 . As shown in FIG3 , the micro-LED integrated circuit uIC includes a shift register and token controller SRTC, a clock unit CL, an inverter/buffer/D-type flip-flop IBD, a data unit DU, a register setter RS, a register ST, a pulse width modulation controller PWMC, an LED current source CS, and a bias unit BS. The shift register and token controller SRTC are coupled to the clock unit CL, the data unit DU, and the register setter RS, respectively. The data unit DU is coupled to the register ST. The register ST is coupled to the pulse width modulation controller PWMC. The pulse width modulation controller PWMC is coupled to the LED current source CS. The bias unit BS is coupled to the LED current source CS.

The shift register and token controller SRTC receives the enable signal EN and the column data signal CD from the driver DR and outputs the token signal TK. The clock unit CL receives the shift clock signal SC from the driver DR and outputs the clock signal CLK to all blocks. The inverter/buffer/D-type flip-flop IBD receives the column data signal CD and the shift clock signal SC from the driver DR and outputs the column data signal CD and the shift clock signal SC. The shift register and token controller SRTC also outputs the RGB data signal to the data unit DU. The data unit DU outputs the RGB data signal to the register ST for storage. The pulse width modulation controller PWMC generates a pulse width modulation signal PWM to the LED current source CS according to the RGB data signal stored in the register ST. The LED current source CS generates n LED currents I1~In according to the pulse width modulation signal PWM and the bias provided by the bias unit BS to make the n uLEDs emit light.

Please refer to FIG. 4 to FIG. 8 , which respectively illustrate timing diagrams of the control unit of the driver controlling the storage unit to read/write column data signals in different embodiments.

As shown in FIG. 4 , if the storage unit SRAM (BFB) includes a first storage area SRAM0, a second storage area SRAM1, and a third storage area SRAM2 and the input data signal DAT includes a setting signal SET, a first bit frame BF0, a second bit frame BF1, a third bit frame BF2, and a horizontal synchronization signal LSYNC, during the period from the zeroth time t0 to the first time t1, the input data signal DAT is the setting signal SET; during the period from the first time t1 to the second time t2, the input data signal DAT is the first bit frame BF0, and the control unit CON writes the first bit frame BF0 into the first storage area SRAM0; during the period from the second time t2 to the third time t3, the input data signal DAT is the second bit frame BF1, and the control unit CON writes the first bit frame BF0 into the first storage area SRAM0; The control unit CON writes the second bit frame BF1 into the second storage area SRAM1; during the third time t3 to the fourth time t4, the input data signal DAT is the third bit frame BF2, the control unit CON writes the third bit frame BF2 into the third storage area SRAM2 and reads the first bit frame BF0 from the first storage area SRAM0 and then outputs it, so the output data signal DAT is the first bit frame BF0, that is, the zeroth subframe SF0; during the fourth time t4 to the fifth time t5, the input data signal DAT is the horizontal synchronization signal LSYNC, the control unit CON reads the second bit frame BF1 from the second storage area SRAM1 and then outputs it, so the output data signal DAT is the second bit frame BF1, that is, the first subframe SF1; during the fifth time t5 During the period from t5 to the sixth time t6, the input data signal DAT is the horizontal synchronization signal LSYNC, and the control unit CON reads the first bit frame BF0 from the first storage area SRAM0 and outputs it, so the output data signal DAT is the first bit frame BF0, that is, the second sub-frame SF2; during the period from the sixth time t6 to the seventh time t7, the control unit CON reads the third bit frame BF2 from the third storage area SRAM2 and outputs it, so the output data signal DAT is the third bit frame BF2, that is, the third sub-frame SF3; during the period from the seventh time t7 to the eighth time t8, the input data signal DAT is the third bit frame BF2, and the control unit CON writes the third bit frame BF2 into the third storage area SRAM2 and reads the third bit frame BF2 from the first storage area SRAM0. The first bit frame BF0 is taken and then outputted, so the output data signal DAT is the first bit frame BF0, that is, the fourth sub-frame SF4; during the eighth time t8 to the ninth time t9, the input data signal DAT is the horizontal synchronization signal LSYNC, the control unit CON reads the second bit frame BF1 from the second storage area SRAM1 and then outputs it, so the output data signal DAT is the second bit frame BF1, that is, the fifth sub-frame SF5; during the ninth time t9 to the tenth time t10, the input data signal DAT is the horizontal synchronization signal LSYNC, the control unit CON reads the first bit frame BF0 from the first storage area SRAM0 and then outputs it, so the output data signal DAT is the first bit frame BF0, that is, the sixth sub-frame SF6, and the rest can be deduced accordingly.

As shown in FIG5 , if the storage unit SRAM (BFB) includes a first storage area SRAM0, a second storage area SRAM1, and a third storage area SRAM2 and the input data signal DAT includes a setting signal SET, a first bit frame BF0, a second bit frame BF1, a third bit frame BF2, and a horizontal synchronization signal LSYNC, during the period from the zeroth time t0 to the first time t1, the input data signal DAT is the setting signal SET; during the period from the first time t1 to the second time t2, the input data signal DAT is the first bit frame BF0, and the control unit CON writes the first bit frame BF0 into the first storage area SRAM0; during the period from the second time t2 to the third time t3, the input data signal DAT is the second bit frame BF1, and the control unit CON writes the first bit frame BF0 into the first storage area SRAM0; The control unit CON writes the second bit frame BF1 into the second storage area SRAM1; during the third time t3 to the fourth time t4, the input data signal DAT is the third bit frame BF2, the control unit CON writes the third bit frame BF2 into the third storage area SRAM2 and reads the first bit frame BF0 from the first storage area SRAM0 and then outputs it, so the output data signal DAT is the first bit frame BF0, that is, the zeroth subframe SF0; during the fourth time t4 to the fifth time t5, the input data signal DAT is the horizontal synchronization signal LSYNC, the control unit CON reads the second bit frame BF1 from the second storage area SRAM1 and then outputs it, so the output data signal DAT is the second bit frame BF1, that is, the first subframe SF1; during the fifth time t5 During the period from t5 to the sixth time t6, the input data signal DAT is the horizontal synchronization signal LSYNC, and the control unit CON reads the first bit frame BF0 from the first storage area SRAM0 and outputs it, so the output data signal DAT is the first bit frame BF0, that is, the second sub-frame SF2; during the period from the sixth time t6 to the seventh time t7, the control unit CON reads the third bit frame BF2 from the third storage area SRAM2 and outputs it, so the output data signal DAT is the third bit frame BF2, that is, the third sub-frame SF3; during the period from the seventh time t7 to the eighth time t8, the input data signal DAT is the third bit frame BF2, and the control unit CON writes the third bit frame BF2 into the third storage area SRAM2 and reads the third bit frame BF2 from the first storage area SRAM0. The first bit frame BF0 is taken and then outputted, so the output data signal DAT is the first bit frame BF0, that is, the fourth sub-frame SF4; during the eighth time t8 to the ninth time t9, the input data signal DAT is the horizontal synchronization signal LSYNC, the control unit CON reads the second bit frame BF1 from the second storage area SRAM1 and then outputs it, so the output data signal DAT is the second bit frame BF1, that is, the fifth sub-frame SF5; during the ninth time t9 to the tenth time t10, the input data signal DAT is the horizontal synchronization signal LSYNC, the control unit CON reads the first bit frame BF0 from the first storage area SRAM0 and then outputs it, so the output data signal DAT is the first bit frame BF0, that is, the sixth sub-frame SF6, and the rest can be deduced accordingly.

As shown in FIG6 , if the storage unit SRAM (BFB) includes a first storage area SRAM0 and a second storage area SRAM1 and the input data signal DAT includes a setting signal SET, a first bit frame BF0 and a second bit frame BF1, during the period from the zeroth time t0 to the first time t1, the input data signal DAT is the setting signal SET; during the period from the first time t1 to the second time t2, the input data signal DAT is the first bit frame BF0, and the control unit CON sets the first bit frame BF1 to the setting signal SET. 0 is written into the first storage area SRAM0; during the second time t2 to the third time t3, the input data signal DAT is the second bit frame BF1, the control unit CON writes the second bit frame BF1 into the second storage area SRAM1 and reads the first bit frame BF0 from the first storage area SRAM0 and then outputs it, so the output data signal DAT is the first bit frame BF0, that is, the zeroth subframe SF0; during the third time t3 to the fourth time t4, the input data signal DAT is the first bit frame BF0, the control unit CON writes the first bit frame BF0 into the first storage area SRAM0 and reads the second bit frame BF1 from the second storage area SRAM1 and then outputs it, so the output data signal DAT is the second bit frame BF1, that is, the first subframe SF1; during the fourth time t4 to the fifth time t5, the input data signal DAT is the second bit frame BF1, the control unit CON writes the second bit frame BF1 into the second storage area SRAM1 and reads the first subframe SF1 from the first storage area SRAM0 The data signal DAT is output after the first bit frame BF0, so the output data signal DAT is the first bit frame BF0, that is, the second sub-frame SF2; during the fifth time t5 to the sixth time t6, the input data signal DAT is the first bit frame BF0, the control unit CON writes the first bit frame BF0 to the first storage area SRAM0 and reads the second bit frame BF1 from the second storage area SRAM1 and then outputs it, so the output data signal DAT is the second bit frame BF1, that is, the third sub-frame SF3, and the rest can be deduced accordingly.

As shown in FIG7 , if the storage unit SRAM (BFB) includes a first storage area SRAM0, a second storage area SRAM1, and a third storage area SRAM2 and the input data signal DAT includes a setting signal SET, a first bit frame BF0, a second bit frame BF1, a third bit frame BF2, and a horizontal synchronization signal LSYNC, during a period from the zeroth time t0 to the first time t1, the input data signal DAT is the setting signal SET; during a period from the first time t1 to the third time t3, the input data signal DAT is the first bit frame BF0, and the control unit CON writes the first bit frame BF0 into the first storage area SRAM0; during a period from the third time t3 to the fifth time t5, the input data signal DAT is the second bit frame BF1, and the control unit CON writes the second bit frame BF1 into the second storage area SRAM1; during the fifth time t5 to the sixth time t6, the input data signal DAT is the third bit frame BF2, the control unit CON writes the third bit frame BF2 to the third storage area SRAM2 and reads the first bit frame BF0 from the first storage area SRAM0 and then outputs it, so the output data signal DAT is the first bit frame BF0, that is, the zeroth subframe SF0; at the sixth time t During the period from the seventh time t6 to the seventh time t7, the input data signal DAT is the third bit frame BF2, the control unit CON continues to write the third bit frame BF2 into the third storage area SRAM2 and reads the second bit frame BF1 from the second storage area SRAM1 and then outputs it, so the output data signal DAT is the second bit frame BF1, that is, the first subframe SF1; during the period from the seventh time t7 to the eighth time t8, the input data signal DAT is the third bit frame BF2, the control unit CON continues to write the third bit frame BF2 into the third storage area SRAM2 and reads the second bit frame BF1 from the second storage area SRAM1 and then outputs it, so the output data signal DAT is the second bit frame BF1, that is, the first subframe SF1; during the period from the seventh time t7 to the eighth time t8, the input The data signal DAT is the horizontal synchronization signal LSYNC, and the control unit CON reads the first bit frame BF0 from the first storage area SRAM0 and outputs it. Therefore, the output data signal DAT is the first bit frame BF0, that is, the second subframe SF2. During the eighth time t8 to the ninth time t9, the input data signal DAT is the horizontal synchronization signal LSYNC, and the control unit CON reads the first bit frame BF0 from the third storage area SRAM0 and outputs it. Therefore, the output data signal DAT is the first bit frame BF0, that is, the second subframe SF2. RAM2 reads the third bit frame BF2 and then outputs it, so the output data signal DAT is the third bit frame BF2, that is, the third subframe SF3; during the ninth time t9 to the tenth time t10, the input data signal DAT is the third bit frame BF2, the control unit CON writes the third bit frame BF2 to the third storage area SRAM2 and reads the first bit frame BF0 from the first storage area SRAM0. The output data signal DAT is the first bit frame BF0, i.e., the fourth subframe SF4. During the tenth time t10 to the eleventh time t11, the input data signal DAT is the third bit frame BF2. The control unit CON continues to write the third bit frame BF2 into the third storage area SRAM2 and reads the second bit frame BF1 from the second storage area SRAM1 and then outputs it. Therefore, the output data signal DAT is the first bit frame BF0, i.e., the fourth subframe SF4. During the tenth time t10 to the eleventh time t11, the input data signal DAT is the third bit frame BF2. The control unit CON continues to write the third bit frame BF2 into the third storage area SRAM2 and reads the second bit frame BF1 from the second storage area SRAM1 and then outputs it. The data signal DAT is the second bit frame BF1, that is, the fifth subframe SF5; during the eleventh time t11 to the twelfth time t12, the input data signal DAT is the horizontal synchronization signal LSYNC, and the control unit CON reads the first bit frame BF0 from the first storage area SRAM0 and outputs it, so the output data signal DAT is the first bit frame BF0, that is, the sixth subframe SF6, and the rest can be deduced accordingly.

As shown in FIG8 , if the storage unit SRAM (BFB) includes a first storage area SRAM0, a second storage area SRAM1, and a third storage area SRAM2 and the input data signal DAT includes a setting signal SET, a first bit frame BF0, a second bit frame BF1, and a third bit frame BF2, during the period from the zeroth time t0 to the first time t1, the input data signal DAT is the setting signal SET; during the period from the first time t1 to the fourth time t4, the input data signal DAT is the first bit frame BF0, and the control unit CON sets the first bit frame to BF0 is written into the first storage area SRAM0; during the period from the fourth time t4 to the seventh time t7, the control unit CON writes the second bit frame BF1 into the second storage area SRAM1; during the period from the seventh time t7 to the eighth time t8, the control unit CON writes the third bit frame BF2 into the third storage area SRAM2 and reads the first bit frame BF0 from the first storage area SRAM0 and outputs it; during the period from the eighth time t8 to the ninth time t9, the control unit CON continues to write the third bit frame BF2 into the third storage area SRAM2 and reads the first bit frame BF0 from the second storage area SRAM0. The storage area SRAM1 reads the second bit frame BF1 and outputs it; during the ninth time t9 to the tenth time t10, the control unit CON writes the third bit frame BF2 into the third storage area SRAM2 and reads the first bit frame BF0 from the first storage area SRAM0 and outputs it; during the tenth time t10 to the eleventh time t11, the control unit CON reads the third bit frame BF2 from the third storage area SRAM2 and outputs it; during the eleventh time t11 to the twelfth time t12, the control unit CON writes the third bit frame BF2 into the first storage area SRAM0 and outputs it; The control unit CON writes the third bit frame BF2 into the third storage area SRAM2 and reads the first bit frame BF0 from the first storage area SRAM0 and outputs it; during the twelfth time t12 to the thirteenth time t13, the control unit CON continues to write the third bit frame BF2 into the third storage area SRAM2 and reads the second bit frame BF1 from the second storage area SRAM1 and outputs it; during the thirteenth time t13 to the fourteenth time t14, the control unit CON writes the third bit frame BF2 into the third storage area SRAM2 and reads the first bit frame BF0 from the first storage area SRAM0 and outputs it.

Please refer to FIG. 9, which shows a timing diagram of an enable signal, a row data signal, and a shift clock signal of a single row of micro-LED integrated circuits. As shown in FIG. 9, the nth subframe SFn includes shift setting SS0, shift data SD0, shift setting SS1, shift data SD1, ..., shift setting SSm-1, shift data SDm-1, and dummy data DM in sequence. The row data signal CD corresponding to the shift settings SS0, SS1, ..., SSm-1 is a plurality of setting values S[0], S[1], ... in sequence. The row data signal CD corresponding to the shift data SD0, SD1, ..., SDm-1 is a plurality of data D0, D1, ... in sequence. The enable signal EN maintains a high level until the shift data SDm-1 changes to a low level. Each pulse of the shift clock signal SC corresponds to a plurality of setting values S[0], S[1], ... and a plurality of data D0, D1, ...

Please refer to FIG. 10 , which shows a timing diagram of an enable signal, a row data signal, and a shift clock signal of a plurality of rows of micro-LED integrated circuits. As shown in FIG. 10 , for the first row of micro-LED integrated circuits, the nth subframe SFn includes shift setting SS0, shift data SD0, shift setting SS1, shift data SD1, …, shift setting SSm-1, shift data SDm-1, and dummy data DM in sequence. The row data signals CD corresponding to the shift settings SS0, SS1, …, SSm-1 are respectively a plurality of setting values S[0], S[1], …. The row data signals CD corresponding to the shift data SD0, SD1, …, SDm-1 are respectively a plurality of data D0, D1, …. Similarly, the n+1th subframe SFn includes shift setting SS0, shift data SD0, shift setting SS1, shift data SD1, ..., shift setting SSm-1, shift data SDm-1 and dummy data DM in sequence. The row data signals CD corresponding to the shift settings SS0, SS1, ..., SSm-1 are a plurality of setting values S[0], S[1], ... in sequence. The row data signals CD corresponding to the shift data SD0, SD1, ..., SDm-1 are a plurality of data D0, D1, ... in sequence. The enable signal EN maintains a high level from the shift setting SS0 until the shift data SDm-1 changes to a low level. The period during which the enable signal EN maintains a high level includes a shift enable period SEP and an LED start enable period ONEP in sequence. Each pulse of the shift clock signal SC corresponds to a plurality of setting values S[0], S[1], ... and a plurality of data D0, D1, ...

Next, for the second row of micro-LED integrated circuits, the shift setting SS0 and the shift data SD0 correspond to the row data signal CD that maintains 0 or 1. The enable signal EN maintains a high level in the shift setting SS0 and maintains a low level in the shift data SD0. The row data signal CD corresponding to the shift settings SS1, ..., SSm-1 are respectively a plurality of setting values S[0], S[1], ... in sequence. The row data signal CD corresponding to the shift data SD1, ..., SDm-1 are respectively a plurality of data D0, D1, ... in sequence. The enable signal EN maintains a high level from the shift setting SS1 until the shift setting SS0 of the next subframe becomes a low level. The period during which the enable signal EN maintains a high level includes the shift enable period SEP and the LED start enable period ONEP in sequence. It should be noted that the rising edge of the enable signal EN sent by the second row of micro-LED integrated circuits is later than the rising edge of the enable signal EN sent by the first row of micro-LED integrated circuits.

The rest can be deduced in this way until the last n-th row of micro-LED integrated circuits, whose enable signal EN maintains a high level from the shift setting SSm-1 until the shift data SD1 of the next subframe changes to a low level. In this embodiment, the period during which the enable signal EN maintains a high level can include the shift enable period SEP and the LED start enable period ONEP in sequence, but is not limited thereto.

The second preferred embodiment of the present invention is also a micro-LED display system. Please refer to Figures 11 and 12, which respectively show the driver of the LED display system and the first row of micro-LED integrated circuits in the second preferred embodiment of the present invention.

As shown in FIG11 , the driver DR of the LED display system includes a clock data recovery unit CDR, a frequency division unit DIV, a decoding unit DEC, a temporary storage unit REG, a storage unit SRAM (LB), a control unit CON, and a generation unit GEN. The clock data recovery unit CDR is coupled to the frequency division unit DIV and the decoding unit DEC respectively. The decoding unit DEC is coupled to the temporary storage unit REG and the storage unit SRAM (LB) respectively. The control unit CON is coupled to the storage unit SRAM (LB). The storage unit SRAM (LB) is coupled to the generation unit GEN.

The clock data recovery unit CDR receives the data signal DAT embedded with the clock signal CLK and outputs the clock signal CLK and the data signal DAT respectively. The frequency division unit DIV is used to receive the clock signal CLK and output the first clock signal DCLK and the second clock signal GCLK respectively. The decoding unit DEC is used to decode the data signal DAT and the first clock signal DCLK and then output them. The temporary storage unit REG is used to temporarily store the relevant parameter settings required for generating the column data signal CD, the second clock signal GCLK, the shift clock signal SC and the enable signal EN. The storage unit SRAM (LB) is used to store the data signal DAT and the first clock signal DCLK for access by the generation unit GEN. The storage unit SRAM (LB) is a line buffer. The control unit CON is used to control the read/write operation of the storage unit SRAM (LB). The generation unit GEN is used to generate a token signal TK, a column data signal CD and a shift clock signal SC according to a data signal DAT, a first clock signal DCLK and a second clock signal GCLK.

As shown in FIG12 , the first row of micro-LED integrated circuits of the LED display system includes a plurality of micro-LED integrated circuits uICs connected in series to sequentially transmit the token signal TK, the row data signal CD and the shift clock signal SC provided by the generation unit GEN of the driver DR through the mechanism of token-in TKI and token-out TKO, but is not limited thereto.

Please refer to FIG. 13 , which is a schematic diagram of the micro-LED integrated circuit in FIG. 12 . As shown in FIG. 13 , the micro-LED integrated circuit uIC includes a shift register and token controller SRTC, a clock unit CL, an inverter/buffer/D-type flip-flop IBD, a data unit DU, a register setter RS, a register ST, a pulse width modulation controller PWMC, an LED current source CS, and a bias unit BS. The shift register and token controller SRTC are coupled to the clock unit CL, the data unit DU, and the register setter RS, respectively. The data unit DU is coupled to the register ST. The register ST is coupled to the pulse width modulation controller PWMC. The pulse width modulation controller PWMC is coupled to the LED current source CS. The bias unit BS is coupled to the LED current source CS.

The shift register and token controller SRTC receives the token signal TK and the column data signal CD from the driver DR and outputs the token signal TK. The clock unit CL receives the shift clock signal SC from the driver DR and outputs the clock signal CLK to all blocks. The inverter/buffer/D-type flip-flop IBD receives the column data signal CD and the shift clock signal SC from the driver DR and outputs the column data signal CD and the shift clock signal SC. The shift register and token controller SRTC also outputs the RGB data signal to the data unit DU. The data unit DU outputs the RGB data signal to the register ST for storage. The pulse width modulation controller PWMC generates a pulse width modulation signal PWM to the LED current source CS according to the RGB data signal stored in the register ST. The LED current source CS generates n LED currents I1~In according to the pulse width modulation signal PWM and the bias provided by the bias unit BS to make the n LEDs emit light.

Please refer to Figure 14, which shows a timing diagram of the token signal, row data signal and shift clock signal of a single row of micro-LED integrated circuits and the operating state of each micro-LED integrated circuit. As shown in Figure 14, the nth frame starts from the zeroth time t0 and ends at the twentieth time t20. The row data signal CD includes the register setting RS and the RGB data DRGB, wherein the period from the first time t1 to the third time t3, the period from the fifth time t5 to the seventh time t7, the period from the ninth time t9 to the eleventh time t11, and the period from the fifteenth time t15 to the seventeenth time t17 are the register setting RS, and the period from the third time t3 to the fifth time t5, the period from the seventh time t7 to the ninth time t9, the period from the eleventh time t11 to the twelfth time t12, and the period from the seventeenth time t17 to the eighteenth time t18 are the RGB data DRGB. The shift clock signal SC is a periodic pulse signal. The token signal TK is maintained at a high level only during the period from the first time t1 to the time t2', and is maintained at a low level for the rest of the time.

During the nth frame (zeroth time t0 to twentieth time t20), assuming that the column of micro-LED integrated circuits includes n micro-LED integrated circuits uIC1~uICn, with respect to the micro-LED integrated circuit uIC1, it is in the idle IDLE operating state during the zeroth time t0 to the second time t2, it is in the shift data SD operating state during the second time t2 to the sixth time t6, and it is in the pulse width modulation generator PWMG generating the nth frame operating state during the sixth time t6 to the twentieth time t20.

Next, with respect to the micro-luminescent diode integrated circuit uIC2, during the period from the zeroth time t0 to the fourth time t4, the pulse width modulation generator PWMG generates the operating state of the n-1th frame, during the period from the fourth time t4 to the sixth time t6, it is the idle operating state IDLE, during the period from the sixth time t6 to the tenth time t10, it is the operating state of the shift data SD, and during the period from the tenth time t10 to the twentieth time t20, the pulse width modulation generator PWMG generates the operating state of the nth frame.

The rest can be deduced in this way until the last micro-LED integrated circuit uICn, which is the pulse width modulation generator PWMG generating the n-1th frame operation state during the zeroth time t0 to the fourteenth time t14, the idle IDLE operation state during the fourteenth time t14 to the sixteenth time t16, the shift data SD operation state during the sixteenth time t16 to the nineteenth time t19, and the pulse width modulation generator PWMG generating the nth frame operation state during the nineteenth time t19 to the twentieth time t20.

Please refer to FIG. 15 , which shows a timing diagram of a token signal, a row data signal, and a shift clock signal of a plurality of rows of micro-LED integrated circuits. As shown in FIG. 15 , for the first row of micro-LED integrated circuits, the nth subframe SFn includes shift setting SS0, shift data SD0, shift setting SS1, shift data SD1, …, shift setting SSm-1, shift data SDm-1, and dummy data DM in sequence. The row data signal CD corresponding to the shift settings SS0, SS1, …, SSm-1 is a plurality of setting values S[0], S[1], … in sequence. The row data signal CD corresponding to the shift data SD0, SD1, …, SDm-1 is a plurality of data D0, D1, … in sequence. Similarly, the n+1th subframe SFn includes shift setting SS0, shift data SD0, shift setting SS1, shift data SD1, ..., shift setting SSm-1, shift data SDm-1 and dummy data DM in sequence. The row data signal CD corresponding to the shift settings SS0, SS1, ..., SSm-1 is a plurality of setting values S[0], S[1], ... in sequence. The row data signal CD corresponding to the shift data SD0, SD1, ..., SDm-1 is a plurality of data D0, D1, ... in sequence. During the nth subframe SFn, the token signal TK maintains a high level only when the setting value S[0] of the shift setting SS0 is set, and maintains a low level at the rest of the time. Each pulse of the shift clock signal SC corresponds to a plurality of setting values S[0], S[1], ... and a plurality of data D0, D1, ...

Next, for the second row of micro-LED integrated circuits, the shift setting SS0 and the shift data SD0 correspond to the row data signal CD that maintains 0 or 1. The row data signal CD corresponding to the shift settings SS1, ..., SSm-1 are sequentially a plurality of setting values S[0], S[1], .... The row data signal CD corresponding to the shift data SD1, ..., SDm-1 are sequentially a plurality of data D0, D1, .... During the n-th subframe SFn, the token signal TK maintains a high level only when the setting value S[0] of the shift setting SS1 is maintained, and maintains a low level at the rest of the time. It should be noted that the rising edge of the token signal TK transmitted by the second row of micro-LED integrated circuits is later than the rising edge of the token signal TK transmitted by the first row of micro-LED integrated circuits.

The rest can be deduced in this way until the last n-th row of micro-LED integrated circuits. During the n-th subframe SFn, the token signal TK maintains a high level only when the setting value S[0] of the shift setting SSm-1 is maintained, and maintains a low level for the rest of the time.

The third preferred embodiment of the present invention is also a micro-LED display system. Please refer to Figures 16 and 17, which respectively show the driver of the LED display system and the first row of micro-LED integrated circuits in the third preferred embodiment of the present invention.

As shown in FIG16 , the driver DR of the LED display system includes a clock data recovery unit CDR, a frequency division unit DIV, a decoding unit DEC, a temporary storage unit REG, a storage unit SRAM (LB), a control unit CON, an encoding unit ENC and a generation unit GEN. The clock data recovery unit CDR is coupled to the frequency division unit DIV and the decoding unit DEC respectively. The decoding unit DEC is coupled to the temporary storage unit REG and the storage unit SRAM (LB) respectively. The control unit CON is coupled to the storage unit SRAM (LB). The storage unit SRAM (LB) is coupled to the encoding unit ENC. The encoding unit ENC is coupled to the generation unit GEN.

The clock data recovery unit CDR receives the data signal DAT embedded with the clock signal CLK and outputs the clock signal CLK and the data signal DAT respectively. The frequency division unit DIV is used to receive the clock signal CLK and output the first clock signal DCLK and the second clock signal GCLK respectively. The decoding unit DEC is used to decode the data signal DAT and the first clock signal DCLK and then output them. The temporary storage unit REG is used to temporarily store the relevant parameter settings required to generate the column data signal CD, the second clock signal GCLK, the shift clock signal SC and the enable signal EN. The storage unit SRAM (LB) is used to store the data signal DAT and the first clock signal DCLK for access by the encoding unit ENC. The storage unit SRAM (LB) is a line buffer. The control unit CON is used to control the read/write operation of the storage unit SRAM (LB). After the encoding unit ENC encodes the data signal DAT and the first clock signal DCLK, the generation unit GEN generates the column data signal CD and the shift clock signal SC according to the data signal DAT, the first clock signal DCLK and the second clock signal GCLK.

As shown in FIG17 , the first row of micro-LED integrated circuits of the LED display system includes a plurality of micro-LED integrated circuits uICs connected in series to sequentially transmit the row data signal CD and shift clock signal SC provided by the generation unit GEN of the driver DR and the token signal TK received from the outside through the mechanism of token-in TKI and token-out TKO, but not limited to this.

Please refer to FIG. 18 , which shows a schematic diagram of the micro-LED integrated circuit in FIG. 17 . As shown in FIG. 18 , the micro-LED integrated circuit uIC includes a decoder, a bit alignment, a shift buffer and a token controller DBST, a clock unit CL, an inverter/buffer/D-type flip-flop IBD, a data unit DU, a buffer setter RS, a register ST, a pulse width modulation controller PWMC, an LED current source CS and a bias unit BS. The decoder, the bit alignment, the shift buffer and the token controller DBST are coupled to the clock unit CL, the data unit DU and the buffer setter RS respectively. The data unit DU is coupled to the register ST. The register ST is coupled to the pulse width modulation controller PWMC. The pulse width modulation controller PWMC is coupled to the LED current source CS. The bias unit BS is coupled to the LED current source CS.

The decoder, bit alignment, shift buffer and token controller DBST receives the token signal TK and the column data signal CD from the driver DR and outputs the token signal TK. The clock unit CL receives the shift clock signal SC from the driver DR and outputs the clock signal CLK to all blocks. The inverter/buffer/D-type flip-flop IBD receives the column data signal CD and the shift clock signal SC from the driver DR and outputs the column data signal CD and the shift clock signal SC. The decoder, bit alignment, shift buffer and token controller DBST also outputs the RGB data signal to the data unit DU. The data unit DU outputs the RGB data signal to the register ST for storage. The pulse width modulation controller PWMC generates a pulse width modulation signal PWM to the LED current source CS according to the RGB data signal stored in the register ST. The LED current source CS generates n LED currents I1~In according to the pulse width modulation signal PWM and the bias provided by the bias unit BS to make the n LEDs emit light.

Please refer to Figure 19, which shows a timing diagram of the enable signal, row data signal and shift clock signal of a single row of micro-LED integrated circuits and the operating state of each micro-LED integrated circuit. As shown in Figure 19, the nth frame starts from the zeroth time t0 and ends at the twenty-second time t22. The row data signal CD includes a start code EC, a register setting RS and RGB data DRGB, wherein the period from the 0th time t0 to the first time t1 and the period from the 18th time t18 to the 20th time t20 are the start code EC, the period from the 1st time t1 to the third time t3, the period from the 5th time t5 to the 7th time t7, the period from the 9th time t9 to the 11th time t11 and the period from the 15th time t15 to the 17th time t17 are the register setting RS, the period from the 3rd time t3 to the 5th time t5, the period from the 7th time t7 to the 9th time t9, the period from the 11th time t11 to the 12th time t12 and the period from the 17th time t17 to the 18th time t18 are the RGB data DRGB. The shift clock signal SC is a periodic pulse signal. The token signal TK is maintained at a high level.

During the nth frame (from the zeroth time t0 to the twenty-second time t22), assuming that the column of micro-LED integrated circuits includes n micro-LED integrated circuits uIC1~uICn, with respect to the micro-LED integrated circuit uIC1, it is in the idle IDLE operating state during the zeroth time t0 to the second time t2, it is in the shift data SD operating state during the second time t2 to the sixth time t6, and it is in the pulse width modulation generator PWMG generating the nth frame operating state during the sixth time t6 to the twenty-first time t21.

Next, with respect to the micro-luminescent diode integrated circuit uIC2, during the period from the zeroth time t0 to the fourth time t4, the pulse width modulation generator PWMG generates the operating state of the n-1th frame, during the period from the fourth time t4 to the sixth time t6, it is the idle operating state IDLE, during the period from the sixth time t6 to the tenth time t10, it is the operating state of the shift data SD, and during the period from the tenth time t10 to the twenty-second time t22, the pulse width modulation generator PWMG generates the operating state of the nth frame.

The rest can be deduced in this way until the last micro-LED integrated circuit uICn, in which the pulse width modulation generator PWMG generates the operating state of the n-1th frame during the period from the zeroth time t0 to the fourteenth time t14, the idle operating state during the period from the fourteenth time t14 to the sixteenth time t16, the shift data SD operating state during the period from the sixteenth time t16 to the nineteenth time t19, and the pulse width modulation generator PWMG generates the operating state of the nth frame during the period from the nineteenth time t19 to the twenty-second time t22.

Please refer to FIG. 20, which shows a timing diagram of a token signal, a row data signal, and a shift clock signal of a plurality of rows of micro-LED integrated circuits. As shown in FIG. 20, for the first row of micro-LED integrated circuits, the nth subframe SFn includes shift setting SS0, shift data SD0, shift setting SS1, shift data SD1, ..., shift setting SSm-1, shift data SDm-1, and dummy data DM in sequence. The row data signal CD corresponding to the shift settings SS0, SS1, ..., SSm-1 is a plurality of setting values S[0], S[1], ... in sequence. The row data signal CD corresponding to the shift data SD0, SD1, ..., SDm-1 is a plurality of data D0, D1, ... in sequence. Similarly, the n+1th subframe SFn includes shift setting SS0, shift data SD0, shift setting SS1, shift data SD1, ..., shift setting SSm-1, shift data SDm-1 and dummy data DM in sequence. The row data signal CD corresponding to the shift settings SS0, SS1, ..., SSm-1 is a plurality of setting values S[0], S[1], ... in sequence. The row data signal CD corresponding to the shift data SD0, SD1, ..., SDm-1 is a plurality of data D0, D1, ... in sequence. During the nth subframe SFn, the token signal TK maintains a high level only when the setting value S[0] of the shift setting SS0 is set, and maintains a low level at the rest of the time. Each pulse of the shift clock signal SC corresponds to a plurality of setting values S[0], S[1], ... and a plurality of data D0, D1, ...

Next, for the second row of micro-LED integrated circuits, the shift setting SS0 and the shift data SD0 correspond to the row data signal CD that maintains 0 or 1. The row data signal CD corresponding to the shift settings SS1, ..., SSm-1 are sequentially a plurality of setting values S[0], S[1], .... The row data signal CD corresponding to the shift data SD1, ..., SDm-1 are sequentially a plurality of data D0, D1, .... During the n-th subframe SFn, the token signal TK maintains a high level only when the setting value S[0] of the shift setting SS1 is maintained, and maintains a low level at the rest of the time.

The rest can be deduced in this way until the last n-th row of micro-LED integrated circuits. During the n-th subframe SFn, the token signal TK maintains a high level only when the setting value S[0] of the shift setting SSm-1 is maintained, and maintains a low level for the rest of the time.

Compared to the prior art, the micro-LED display system of the present invention includes a plurality of columns of micro-LED integrated circuits, and each micro-LED integrated circuit connected in series in each column of micro-LED integrated circuits does not need to be provided with a phase-locked loop (PLL), and the number of connections between adjacent micro-LED integrated circuits and the number of connections between the micro-LED integrated circuits and the panel can be reduced, thereby achieving the substantial effect of significantly reducing the overall circuit cost and area of the micro-LED display system.

DR: Driver for LED display system

CDR: Clock Data Recovery Unit

DIV:Division unit

DEC: Decoding Unit

REG: Temporary Unit

SRAM(BFB): Storage Cell

CON: Control Unit

GEN:Generate unit

DAT: Data signal

CLK: clock signal

DCLK: first clock signal

GCLK: Second clock signal

CD: row data signal

EN: Enable signal

SC: shift clock signal

uIC: micro-luminescent diode integrated circuit

TKI: Token Input

TKO: Token Output

SRTC: Displacement Regulator and Token Controller

CL:Clock Unit

IBD: Inverter/Buffer/D-type Flip-flop

RGB: data unit

RS:Save Configurator

ST: Register

PWMC: Pulse Width Modulation Controller

CS:LED current source

BS: Bias Unit

I1~In:LED current

TK: Token signal

SRAM0: first storage area

SRAM1: Second storage area

SRAM2: The third storage area

SET: Set signal

BF0: First frame

BF1: Second bit frame

BF2: Third Bit Frame

LSYNC: horizontal synchronization signal

BF0: First frame

BF1: Second bit frame

BF2: Third Bit Frame

SF0~SF15: 0th subframe~15th subframe

t0~t27: time 0~time 27

SET: Set signal

SFn:nth subframe

SFn+1: n+1th subframe

SS0~SSm-1: shift setting

SD0~SDm-1: shift data

S[0]: Setting value

S[1]: Setting value

D0: Data

D1: Data

D2: Data

DM:Dummy data

DRGB: RGB data

SEP: Shift Enabled Period

ONEP: LED enable period

SRAM(LB): Storage Cell

uIC1~uICn: micro-luminescent diode integrated circuit

RS:Save Configurator

DU:Data Unit

IDLE: Idle

SD: Shift data

PWMG: Pulse Width Modulation Generator

ENC:Encoding unit

DBST: decoder, bit alignment, shift register and token controller

EC: Start code

FIG. 1 and FIG. 2 are schematic diagrams of a driver and a first row of micro-LED integrated circuits of a LED display system in a first preferred embodiment of the present invention, respectively.

FIG. 3 is a schematic diagram of the micro-LED integrated circuit in FIG. 2 .

FIG. 4 to FIG. 8 respectively illustrate timing diagrams of the control unit of the driver controlling the storage unit to read/write column data signals in different embodiments.

FIG. 9 is a timing diagram showing an enable signal, a row data signal, and a shift clock signal of a single row of micro-LED integrated circuits.

FIG. 10 is a timing diagram showing an enable signal, a row data signal, and a shift clock signal of a plurality of rows of micro-LED integrated circuits.

FIG. 11 and FIG. 12 are schematic diagrams of a driver and a first row of micro-LED integrated circuits of a LED display system in a second preferred embodiment of the present invention, respectively.

FIG. 13 is a schematic diagram of the micro-LED integrated circuit in FIG. 12 .

FIG. 14 is a timing diagram showing a token signal, a row data signal, and a shift clock signal of a single row of micro-LED integrated circuits and the operating state of each micro-LED integrated circuit.

FIG. 15 is a timing diagram showing a token signal, a row data signal, and a shift clock signal of a plurality of rows of micro-LED integrated circuits.

FIG. 16 and FIG. 17 are schematic diagrams of a driver and a first row of micro-LED integrated circuits of a LED display system in a third preferred embodiment of the present invention, respectively.

FIG. 18 is a schematic diagram of the micro-LED integrated circuit in FIG. 17 .

FIG. 19 is a timing diagram showing an enable signal, a row data signal, and a shift clock signal of a single row of micro-LED integrated circuits and the operating state of each micro-LED integrated circuit.

FIG. 20 is a timing diagram showing a token signal, a row data signal, and a shift clock signal of a plurality of rows of micro-LED integrated circuits.

DR: Driver for LED display system

CDR: Clock Data Recovery Unit

DIV:Division unit

DEC: decoding unit

REG: Temporary unit

SRAM(BFB): storage unit

CON: Control unit

GEN:Generation unit

DAT: data signal

CLK: clock signal

DCLK: first clock signal

GCLK: second clock signal

CD: row data signal

EN: Enable signal

SC: shift clock signal

Claims (17)

A micro-luminescent diode (μLED) display system includes: a driver, including: a clock data recovery unit, for receiving a data signal embedded with a clock signal and outputting the clock signal and the data signal respectively; a frequency division unit, coupled to the clock data recovery unit, for receiving the clock signal and outputting a first clock signal and a second clock signal respectively; and a A generating unit is coupled to the clock data recovery unit and the frequency dividing unit, and is used to generate a column data signal and a shift clock signal according to the data signal, the first clock signal and the second clock signal respectively; and a first column micro-luminescent diode integrated circuit, including a plurality of micro-luminescent diode integrated circuits connected in series, and is used to sequentially transmit the column data signal and the shift clock signal. The micro-luminescent diode display system as described in claim 1, wherein the generating unit further generates an enable signal according to the data signal, the first clock signal and the second clock signal, and the enable signal is sequentially transmitted by the plurality of micro-luminescent diode integrated circuits connected in series. The micro-luminescent diode display system as described in claim 2, wherein the driver further includes: a decoding unit, coupled to the clock data recovery unit and the frequency division unit, for decoding the data signal and the first clock signal and outputting them; and a storage unit, coupled between the decoding unit and the generation unit, for storing the data signal and the first clock signal for access by the generation unit, and the storage unit is a bit frame buffer. The micro-luminescent diode display system as described in claim 3, wherein the driver further comprises: a control unit coupled to the storage unit for controlling the read/write operation of the storage unit; and a temporary storage unit coupled to the decoding unit for temporarily storing the relevant parameter settings required to generate the column data signal, the second clock signal, the shift clock signal and the enable signal. As described in claim 2, the micro-luminescent diode display system, wherein each micro-luminescent diode integrated circuit is respectively coupled to a plurality of micro-luminescent diodes and generates a pulse width modulation control signal according to the enable signal, the row data signal and the shift clock signal to control whether the plurality of micro-luminescent diodes emit light or not. A micro-luminescent diode display system as described in claim 4, wherein if the storage unit includes a first storage area, a second storage area and a third storage area and the data signal includes a first bit frame, a second bit frame and a third bit frame, during a first time to a second time, the control unit writes the first bit frame to the first storage area; during a second time to a third time, the control unit writes the second bit frame to the second storage area; during a third time to a fourth time, the control unit writes the third bit frame to the third storage area and writes the third bit frame from the first storage area to the third storage area. The control unit reads the first bit frame from the first storage area and outputs it; during the fourth time to the fifth time, the control unit reads the second bit frame from the second storage area and outputs it; during the fifth time to the sixth time, the control unit reads and outputs the first bit frame from the first storage area; during the sixth time to the seventh time, the control unit reads the third bit frame from the third storage area and outputs it; during the seventh time to the eighth time, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area and outputs it. A micro-luminescent diode display system as described in claim 4, wherein if the storage unit includes a first storage area, a second storage area and a third storage area and the data signal includes a first bit frame, a second bit frame and a third bit frame, during a first time to a third time, the control unit writes the first bit frame to the first storage area; during a third time to a fifth time, the control unit writes the second bit frame to the second storage area; during a fifth time to a sixth time, the control unit writes the third bit frame to the third storage area and reads the first bit frame from the first storage area and outputs it; during a sixth time to a seventh time, the control unit continues The third bit frame is written into the third storage area and the second bit frame is read from the second storage area and then outputted; during the seventh time to the eighth time, the control unit reads and outputs the first bit frame from the first storage area; during the eighth time to the ninth time, the control unit reads and outputs the third bit frame from the third storage area; During the period from the ninth time to the tenth time, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area and then outputs it; during the period from the tenth time to the eleventh time, the control unit continues to write the third bit frame into the third storage area and reads the second bit frame from the second storage area and then outputs it. A micro-luminescent diode display system as described in claim 4, wherein if the storage unit includes a first storage area, a second storage area and a third storage area and the data signal includes a first bit frame, a second bit frame and a third bit frame, during a first time to a fourth time, the control unit writes the first bit frame into the first storage area; during a fourth time to a seventh time, the control unit The second bit frame is written into the second storage area; during the seventh time to the eighth time, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area and outputs it; during the eighth time to the ninth time, the control unit continues to write the third bit frame into the third storage area and reads the second bit frame from the second storage area and outputs it; during the ninth time During the period from the tenth time to the tenth time, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area and outputs it; during the period from the tenth time to the eleventh time, the control unit reads the third bit frame from the third storage area and outputs it; during the period from the eleventh time to the twelfth time, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area The control unit reads the first bit frame from the first storage area and outputs it; during the period from the twelfth time to the thirteenth time, the control unit continues to write the third bit frame into the third storage area and reads the second bit frame from the second storage area and outputs it; during the period from the thirteenth time to the fourteenth time, the control unit writes the third bit frame into the third storage area and reads the first bit frame from the first storage area and outputs it. The micro-LED display system as described in claim 2 further includes a second row of micro-LED integrated circuits, which includes a plurality of micro-LED integrated circuits connected in series to sequentially transmit the enable signal, the row of data signals and the shift clock signal, wherein the rising edge of the enable signal transmitted by the second row of micro-LED integrated circuits is later than the rising edge of the enable signal transmitted by the first row of micro-LED integrated circuits. The micro-luminescent diode display system as described in claim 1, wherein the generating unit further generates a token signal according to the data signal, the first clock signal and the second clock signal, and the token signal is sequentially transmitted by the plurality of micro-luminescent diode integrated circuits connected in series. The micro-luminescent diode display system as described in claim 10, wherein the driver further includes: a decoding unit, coupled to the clock data recovery unit and the frequency division unit, for receiving the data signal and the first clock signal for decoding and output; and a storage unit, coupled between the decoding unit and the generation unit, for storing the decoded data signal and the first clock signal for access by the generation unit, and the storage unit is a line buffer. The micro-luminescent diode display system as described in claim 11, wherein the driver further comprises: a control unit coupled to the storage unit for controlling the read/write action of the storage unit; and a temporary storage unit coupled to the decoding unit for temporarily storing the relevant parameter settings required to generate the column data signal, the second clock signal, the shift clock signal and the token signal. A micro-LED display system as described in claim 10, wherein each micro-LED integrated circuit is respectively coupled to a plurality of micro-LEDs and generates a pulse width modulation control signal according to the token signal, the column data signal and the shift clock signal to control the light emission of the plurality of micro-LEDs. A micro-LED display system as described in claim 1, wherein the plurality of micro-LED integrated circuits connected in series also receive a token signal and transmit the token signal in sequence. The micro-luminescent diode display system as described in claim 14, wherein the driver further comprises: a decoding unit, coupled to the clock data recovery unit and the frequency division unit, for receiving the data signal and the first clock signal for decoding and outputting; a storage unit, coupled to the decoding unit, for storing the decoded data signal and the first clock signal, and the storage unit is a line buffer; and a coding unit, coupled between the storage unit and the generation unit, for encoding the decoded data signal and the first clock signal and transmitting them to the generation unit. The micro-luminescent diode display system as described in claim 15, wherein the driver further comprises: a control unit coupled to the storage unit for controlling the read/write action of the storage unit; and a temporary storage unit coupled to the decoding unit for temporarily storing the relevant parameter settings required to generate the column data signal, the second clock signal, and the shift clock signal. A micro-luminescent diode display system as described in claim 14, wherein each micro-luminescent diode integrated circuit is respectively coupled to a plurality of micro-luminescent diodes and generates a pulse width modulation control signal according to the token signal, the column data signal and the shift clock signal to control the illumination of the plurality of micro-luminescent diodes.

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