JP2004061585A - Display panel drive, display control device and drive - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display panel drive for performing reading operation of data for controlling display of a display panel, and processing the read data on the basis of the clock with a proper frequency. <P>SOLUTION: This drive is equipped with a frame memory 1 for storing address data, a read control part 3 for reading the address data from the frame memory 1 based on the clock A, a serializer 7 for transferring the address data read by the read control part 3, and a drive part 100B for driving a plasma display panel 30 based on the address data transferred by the serializer 7. By setting FIFO memories 61-63 between the frame memory 1 and the serializer 7, the clock for reading operation of the address data (clock A) is separated from the clock for processing operation of the read address data (clock B). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display panel driving device for driving a matrix display panel such as a plasma display panel.
[0002]
[Prior art]
Japanese Patent Application Laid-Open No. H11-95713 describes a display panel driving device for transmitting image data or the like, which is digital data, on a line in a display device. Here, a method of transmitting this digital signal by LVDS (Low Voltage Differential Signaling) (differential serial transmission method) is used. The LVDS transmission system is a system in which two signal lines are driven symmetrically in opposite phases and the difference between the signals on the two signal lines is transmitted, so that noise mixed in from the outside cancels out the signal. Has the advantage that it is difficult to give
[0003]
[Problems to be solved by the invention]
However, conventionally, in a case where image data or the like is read from a memory by such a method and transmitted, the clock used for reading the image data from the memory is the same as the clock used in the LVDS transmission method. Frequency or an integer ratio of frequencies. For this reason, there have been cases where it is not possible to set both the clock used for the operation of reading image data from the memory and the clock used for transmission by the LVDS or the operation of the destination circuit to the optimum clock frequency.
[0004]
An object of the present invention is to provide a display panel driving device or the like that can execute a data read operation for controlling display on a display panel and a read data processing operation based on a clock having an appropriate frequency. I do.
[0005]
[Means for Solving the Problems]
2. The display panel driving device according to claim 1, wherein: a memory for storing display control data; reading means for reading the display control data from the memory based on a first clock of a first frequency; and the reading means. A display panel drive device comprising: a data transfer unit that transfers the read display control data; and a display panel drive unit that drives a display panel based on the display control data transferred by the data transfer unit. A clock conversion circuit is provided between the memory and the data transfer means.
[0006]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a display panel driving device according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a display panel driving device of the present embodiment.
[0007]
As shown in FIG. 1, the display panel driving device 100 of the present embodiment is configured by connecting a display control unit 100A and a driving unit 100B to each other by transmission lines L1 and L2.
[0008]
As shown in FIG. 1, the display control unit 100A includes a frame memory 1 for sequentially storing address data, a write control unit 2 for writing address data to the frame memory 1, and a read control unit for reading address data from the frame memory 1. A read control unit 3, a control unit 4 for controlling each unit of the device, an AND circuit 5 for calculating a logical product of a clock output from the control unit 4 and a signal HA output from the read control unit 3, and an address data and the like. A clock converter 6A for converting a clock, a serializer 7 for converting parallel data such as address data output from the clock converter 6A into a serial differential signal, and various types of data read from the control data memory 4a of the controller 4. A clock converter 6B for converting a clock such as control data, and various control data output from the clock converter 6B It includes a serializer 11 for converting parallel data into serial differential signal.
[0009]
The drive unit 100B includes a deserializer 8 that converts a serial differential signal transferred from the serializer 7 via the transmission line L1 into multi-bit parallel data, and a serial differential signal transferred from the serializer 11 via the transmission line L2. , A shift register 15 for storing one line of address data, and one line of address data when the one line of address data is stored in the shift register 15. A latch circuit 16 for latching, and an address driver 17 for generating a data pulse for one line according to the address data for one line and applying the data pulse simultaneously to the column electrodes Z1 to Zm of the plasma display panel 30 are provided. Address driver 18 and Y sustain A sustain driver 19 for simultaneously applying pulses to the sustain electrodes Y1 to Yn of the plasma display panel 30, a scan driver 20 for sequentially applying scan pulses to the sustain electrodes Y1 to Yn, and a sustain electrode X1 for applying the X sustain pulse to the plasma display panel 30. To Xn, and a drive control unit 22 that controls the reset pulse generation circuits 20A and 21A that generate reset pulses, the sustain driver 19, the scan driver 20, the sustain driver 21, and the like.
[0010]
As shown in FIG. 1, the clock conversion unit 6 </ b> A converts a shift clock output from the AND circuit 5 into a FIFO (First-In First-Out) memory 61 that sequentially stores address data read from the frame memory 1. The memory includes a FIFO memory 62 for sequentially storing and a FIFO memory 63 for sequentially storing pulse generation control data output from the control unit 4. As shown in FIG. 1, the FIFO memory 61, the FIFO memory 62, and the FIFO memory 63 each execute a write operation in accordance with a clock A output from the control unit 4, and perform a read operation in accordance with a clock B output from the control unit 4. Execute The frequencies of the clock A and the clock B can be set independently of each other. For example, the frequencies of the clock A and the clock B can be set so that the two frequencies are not the same frequency and do not have an integer ratio.
[0011]
The clock conversion unit 6B includes a FIFO memory 64, a FIFO memory 65, and a FIFO memory that sequentially store the scan driver control data, the sustain driver control data, the other control data, and the clock C, which are read from the control data memory 4a. 66 and a FIFO memory 67. As shown in FIG. 1, the FIFO memory 64, the FIFO memory 65, the FIFO memory 66, and the FIFO memory 67 each execute a write operation according to the clock A output from the control unit 4, and The read operation is performed according to B.
[0012]
As will be described later, in the display panel driving device 100 of the present embodiment, the clock converter 6A and the clock converter 6B convert the clock frequency handling address data, various control data, and the like from the clock A to the clock B. I have. Thus, the clock frequency of the data read operation from the frame memory 1, the control data memory 4a, and the like, and the clock frequency of the data processing operation at a stage subsequent to the clock converters 6A and 6B can be set independently. Therefore, it is possible to select an optimum clock frequency for each operation.
[0013]
As shown in FIG. 1, the serializer 7 includes a PLL unit 71 that receives a clock B from the control unit 4 and generates a transmission clock, the address data read from the frame memory 1, and the shift data output from the AND circuit 6. An input latch unit 72 for latching a clock and pulse generation control data output from the control unit 4 based on a clock B from the control unit 4, and parallel data latched by the input latch unit 72 from the PLL unit 71. A parallel / serial conversion unit 73 for serializing based on a clock having a frequency n times higher than the clock B input from the control unit 4, and a serial cable output from the parallel / serial conversion unit 73 with a twist cable or the like. And a transmission output unit 74 for performing differential serial transmission via the transmission line L1.
[0014]
The deserializer 8 includes a receiving unit 81 that receives a differential serial signal transferred via the transmission line L1, a PLL unit 82 that receives a transfer clock transferred via the transmission line L1, and generates a clock, A serial / parallel conversion unit 83 that converts a serial signal output from 81 into parallel data based on a clock having a frequency n times as high as a transfer clock from a PLL unit 82, and parallel data output from the serial / parallel conversion unit 83 And an output latch unit 84 that latches the clock with the clock from the PLL unit 82. The transfer clock and the clock supplied to the output latch unit 84 have the same frequency as the clock B input to the PLL unit 71.
[0015]
As shown in FIG. 1, the serializer 11 includes a PLL unit 111 that receives a clock B from the control unit 4 and generates a transmission clock, a scan driver control data output from the control data memory 4a, and a sustain driver control data. An input latch unit 112 for latching other pulse generation control data and a clock based on the clock B output from the control unit 4, and a parallel data latched by the input latch unit 112 from the control unit 5. A parallel / serial conversion unit 113 that serializes based on a clock having a frequency n times the input clock and serial data output from the parallel / serial conversion unit 113 are transmitted via a transmission line L2 composed of a twisted cable or the like. And a transmission output unit 114 for performing dynamic serial transmission.
[0016]
The deserializer 12 includes: a receiving unit 121 that receives a differential serial signal transferred via the transmission line L2; a PLL unit 122 that receives a transfer clock transferred via the transmission line L2 to generate a clock; A serial / parallel conversion unit 123 that converts a serial signal output from the serial signal 121 into parallel data based on a clock having a frequency n times the transfer clock from a PLL unit 122, and parallel data output from the serial / parallel conversion unit 123 And an output latch unit 124 for latching the clock with the clock from the PLL unit 122. The transfer clock and the clock supplied to the output latch unit 124 have the same frequency as the clock B input to the PLL unit 111.
[0017]
As shown in FIG. 1, a clock output from the deserializer 12 is provided to the drive control unit 22, and the drive control unit 22 controls the generation timing of the drive pulse based on the clock.
[0018]
Next, the operation of the display panel driving device 100 will be described.
[0019]
One field as a period for driving the plasma display panel 30 includes a plurality of subfields SF1 to SFN. As shown in FIG. 2, each subfield is provided with an address period for selecting a cell to be lit and a sustain period for keeping the cell selected in the address period lit for a predetermined time. Further, a reset period for resetting the lighting state in the previous field is further provided at the head of SF1, which is the first subfield. In this reset period, all cells are reset to lighting cells (cells on which wall charges are formed) or off cells (cells on which no wall charges are formed). In the former case, a predetermined cell is switched to a non-lighted cell, and in the latter case, a predetermined cell is switched to a lighted cell in a subsequent address period. The sustain period is gradually increased in the order of the subfields SF1 to SFN, and a predetermined gradation display is enabled by changing the number of the subfields to be continuously turned on.
[0020]
In the address period of each subfield shown in FIG. 3, address scanning is performed for each line. That is, at the same time as the scanning pulse is applied to the row electrode Y1 forming the first line, the data pulse DP1 corresponding to the address data corresponding to the cell of the first line is applied to the column electrodes Z1 to Zm. At the same time, a scan pulse is applied to the row electrode Y2 forming the second line, and at the same time, a data pulse DP2 corresponding to the address data corresponding to the second cell is applied to the column electrodes Z1 to Zm. Similarly, the scanning pulse and the data pulse are simultaneously applied to the third and subsequent lines. Lastly, the scan pulse is applied to the row electrodes Yn forming the n-th line, and at the same time, the data pulses DPn corresponding to the address data corresponding to the cells of the n-th line are applied to the column electrodes Z1 to Zm. . As described above, in the address period, a predetermined cell is switched from a lit cell to a non-lit cell or from a non-lit cell to a lit cell.
[0021]
When the address scanning is completed in this way, all the cells in the subfield are set as either the lighted cells or the lighted cells, and only the lighted cells emit light each time a sustain pulse is applied in the next sustain period. repeat. As shown in FIG. 3, during the sustain period, an X sustain pulse and a Y sustain pulse are repeatedly applied to the row electrodes X1 to Xn and the row electrodes Y1 to Yn at predetermined timings. In the last subfield SFN, there is provided an erasing period in which all cells are set to non-lighted cells.
[0022]
Next, signal processing of address data and various control data used for driving the plasma display panel 30 will be described.
[0023]
As shown in FIG. 1, the address data read from the frame memory 1, the shift clock output from the AND circuit 6, and the control data for pulse generation read from the control data memory 4a are stored in the clock conversion unit 6A. The data is sequentially written to the FIFO memory 61, the FIFO memory 62, and the FIFO memory 63, respectively. The address data, shift clock, and pulse generation control data read from the FIFO memories 61, 62, and 63 of the clock converter 6A are input to the serializer 7.
[0024]
As shown in FIG. 1, a clock A from the control unit 4 is supplied to the write control unit 2, the read control unit 3, and the control data memory 4A. The operation of writing address data to the memory 1, the operation of reading address data from the frame memory 1, and the operation of reading control data for pulse generation from the control data memory 4A are executed based on the clock A. Further, the operation of writing the address data, the shift clock, and the control data for pulse generation to the FIFO memories 61, 62, and 63 of the clock conversion unit 6A is also executed based on the clock A.
[0025]
On the other hand, the read operation of the address data, the shift clock, and the pulse generation control data from the FIFO memories 61, 62, and 63 of the clock conversion unit 6A is executed based on the clock B. The operations of the serializer 7 and the deserializer 8 are also performed based on the clock B or a clock generated from the clock B. As described above, the operation of reading each data from the clock conversion unit 6A and the operation at a stage subsequent to the clock conversion unit 6A are executed based on the clock B.
[0026]
As described above, in the display panel driving device 100 of the present embodiment, the operation of reading out each data from the frame memory 1 and the control data memory 4A arranged before the clock conversion unit 6A is executed based on the clock A. The operation of reading each data from clock conversion unit 6A and the operation at a stage subsequent to clock conversion unit 6A are executed based on clock B. That is, the clock (clock A) of the operation of the frame memory 1 arranged before the clock conversion unit 6A by the clock conversion unit 6A, and the processing operation of each of the read data in the stage subsequent to the clock conversion unit 6A. Clock (clock B) can be separated from each other. In the present embodiment, since the frequencies of the clock A and the clock B can be set independently of each other, the frequency of the clock A and the frequency of the clock B can be set to an optimum frequency according to the respective operations. It becomes.
[0027]
The address data, the shift clock, and the control data for pulse generation read from the clock conversion unit 6A are latched by the input latch unit 72 based on the clock B from the control unit 4 and serialized by the parallel / serial conversion unit 73. The signal is converted and converted by the transmission output unit 74 into a signal according to the differential serial transmission method (LVDS transmission method). The differential serial signal (LVDS signal) thus obtained is transferred at high speed LVDS data via the transmission line L1. Here, the address data is bit data (serial data) for each subfield for each cell of R, G, and B, and the serial data of each of R, G, and B is stored in the serializer 7 together with the shift clock and the control data for pulse generation. Are input in parallel. These parallel data are serial-converted in the serializer 7.
[0028]
The serial signal transferred via the transmission line L1 is parallel-converted in the deserializer 8, and the original parallel signal is restored.
[0029]
FIG. 4 is a diagram showing the timing of writing address data and latch enable. The address data output from the deserializer 8 is sequentially written into the shift register 15 line by line. As shown in FIG. 4, the latch enable input to the latch circuit 16 rises at the same time as the rise of the shift clock for writing the last data (data z) for one line, so that the data for one line (for example, Data a to data z) are latched and input to the address driver 17 at the same time. Thus, as described above, at the same time as the scanning pulse is sequentially applied to the row electrodes Y1 to Yn in the address period, the data pulses DP1 to DPn corresponding to the predetermined address data are applied to the column electrodes Z1 to Zm. This latch enable is generated in the latch enable generation unit 16A based on the shift clock.
[0030]
In the present embodiment, the signal HA is output from the read control unit 3 only while the address data is being read from the frame memory 1. As shown in FIG. 1, by inputting the signal HA and the clock output from the control unit 5 to the AND circuit 6, the clock passes only during the period in which the signal HA is output ("H"). And outputs it as a shift clock. That is, the supply of the shift clock is stopped during a period in which the address data is not read from the frame memory 1. For this reason, as shown in FIG. 4, the shift clock is not supplied during the period in which the address data is not read, and during this period, the data in the shift register 15 is not updated, and the normal latch enable signal is not The memory state at the time of starting up is maintained. Therefore, as shown in FIG. 4, even when the noise is superimposed on the latch enable, the data latched by the noise becomes the same as the normal address data. Therefore, even if the address data is latched at an incorrect timing due to noise, a data pulse according to the normal address data is applied to the plasma display 30.
[0031]
The pulse generation control data output from the deserializer 8 is data for controlling on / off of a switch provided in an address resonance power supply circuit 17A (FIG. 1) that outputs a drive pulse to the address driver 17. . The address resonance power supply circuit 17A is a circuit for obtaining a predetermined power supply voltage by utilizing resonance when the switches are regularly turned on / off, but details thereof are omitted.
[0032]
Next, as shown in FIG. 1, the scan driver control data, the sustain driver control data, the other pulse generation control data, and the clock C read from the control data memory 4A are stored in the FIFO memory of the clock converter 6B. 64, FIFO memory 65, FIFO memory 66, and FIFO memory 67, respectively. The control data for the scan driver, the control data for the sustain driver, the control data for the sustain driver, other control data for pulse generation, and the clock C of the FIFO memory 64, the FIFO memory 65, the FIFO memory 66, and the FIFO memory 67 of the clock conversion unit 6B are serializers. 11 is input.
[0033]
As shown in FIG. 1, a clock A from the control unit 4 is supplied to the control data memory 4A, and the operation of reading each control data from the control data memory 4A is executed based on the clock A. The write operation of scan driver control data, sustain driver control data, other pulse generation control data, and clock C into FIFO memories 64, FIFO memories 65, FIFO memories 66, and FIFO memories 67 of clock converter 6B is also performed. , Based on the clock A.
[0034]
On the other hand, the read operations of the scan memory control data, the sustain driver control data, the other pulse generation control data, and the clock C from the FIFO memory 64, FIFO memory 65, FIFO memory 66, and FIFO memory 67 of the clock conversion unit 6B are as follows. , Based on the clock B. The operations of the serializer 11 and the deserializer 12 are also executed based on the clock B or a clock generated from the clock B. As described above, the operation of reading each data from the clock conversion unit 6B and the operation at a stage subsequent to the clock conversion unit 6B are executed based on the clock B.
[0035]
As described above, in the display panel drive device 100 of the present embodiment, the operation of reading each data from the control data memory 4A disposed before the clock conversion unit 6B is executed based on the clock A, and the clock conversion unit The operation of reading each data from 6B and the operation at a stage subsequent to clock conversion unit 6B are executed based on clock B. In other words, the clock (clock A) of each control data read operation from the control data memory 4A arranged before the clock conversion unit 6B by the clock conversion unit 6B, and the clock read at a stage subsequent to the clock conversion unit 6B. The clock (clock B) for the processing operation of each control data can be separated from each other. In the present embodiment, since the frequencies of the clock A and the clock B can be set independently of each other, the frequency of the clock A and the frequency of the clock B can be set to an optimum frequency according to the respective operations. It becomes.
[0036]
As shown in FIG. 1, the scan driver control data, the sustain driver control data, other pulse generation control data, and the clock C read from the clock conversion unit 6B are based on the clock B from the control unit 4. The signal is latched by the input latch unit 112, is converted into a serial signal by the parallel / serial conversion unit 113, and is converted by the transmission output unit 114 into a signal according to the differential serial transmission method (LVDS transmission method). The differential serial signal (LVDS signal) thus obtained is transferred at high speed LVDS data via the transmission line L2. Here, the scan driver control data, the sustain driver control data, the other pulse generation control data, and the clock C are input to the serializer 11 in parallel, and the parallel data is serial-converted in the serializer 11.
[0037]
The serial signal transferred via the transmission line L2 is parallel-converted in the deserializer 12, and the original parallel signal is restored.
[0038]
The scan driver control data, the sustain driver control data, and other pulse generation control data output from the deserializer 12 are input to the drive control unit 22, respectively. The drive control unit 22 sends a signal for turning on / off a switching element provided in the scan driver 20 based on the scan driver control data to a switching element provided in the sustain drivers 19 and 21 based on the sustain driver control data. And a signal for turning on / off the switching elements provided in the reset pulse control units 20A and 21A, based on other pulse generation control data.
[0039]
As described above, in the display panel driving device 100 of the present embodiment, since the clock conversion unit 6A and the clock conversion unit 6B are provided, the clock of the data read operation in the preceding stage of the clock conversion unit 6A or the clock conversion unit 6B is provided. And a clock for an operation for processing the read data in a subsequent stage of the clock conversion unit 6A or the clock conversion unit 6B can be separated from each other. Therefore, the clock frequency of each operation can be optimized.
[0040]
In the display panel driving device 100, both the address data and the shift clock are converted into a series of serial data by the serializer 7 and transferred. In other words, the shift clock is converted into data at the same time as the address data, and then both are collectively processed. Transfer. Therefore, there is no possibility that skew occurs between the address data and the shift clock. In the display panel driving device 100, the control data such as the scan driver control data, the sustain driver control data, and other pulse generation control data, and the clock C are converted into a series of serial data by the serializer 11 and transferred. are doing. Therefore, there is no possibility that skew occurs between the control data and the clock C. Therefore, there is an advantage that a means for adjusting timing such as a delay circuit for canceling skew is not required.
[0041]
Further, in this embodiment, since the differential serial transmission system using the LVDS is adopted, there are advantages such as being less susceptible to noise and reducing radiation of noise to the outside.
[0042]
The address data, the pulse generation control data, the scan driver control data, the sustain driver control data, and the other pulse generation control data in the above embodiment respectively correspond to the “display control data” described in the claims. . The display control data is not limited to the data described in the above embodiment.
[0043]
The frame memory 1 and the control data memory 4A in the above embodiment each correspond to a “memory” described in claims.
[0044]
In the above embodiment, the plasma display panel is exemplified as the display panel, but the present invention can be applied to various display panels such as a liquid crystal display panel and an EL display panel as the display panel.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a display panel driving device according to an embodiment.
FIG. 2 is a diagram showing a configuration of one field.
FIG. 3 is a diagram showing a driving pulse in one subfield.
FIG. 4 is a diagram showing address data latched by a latch enable;
[Explanation of symbols]
1 frame memory (memory)
3 Read control unit (read means)
4A control data memory (memory)
6A Clock converter (clock converter)
6B Clock converter (clock converter)
7, 11 serializer (data transfer means)
30 Plasma display panel (display panel)
61 to 67 FIFO memories 71 and 111 PLL circuits (first PLL circuits)
73, 113 Parallel / serial converters 74, 114 Transmission output unit (transfer unit)
82,122 PLL circuit (second PLL circuit)
83, 123 serial / parallel converter L1, L2 transmission line 100B drive unit (display panel drive unit)

Claims (3)

A memory for storing display control data, read means for reading the display control data from the memory based on a first clock of a first frequency, and data for transferring the display control data read by the read means A display panel drive device comprising: a transfer unit; and a display panel drive unit that drives a display panel based on the display control data transferred by the data transfer unit.
A display panel drive device comprising a clock conversion circuit provided between the memory and the data transfer means. The clock conversion circuit includes a FIFO memory;
The display control data is written into the FIFO memory based on the first clock, and is stored in the FIFO memory based on a second clock having a second frequency set independently of the first clock. The display panel driving device according to claim 1, wherein the written display control data is read. A first PLL circuit that generates a third clock having an n-fold frequency and a fourth clock having the second frequency in synchronization with the second clock;
A parallel / serial converter for performing parallel / serial conversion of the display control data based on the third clock output from the first PLL circuit;
A transfer unit that converts a signal serially converted by the parallel / serial converter into a signal according to a differential serial transmission method and transfers the signal via a transmission line;
A receiving unit that receives the display control data transferred via the transmission line,
A fifth clock having an n-fold frequency and a sixth clock having the same frequency as the fourth clock in synchronization with the fourth clock output from the first PLL circuit and transmitted via the transmission line. A second PLL circuit that generates
2. A serial / parallel converter for serially / parallel-converting the received display control data based on the fifth clock output from the second PLL circuit. 3. The display panel driving device according to 2.

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