TWI712020B - Display device - Google Patents

Abstract

The present invention discloses a display device for fingerprint identification, including a pixel array, a gate driving circuit and a fingerprint identification circuit. The gate driving circuit is connected to the pixel array and the fingerprint identification circuit, and the gate driving circuit includes a plurality of gate driving units, each of the gate driving units further includes a pull up circuit and a boosting circuit, the boosting circuit is configured to enhance a driving voltage level, and the pull up circuit is configured to receive the driving voltage level, thereby controlling the output signal of the fingerprint identification circuit.

Description

Display device

This application relates to a display device, especially a display device for fingerprint recognition.

In recent years, the number of fingerprint recognition circuits applied to portable panels has increased year by year, and especially for mobile phones, almost 80% of mobile phones are predicted to have fingerprint recognition in 2020. For mobile phones, fingerprint recognition has become the standard Equipped. Therefore, if fingerprint recognition can be integrated on the panel, it will help reduce costs.

However, the fingerprint recognition circuit constructed by using CMOS devices uses the principle of switching capacitor, and uses two-phase cut timing to send the capacitive charge on the fingerprint of the finger to the integrator for signal amplification; The design itself will be affected by parasitic capacitance, which will cause unexpected signals to be mixed in signal amplification. Furthermore, in order to achieve good picture quality, the screen resolution and the ability to control the fingerprint recognition circuit must be relatively improved. In this case, the load of the control circuit will increase. Therefore, strengthening the driving ability of the gate drive circuit must be overcome. problem.

The present application provides a display device to solve the noise problem generated by the current fingerprint recognition circuit and the insufficient driving capability of the gate drive circuit, which causes the circuit components to deteriorate and have a short life span, and the control fingerprint recognition ability is poor.

In order to solve the above-mentioned problems, this application is implemented as follows: This application provides a display device for fingerprint recognition. The display device includes a pixel array, a fingerprint recognition circuit, and a gate drive circuit. The pixel array has multiple images. Element unit; the gate drive circuit is connected to the pixel array and the fingerprint identification circuit. The gate drive circuit includes a plurality of gate drive units. Each gate drive unit includes a pull-up circuit and an increase circuit. The pull-up circuit is connected to increase The booster circuit enhances a driving voltage level, and the pull-up circuit is used to receive the driving voltage level, thereby controlling the output signal of the fingerprint recognition circuit.

In the embodiment of the present application, the gate drive circuit is shared to achieve the panel display and fingerprint identification signal output. That is to say, when the screen is scanned once, the fingerprint identification circuit will also be scanned once to perform fingerprint detection. Sensing result output.

In order to have a further understanding and understanding of the features of the application and the achieved effects, only examples and detailed descriptions are provided, and the description is as follows:

With the development of low-temperature polysilicon semiconductor thin film transistors with ultra-high carrier mobility characteristics, integrated circuit technology based on the periphery of the panel has gradually become the focus of attention. The array substrate row drive technology (Gate Driver on Array, GOA) uses liquid crystal displays In the array manufacturing process, a gate scanning driving signal circuit is fabricated on an array substrate to realize the progressive driving and scanning of the pixel unit. In order to reduce the production cost and achieve a more streamlined display device, this application proposes a GOA circuit with a fingerprint recognition circuit system. At the same time, the fingerprint recognition circuit is integrated in the panel to achieve the purpose of reducing cost. In the application of this application, the GOA circuit proposed in this application is suitable for small size panels. Please refer to FIG. 1, which is a circuit block diagram of this application. The display device 1 includes a pixel array 10, a gate drive circuit 12, and a fingerprint recognition circuit 14. The pixel array 10 has a plurality of pixel units 16, and the gate drive circuit 12 is connected to the pixel array 10 for driving The voltage pre-pixel array 10, the gate drive circuit 12 includes a plurality of gate drive units 18, each gate drive unit 18 further includes a pull-up circuit 20 and a booster circuit 22, the pull-up circuit 20 is electrically connected The booster circuit 22, the booster circuit 22 enhances a driving voltage level, and the pull-up circuit 20 is used to receive the driving voltage level, and thereby control the output signal of the fingerprint recognition circuit 14, which will be described in detail later.

To further understand the circuit operation of this application, please refer to FIG. 2, which is the circuit diagram of this application. First, the gate drive circuit 12 includes a plurality of gate drive units. Here, the gate drive unit 18 of the N stage (odd-numbered stage) and the gate drive unit 18' of the N+1th stage (odd-numbered stage) are two sets of gates. Taking the pole driving unit as an example, the gate driving units 18 and 18 ′ are connected to the fingerprint identification circuit 14 and the pixel array 10. The fingerprint recognition circuit 14 further includes a sensing unit 24, an amplifier 26, and a reading unit 28. The amplifier 26 is electrically connected to the sensing unit 24 and the reading unit 28, and the sensing unit 24 is used to sense finger touches. Control voltage, finger touch makes the capacitance Cf change and then determines the amount of charge stored in front of the integrator. All transistors (M1, M2, M3, M4) and capacitances (Cf, Cp) in the sensing unit 24 can be used to a minimum Size to optimize the resolution. The amplifier 26 accumulates and amplifies the touch voltage of the sensed finger and transmits it to the reading unit 28. The amplifier 26 uses the amplification capability of the integrator to use the accumulated signal and amplify the effect. The problem of insufficient gain of the amplifier constructed by the a-Si transistor is made up; finally, the reading unit 28 reads the amplified sensed finger touch voltage.

To further explain the operation of the fingerprint identification circuit, please refer to FIG. 3, which is a circuit timing diagram of the fingerprint identification circuit of this application. When the finger touches, during the sensing period, the clock signal CLKC1 is the high voltage VH, which will turn on the transistor M1 and the transistor M4 to charge the finger capacitance Cf generated on the finger. At this time, both ends of the sensing board Both are charged to the same potential. Since the sensing board is designed at both ends of the parasitic capacitance Cp, according to the capacitance formula Q=CV, the parasitic capacitance Cp of the parallel sensing board will not be charged at this time, so it does not participate in the fingerprint identification process. When the clock signal CLKC2, the transistor M2 and the transistor M3 are turned on, and the charge on the finger capacitor Cf will be put on the accumulated integrating capacitor Cs, and the signal will be accumulated and amplified through the amplifier 26. After the clock signal CLKC2 ends, it will Return to the timing of the clock signal CLKC1, and execute the repeated loop operation until the set read signal comes, and the read unit 28 reads the signal. Since the parasitic capacitance Cp in the design of the fingerprint recognition circuit 14 of the present application does not participate in the fingerprint recognition process, the signal amplification process can solve the problem of unintended signals mixed in the conventional technology, so that the fingerprint recognition ability is improved. optimization.

In further detail the circuit design of a set of gate drive units of the present application, the gate drive unit 18 includes a pull-up circuit 20, a booster circuit 22, a setting circuit 30, a reset circuit 32, and a first anti-noise circuit 34. A second anti-noise circuit 36, a third anti-noise circuit 38, a first negative bias compensation circuit 40, a second negative bias compensation circuit 42, and a third negative bias compensation circuit 44. The setting circuit 30 includes a first transistor M1, including a first terminal, a second terminal, and a third terminal. The first terminal is connected to the boost circuit 22 and the pull-up circuit 20. The reset circuit 32 includes a second transistor M2, including a first terminal, a second terminal, and a third terminal. The first terminal of the second transistor M2 is connected to the first terminal of the first transistor M1. The pull-up circuit 20 includes a third transistor M3, including a first terminal, a second terminal, and a third terminal, and a fourth transistor M4, including a first terminal, a second terminal, and a third terminal. The second end of the fourth transistor M4 is connected to the second end of the third transistor M3. The booster circuit 22 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The fifth transistor M5 includes a first terminal, a second terminal, and a At the third end, the first end of the fifth transistor M5 is connected to the second end of the first capacitor C1 of the booster circuit 22. The sixth transistor M6 includes a first terminal, a second terminal, and a third terminal. The first terminal of the sixth transistor M6 is connected to the second terminal of the first capacitor C1 of the booster circuit 22. The sixth transistor M6 The second end and the third end of the sixth transistor M6 are connected to each other. The seventh transistor M7 includes a first terminal, a second terminal, and a third terminal. The first terminal of the seventh transistor M7 is connected to the second terminal of the first capacitor C1 of the booster circuit 22. The seventh transistor M7 The second end of and the third end of the seventh transistor M7 are connected to each other. The eighth transistor M8 includes a first end, a second end and a third end. The first end of the eighth transistor M8 is connected to the second end of the first capacitor C1 of the booster circuit 22. The eighth transistor M8 The second end of and the third end of the eighth transistor M8 are connected to each other. The first anti-noise circuit 34 includes a thirteenth transistor M13 and a sixteenth transistor M16, and the thirteenth transistor M13 and the sixteenth transistor M16 are used to connect to the third terminal of the third transistor M3. The second anti-noise circuit 36 includes a ninth transistor M9 and a twelfth transistor M12, and the ninth transistor M9 and the sixteenth transistor M16 are used to connect to the third terminal of the fourth transistor M4. The first negative bias compensation circuit 40 includes a fourteenth transistor M14 and a fifteenth transistor M15, the fourteenth transistor M14 and the fifteenth transistor M15 are used to connect the thirteenth transistor M13, and the second The negative bias compensation circuit 42 includes a tenth transistor M10 and an eleventh transistor M11, and the tenth transistor M10 and the eleventh transistor M11 are used for connecting the ninth transistor M9. The third anti-noise circuit 38 includes a twentieth transistor M20 and a nineteenth transistor M19. The twentieth transistor M20 includes a first terminal, a second terminal and a third terminal. The first terminal of the twentieth transistor M20 is connected to the first capacitor C1 of the booster circuit 22. The nineteenth transistor M19 includes a first end, a second end, and a third end. The first end is connected to the second end of the twentieth transistor M20. The third negative bias compensation circuit 44 includes an eighteenth transistor M18 and a seventeenth transistor M17. The seventeenth transistor M17 includes a first terminal, a second terminal, and a third terminal. The first end of the transistor M17 is connected to the second end of the seventeenth transistor M17, and the third end of the seventeenth transistor M17 is connected to the second end of the twentieth transistor M20. The eighteenth transistor M18 is used to connect the third end of the seventeenth transistor M17 and the second end of the twentieth transistor M20.

After understanding the design of the detailed circuit components, we will continue to improve the driving ability and how to improve the driving ability of the overall circuit. Please refer to Figure 2, Figure 3 and Figure 4 at the same time. Figure 4 is the circuit timing diagram of the gate drive unit of this application. . Since the gate drive unit 18 of the N stage (odd-numbered stage) and the gate drive unit 18' of the N+1th stage (odd-numbered stage) have the same circuit design and operation principle, one Take the group gate drive unit 18 as an example. When the whole circuit is in working condition, firstly, in the first time period T1, the trigger signal CN-3 turns on the fifth transistor M5 and pulls down the node AN to the low voltage level VSS2. The purpose is to utilize the capacitive coupling characteristic of the first capacitor C1 , A potential exists between the node QN and the node AN in the booster circuit 22, which is the potential generated by the high voltage VDD minus the transistor voltage V _{TH_M1 and the} lower voltage level _VSS2 . During the second time period T2, the first transistor M1 in the control setting circuit 30 is turned on to start charging the node QN, and the node AN is still pulled down to the low voltage level VSS2 at this time, so that the first capacitor C1 has The potential is the potential generated by the high voltage VDD reduction transistor voltage V _{TH_M1} reducing the voltage level _VSS2 to facilitate subsequent coupling actions, and the first voltage of the node QN rises to the high voltage level V _H -V _{TH_M1} ; At that time, the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, and the fourteenth transistor M14 will be turned on at the same time, and the low voltage level VSS of the node CN and the node GN will be pulled down. It is -6V to prevent noise. Among them, the node CN is used as the output terminal of the fourth transistor M4 in the pull-up circuit 20, which is to control the output of the fingerprint identification circuit, and the node GN is used as the output terminal of the third transistor M3 in the pull-up circuit 20, and the purpose is to output to The pixel array 10 does not require feedback to other stages and increases the circuit design, so the circuit design is more simplified and more efficient, which will be described in detail later.

When the third time period T3 is reached, the trigger signal CN-1 in the booster circuit 22 is precharged to the high voltage level VH, and the high voltage level VH is 18V. At this time, the sixth transistor M6 is turned on to operate and the node AN charges, and uses the capacitive coupling characteristic of the first capacitor C1 to perform a voltage coupling action on the node QN to _raise the second voltage of the node QN to the voltage level V _H -V _{TH_M1} +ΔV1; A negative bias voltage compensation circuit 40 and a second negative bias voltage compensation circuit 42 operate, that is, the clock signal CLK2 of the negative bias voltage compensation will be turned on, and the thirteenth transistor M13 in the first anti-noise circuit 34 will be turned on. And the gate terminal potential level of the ninth transistor M9 in the second anti-noise circuit 36 is pulled down to a low voltage level VSS2, which is -10V, which is the same as the thirteenth transistor M13 and the ninth transistor The source voltage level of M9 is -6V compared to the bias voltage of the component VGS-4V. This action is the negative bias compensation action of this circuit.

When the fourth time period T4 is reached, the clock signal CLK3 changes to the high voltage level VH, which is 18V. At this time, the seventeenth transistor M17 in the third anti-noise circuit 38 will be turned on. The parasitic capacitance on the driving twentieth transistor M20 is used to couple and charge the node QN, so that the third voltage of the node QN is raised to the voltage level V _H -V _{TH_M1} +ΔV1+ΔV2. In addition, the trigger signal CN-1 and node CN respectively turn on the sixth transistor M6 and the seventh transistor M7 in the booster circuit 22 here, and the node AN is also charged again; at this time, the ninth transistor M9, The negative bias compensation of the thirteenth transistor M13 continues, that is to say, the clock signal CLK2 of the negative bias compensation will continue to be turned on, and the thirteenth transistor M13 and the first anti-noise circuit 34 The gate terminal potential level of the ninth transistor M9 in the secondary anti-noise circuit 36 is pulled down to the low voltage level VSS2, the gate terminal voltage level is -10V, which is the same as the thirteenth transistor M13 and the ninth transistor M9 Compared with the source voltage level of -6V, the bias voltage VGS of the component is -4V. This action is the negative bias compensation action of this circuit. When the execution reaches the fifth time period T5, at this time, the node CN and the trigger signal CN+1 in the booster circuit 22 will turn on the seventh transistor M7 and the eighth transistor M8 to operate, and then charge the node AN again, and borrow The first capacitor C1 is capacitively coupled to _{raise the} voltage of the node QN to the fourth high voltage level V _H -V _{TH_M1} +ΔV1+ΔV2+ΔV3. For the twelfth transistor M12 in the first anti-noise circuit 34, the sixteenth transistor M16 in the second anti-noise circuit 36, and the twentieth transistor M20 in the third anti-noise circuit 38 , Because the clock signal CLK4 in the third negative bias compensation circuit 44 turns on the operation of the eighteenth transistor M18, the gates of the twelfth transistor M12, the sixteenth transistor M16, and the twentieth transistor M20 are pulled down The voltage level is to VSS2, and the gate voltage level is -10V, so that the bias voltage VGS of these three transistors presents a potential of -4V, which is the start of the negative bias compensation of the three transistors, such as node PN The gate terminals of the twelfth transistor M12, the sixteenth transistor M16, and the twentieth transistor M20 are coupled, and the negative bias compensation action of the ninth transistor M9 and the thirteenth transistor M13 ends. It is worth noting that the voltage level of node QN is the highest when the execution reaches the fifth time T5 interval. It can be seen from the circuit timing diagram that the voltage level of the node QN is between the second time T2 interval and the fifth time T5 interval. The first capacitor C1 of the booster circuit 22 is pulled up during the second time period T2 to start charging to a first voltage V _H -V _{TH_M1} for the first time, and the first voltage V of the first capacitor C1 is _increased during the third time period T3. _H -V _{TH_M1} to a second voltage V _H -V _{TH_M1} +ΔV1, continue to increase the second voltage of the first capacitor C1 V _H -V _{TH_M1} +ΔV1 to a third voltage V _H -V during the fourth time period T4 _{TH_M1} +ΔV1+ΔV2, finally in the fifth time period T5, the third voltage V _H -V _{TH_M1} +ΔV1+ΔV2 of the first capacitor C1 is pulled up to a fourth voltage V _H -V _{TH_M1} +ΔV1+ΔV2+ΔV3, using The timing sequence enables the multi-stage coupling of the first capacitor C1, so that the driving point node QN of the gate driving unit 18 can be raised to a higher potential, thereby greatly improving the driving capability.

Among them, the node CN in the pull-up circuit 20 of the gate driving unit 18 is connected to the sixth transistor M6 in the reading unit 28 of the fingerprint identification circuit 14, and the gate driving unit of the N+1th stage (odd-numbered stage) The node CN in the pull-up circuit 20' of 18' is connected to the seventh transistor M7 in the reading unit 28 of the fingerprint recognition circuit 14. As shown in FIG. 3, the clock signal CLK2 for negative bias voltage compensation is turned on, and the driving voltage level enhanced by the boost circuit 22 receives the driving voltage level through the pull-up circuit 20, thereby controlling the output signal of the fingerprint recognition circuit 14 In detail, the driving voltage level is output to the sixth transistor M6 and the seventh transistor M7, so that the fingerprint identification will output the identification result Vout only when the designed time clock signal CLKH1 and the clock signal CLKH2. The node GN in the pull-up circuit 20 of the gate driving unit 18 and the node GN in the pull-up circuit 20' of the gate driving unit 18' of the N+1th stage (odd-numbered stage) are connected to the pixel array 10.

Taking the circuit timing diagram of FIG. 4 again, when the execution reaches the sixth time T6 interval, the clock signal CLK1 turns on the thirteenth transistor M13, the fourteenth transistor M14, and the second anti-noise circuit 34. The ninth transistor M9 and the tenth transistor M10 in the anti-noise circuit 36 pull down the node CN and the node GN to the low voltage level VSS, which is -6V, and drive the trigger in the reset circuit 32 The signal CN+2 turns on the operation of the second transistor M2, and pulls down the voltage level of the node QN to VSS, and the voltage level is -6V. When the seventh time period T7 is reached, the trigger signal CN+2 in the reset circuit 32 turns on the second transistor M2, and continues to pull down the voltage level to VSS at the node QN, the voltage level is -6V; at this time, The thirteenth transistor M13 in the first anti-noise circuit 34 and the ninth transistor M9 in the second anti-noise circuit 36 are precharged again to the high voltage level VH due to the clock signal CLK2. The voltage level is 18V, so the negative bias compensation of these two pins starts again. When the eighth time T8 is reached, the third anti-noise circuit 38 turns on the sixteenth circuit in the first anti-noise circuit 34 because the clock signal CLK3 becomes the high voltage level VH, and the high voltage level is 18V. The crystal (M16), the twelfth transistor M12 in the second anti-noise circuit 36, and the twentieth transistor M20 in the third anti-noise circuit 38 operate, and then pull down the nodes QN, CN and GN respectively The voltage level is to VSS, and the low voltage level is -6V to prevent noise generation in a non-working state. When the execution reaches the ninth time interval T9, the clock signal CLK3 and the clock signal CLK4 are activated to start the operation of the eighteenth transistor M18, the sixteenth transistor M16, the twelfth transistor M12, and the twentieth transistor M20. The negative bias compensation action starts to work again. When the ninth time T9 interval ends, in the non-working state, the action from the sixth time T6 interval to the ninth time T9 interval will continue until the next update cycle arrives, and the time sequence from the first time T1 interval Start the action. It can be seen that, in view of the problem of the V _TH shifting to the right of the transistor element due to the long-term positive bias operation, the present application uses the negative bias compensation circuit design to solve the problem of the V _TH shifting to the left of the long-time operating element Compensation can improve the problem of component degradation, thereby extending the life of the circuit. In addition, this application aims at increasing the potential difference between the gate point and the source of the driving transistor, so that the driving force is increased, that is, the fall time can be shorter. In terms of the circuit design of the fast gate drive unit 18, the fall time Fast, fast rise time, driving ability is the most ideal.

Through the operation of the fingerprint recognition circuit 14 described above, the resolution can be calculated to be 411 dpi. Of course, it is not limited to this range. Using the fingerprint recognition circuit 14 of the present application to operate, the resolution can reach 400-500 dpi, so it can be improved. The ability of fingerprint recognition. This application mounts the designed gate drive circuit 12 on a 5.5-inch high-resolution panel, as shown in Figure 5, which is a schematic diagram of the high-resolution negative panel load equivalent circuit of this application, where the measured capacitance values are all 7.6 The pF and resistance values are both 1.92KΩ, and the measured values are consistent. It can be seen that all measurement points GL of the gate drive output are very perfect. Please refer to FIG. 6, FIG. 7 and the following tables (1) and (2) at the same time. FIG. 6 is a fingerprint recognition measurement waveform diagram of the application, and FIG. 7 is a gate drive output measurement waveform diagram of the application. Table (1) shows the measurement results of the gate drive circuit: Noise (RMS) Rise time (µs) Fall time (µs) GL[1] 1.53 1.32 0.06 GL[2] 1.51 1.33 0.07 GL[359] 1.54 1.32 0.08 GL[360] 1.49 1.31 0.09

Among them, from the measured values of rise time, fall time and noise in the table, it can be known that the measured values of this application are very similar, so the driving voltage is quite stable, and the voltage of the node QN also appears as expected by the design. Reached the ability of multi-stage coupling and improved the driving voltage capability.

Table (2) shows the measurement results of the fingerprint identification circuit: Finger capacitance value Sense voltage 100fF 3.564 60fF 2.726 40fF 2.628 1fF 1.623

Among them, the voltage value measured through the distance of the touch position of the finger fingerprint can optimize the fingerprint recognition ability due to the improvement of the driving ability. In this application, the fingerprint recognition circuit 14 and the gate drive circuit 12 are combined and integrated on the glass panel, because the output of the gate drive circuit 12 controls the output switch of the fingerprint recognition circuit 14, so that the fingerprint recognition circuit 14 is designed The identification result will be output only after time, so the control method is that when the pixel array 10 (display screen) is updated once, the fingerprint identification circuit 14 will also follow the identification action once, in which the fourth transistor M4 of the circuit 20 is pulled up. The output node CN is a carry-level design to control the output of the fingerprint recognition circuit 14, and the output node GN of the third transistor M3 of the pull-up circuit 20 is the output of the load, so it will not increase the complexity of other feedback circuits. In turn, the production cost can be reduced.

In summary, in order to achieve good picture quality, the screen resolution of this application is improved, and the problem of noise caused by parasitic capacitance is solved, so that the resolution reaches 411dpi, and the fingerprint recognition capability is relatively improved. Furthermore, the present application uses a novel gate drive circuit design to couple the capacitors in multiple stages through timing, with signal feedback, so that the drive point node QN of the gate drive unit can be raised to a higher potential multiple times, so that The output signal has good rise and fall times, thereby greatly improving the driving capability. Furthermore, a negative bias voltage compensation circuit design is added to the circuit to improve the deterioration of the components, thereby extending the operating life of the circuit.

However, the above are only examples of this application, and are not used to limit the scope of implementation of this application. For example, all the shapes, structures, features and spirits described in the scope of the patent application of this application are equivalent changes and modifications. , Should be included in the scope of patent application of this application.

1: display device 10: Pixel array 12: Gate drive circuit 14: Fingerprint recognition circuit 16: pixel unit 18, 18’: Gate drive unit 20:, 20’: Pull up the circuit 22: Increasing circuit 24: sensing unit 26: Amplifier 28: Reading unit 30: Setting circuit 32: Reset circuit 34: The first anti-noise circuit 36: The second anti-noise circuit 38: The third anti-noise circuit 40: The first negative bias compensation circuit 42: The second negative bias compensation circuit 44: Third negative bias compensation circuit Cf: Finger capacitance Cp: parasitic capacitance Cs: integral capacitance CLKC1:, CLKC2, CLKH1, CLKH2, CLK1, CLK2:, CLK3:, CLK4: clock signal VH: High voltage level C1: first capacitor M1: The first transistor M2: second transistor M3: third transistor M4: The fourth transistor M5: fifth transistor M6: The sixth transistor M7: seventh transistor M8: Eighth Transistor M9: Ninth Transistor M10: Tenth Transistor M11: The eleventh transistor M12: Twelfth Transistor M13: Thirteenth transistor M14: Fourteenth Transistor M15: fifteenth transistor M16: Sixteenth Transistor M17: Seventeenth Transistor M18: Eighteenth Transistor M19: The nineteenth transistor M20: Twentieth transistor VSS2, VSS: Low voltage level CN-3, CN-1, CN+1, CN+2: trigger signal CN, GN, QN, AN, PN: Node T1: the first time T2: second time T3: third time T4: Fourth time T5: Fifth time T6: Sixth time T7: Seventh time T8: Eighth time T9: Ninth time VDD: high voltage

Figure 1: This is the circuit block diagram of this application. Figure 2: This is the circuit diagram of this application. Figure 3: This is a circuit timing diagram of the fingerprint identification circuit of this application. Figure 4: This is a circuit timing diagram of the gate driving unit of this application. Figure 5: This is a schematic diagram of the load equivalent circuit of the high-resolution panel of this application. Figure 6: This is a fingerprint identification measurement waveform diagram of this application. Figure 7: This is the waveform diagram of the gate drive output measurement of this application.

1: display device

10: Pixel array

12: Gate drive circuit

14: Fingerprint recognition circuit

16: pixel unit

18: Gate drive unit

20: Pull up the circuit

22: Increasing circuit

Claims (10)

A display device for fingerprint recognition, comprising: a pixel array with a plurality of pixel units; a fingerprint recognition circuit; and a gate driving circuit connected to the pixel array and the fingerprint recognition circuit, the gate The driving circuit includes a plurality of gate driving units, each of the gate driving units includes a pull-up circuit and a booster circuit, the pull-up circuit is connected to the booster circuit, and the booster circuit boosts a driving voltage level, The pull-up circuit is used for receiving the driving voltage level and controlling the output signal of the fingerprint identification circuit. The display device according to claim 1, wherein the gate driving unit further includes a setting circuit, and the setting circuit includes: a first transistor including a first terminal, a second terminal, and a third terminal , The first end is connected to the boost circuit and the pull-up circuit. The display device according to claim 2, wherein the gate driving unit further includes a reset circuit, and the reset circuit includes: a second transistor including a first terminal, a second terminal, and a first terminal; Three ends, the first end of the second transistor is connected to the first end of the first transistor. The display device according to claim 2, wherein the boosting circuit includes a first capacitor, and the setting circuit boosts a first voltage of the first capacitor at a third time at a second time Raise the first voltage to a second voltage, continue to raise the second voltage to a third voltage at a fourth time, and raise the third voltage to a fourth voltage at a fifth time. For example, the display device of claim 4, wherein the pull-up circuit includes: A third transistor includes a first end, a second end and a third end; a fourth transistor includes a first end, a second end and a third end, and the second end is connected to the The second end of the third transistor, and the first end of the fourth transistor is connected to the first end of the first capacitor. For example, the display device of claim 4, wherein the boosting circuit includes: a fifth transistor including a first terminal, a second terminal and a third terminal, and the first terminal is connected to the first capacitor of the first capacitor Two terminals; a sixth transistor, including a first terminal, a second terminal and a third terminal, the first terminal is connected to the second terminal of the first capacitor, the second terminal and the third terminal are connected to each other A seventh transistor including a first terminal, a second terminal and a third terminal, the first terminal is connected to the second terminal of the first capacitor, and the second terminal and the third terminal are connected to each other; and An eighth transistor includes a first terminal, a second terminal and a third terminal, the first terminal is connected to the second terminal of the first capacitor, and the second terminal and the third terminal are connected to each other; wherein, The first terminal of the first capacitor is connected to the first terminal of the first transistor. The display device according to claim 5, wherein the gate driving unit further includes: a first anti-noise circuit including a thirteenth transistor and a sixteenth transistor, the thirteenth transistor And the sixteenth transistor is used to connect the third end of the third transistor; and a second anti-noise circuit including a ninth transistor and a twelfth transistor, the ninth transistor and The twelfth transistor is used for connecting to the third end of the fourth transistor. The display device according to claim 7, wherein the gate driving unit further includes: a first negative bias compensation circuit including a fourteenth transistor and a fifteenth transistor, the fourteenth transistor The crystal and the fifteenth transistor are used to connect the thirteenth transistor; and A second negative bias compensation circuit includes a tenth transistor and an eleventh transistor, and the tenth transistor and the eleventh transistor are used for connecting the ninth transistor. The display device according to claim 4, wherein the gate driving unit further includes a third anti-noise circuit, including: a twentieth transistor, including a first terminal, a second terminal, and a At the third end, the first end of the twentieth transistor is connected to the first capacitor of the booster circuit; and a nineteenth transistor including a first end, a second end and a third end, The first end is connected to the second end of the twentieth transistor. The display device according to claim 9, wherein the gate driving unit further includes a third negative bias compensation circuit, including a seventeenth transistor, including a first terminal, a second terminal, and a The third end, the first end of the seventeenth transistor is connected to the second end of the seventeenth transistor, and the third end of the seventeenth transistor is connected to the second end of the twentieth transistor End; and an eighteenth transistor for connecting the third end of the seventeenth transistor and the second end of the twentieth transistor.

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