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CN118800161A - Gate driving circuit, display panel and display panel driving method - Google Patents

Gate driving circuit, display panel and display panel driving method Download PDF

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Publication number
CN118800161A
CN118800161A CN202411139292.7A CN202411139292A CN118800161A CN 118800161 A CN118800161 A CN 118800161A CN 202411139292 A CN202411139292 A CN 202411139292A CN 118800161 A CN118800161 A CN 118800161A
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China
Prior art keywords
transistor
point
gate
gate driving
driving unit
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CN202411139292.7A
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Chinese (zh)
Inventor
刘昊天
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Guangzhou China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Guangzhou China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to CN202411139292.7A priority Critical patent/CN118800161A/en
Publication of CN118800161A publication Critical patent/CN118800161A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application relates to a gate driving circuit, a display panel and a display panel driving method, wherein the gate driving circuit comprises a gate driving unit which is cascaded in multiple stages, and an N-th stage gate driving unit comprises: the pull-up module is electrically connected with the second Q point, and N is a positive integer; the pull-up control module comprises a first transistor and a second transistor, wherein the grid electrode of the first transistor and the grid electrode of the second transistor are electrically connected with the grid electrode signal end of the N-1 level grid electrode driving unit, the source electrode of the first transistor is electrically connected with the high voltage end or the grid electrode signal end of the N-1 level grid electrode driving unit, and the drain electrode of the first transistor is electrically connected with the source electrode of the second transistor; the grid electrode of the second transistor is electrically connected with the grid electrode of the first transistor, the drain electrode of the second transistor is electrically connected with the second Q point of the N-th stage grid electrode driving unit, and the drain electrode of the first transistor and the source electrode of the second transistor are both electrically connected with the first Q point; wherein the potential of the first Q point is consistent with the potential of the second Q point.

Description

Gate driving circuit, display panel and display panel driving method
Technical Field
The present application relates to the field of display technologies, and in particular, to a gate driving circuit, a display panel, and a display panel driving method.
Background
The Gate-driver On Array (GOA) of the Array substrate is a driving method of integrating the Gate driving circuit On the Array substrate of the display panel and outputting the Gate scan signal row by using thin film transistors (Thin Film Transistor, TFTs). The gate driving circuit includes a multistage cascade of gate driving units. Taking an nth stage gate driving unit as an example, a Q point of the nth stage gate driving unit is a point of a gate of the related thin film transistor controlling the high potential of the gate scan signal G (N), and the stability of the Q point voltage determines the stability of the gate scan signal G (N), where N is a positive integer.
In the related art, the pull-up control module is composed of a thin film transistor T11. The pull-up control module has two common connection methods, namely a diode connection method and a VGH connection method. In either connection, if the threshold voltage of the thin film transistor T11 is negatively shifted (simply referred to as "negative bias"), or the thin film transistor T11 operates at a high temperature, the leakage at the QN point increases.
Fig. 1 shows a schematic diagram of a gate driving unit in the related art. As shown in fig. 1, the related art gate driving unit outputs gate signals G (N), which are the number of stages of the gate driving unit, row by using a thin film transistor circuit. In the gate driving unit of fig. 1, the gate signal G (N-1) of the upper stage gate driving unit is pulled high, and thus the thin film transistor T11 of the pull-up control module is turned on, thereby pulling the QN point potential high. Since the QN point potential is pulled up, the thin film transistor T21 of the pull-up unit is turned on to output the gate signal G (N), and at the same time, the thin film transistor T41 of the pull-down unit is controlled to be turned on by the gate signal G (n+1) of the lower gate driving unit, so that the QN point potential is pulled down, thereby realizing the level transmission. Therefore, in the operation of the gate driving circuit, the potential stabilization of the QN point is critical to the operation of the gate driving circuit.
Fig. 2 shows a schematic diagram of a pull-up control module in the related art. As shown in fig. 2, in two common junctions of the related art, (a) is a diode junction and (B) is a VGH junction. In the diode connection design, when the potential of the gate signal G (N-1) of the gate driving unit of the previous stage is reduced, the working potential of the QN point is reduced due to the leakage of the QN point to G (N-1) after the thin film transistor T11 is turned off. If the QN point operating potential is lowered too much, the thin film transistor T21 is not fully turned on, resulting in insufficient charging of G (N). As the cascade proceeds, this effect accumulation eventually leads to a failure of the gate signal G (N). In the VGH connection design, the source and the drain of the thin film transistor T11 are both high, so that the leakage current during the QN point operation can be improved, but in the QN point low potential period, the existence of the leakage current can raise the QN point potential, so that the thin film transistor T21 is slightly turned on, and the gate signal G (N) can generate a cyclic peak after the accumulation of the cascade.
Disclosure of Invention
In view of this, the present application provides a gate driving circuit, a display panel and a driving method for a display panel, which can reduce the leakage degree of the Q point, and reduce the influence of the Q point leakage on the gate signal output, so as to improve the stability of the gate driving circuit in the severe leakage environments such as high temperature.
According to an aspect of the present application, there is provided a gate driving circuit including a multi-stage cascade of gate driving units, an nth stage gate driving unit including: the pull-up module is electrically connected with the second Q point and is used for outputting a gate signal of the N-th stage gate driving unit, wherein N is a positive integer; the pull-up control module comprises a first transistor and a second transistor, wherein the grid electrode of the first transistor and the grid electrode of the second transistor are electrically connected to a grid electrode signal end of an N-1 level grid electrode driving unit, the grid electrode signal end of the N-1 level grid electrode driving unit is used for outputting a grid electrode signal of the N-1 level grid electrode driving unit, the source electrode of the first transistor is electrically connected to a high voltage end or a grid electrode signal end of the N-1 level grid electrode driving unit, and the drain electrode of the first transistor is electrically connected to the source electrode of the second transistor; the grid electrode of the second transistor is electrically connected with the grid electrode of the first transistor, the drain electrode of the second transistor is electrically connected with the second Q point of the N-th stage grid electrode driving unit, and the drain electrode of the first transistor and the source electrode of the second transistor are electrically connected with the first Q point; the potential of the first Q point is consistent with the potential of the second Q point.
According to still another aspect of the present application, there is provided a display panel including the gate driving circuit.
According to still another aspect of the present application, there is provided a display panel driving method applied to the gate driving circuit, the display panel driving method including: at a first moment, controlling the potential of a gate signal end of the N-1 level gate driving unit to change from low potential to high potential so that a first Q point and a second Q point of the N level gate driving unit are both raised to a first high potential; at a second moment, controlling the potential of a gate signal end of the N-1 level gate driving unit to change from high potential to low potential, so that the potential of the first Q point and the potential of the second Q point are maintained at a first high potential; and at a third moment, controlling the clock signal end of the N-th stage grid driving unit to change from low potential to high potential, so that the potential of the first Q point and the potential of the second Q point are coupled to second high potential, wherein the potential of the first Q point and the potential of the second Q point are consistent at the first moment, the second moment and the third moment.
By arranging two pull-up control transistors with a common grid structure in the pull-up control module, and electrically connecting the source electrode of one pull-up control transistor and the drain electrode of the other pull-up control transistor to a first Q point, the first Q point is electrically connected to a low voltage end of an N-stage grid driving unit, and the potential of the first Q point is consistent with that of a second Q point.
Drawings
Fig. 1 shows a schematic diagram of a gate driving unit in the related art.
Fig. 2 shows a schematic diagram of a pull-up control module in the related art.
Fig. 3 shows a schematic diagram of an nth stage gate driving unit according to an embodiment of the present application.
Fig. 4 is a schematic diagram showing an operation timing of an nth stage gate driving unit according to an embodiment of the present application.
Fig. 5 shows a flowchart of a display panel driving method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. The technical solutions described below are only for explaining and explaining the idea of the present application and should not be construed as limiting the scope of protection of the present application.
Furthermore, the terms "first," "second," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The term "plurality" and similar words mean two or more, unless specifically defined otherwise.
In view of this, the present application proposes a gate driving circuit, which includes a multi-stage cascade gate driving unit, as shown in fig. 3, and the nth stage gate driving unit includes a pull-up module 101 and a pull-up control module 102.
In an embodiment, the pull-up module 101 is electrically connected to the second Q point QN-b, and the pull-up module 101 is configured to output a gate signal G (N) of the nth stage gate driving unit, where N is a positive integer. The pull-up control module 102 includes a first transistor T11-a and a second transistor T11-b, wherein a gate of the first transistor T11-a is electrically connected to a gate of the second transistor T11-b, and a gate of the first transistor T11-a and a gate of the second transistor T11-b are both electrically connected to a gate signal terminal G (N-1) of an N-1 th stage gate driving unit, and the gate signal terminal G (N-1) of the N-1 th stage gate driving unit is configured to output a gate signal of the N-1 th stage gate driving unit; the source of the first transistor T11-a is electrically connected to the high voltage terminal VGH or the gate signal terminal G (N-1) of the N-1 stage gate driving unit. The drain electrode of the first transistor T11-a is electrically connected to the source electrode of the second transistor T11-b, the drain electrode of the first transistor T11-a and the source electrode of the second transistor T11-b are both electrically connected to the first Q point QN-a, and the drain electrode of the second transistor T11-b is electrically connected to the second Q point QN-b of the N-th stage gate driving unit. Wherein the potential of the first Q point QN-a is consistent with the potential of the second Q point QN-b.
In one embodiment, the first transistor T11-a and the second transistor T11-b may be a common gate structure. The first transistor T11-a and the second transistor T11-b may be diode-connected or VGH-connected. When diode connection is adopted, the source electrode of the first transistor T11-a is electrically connected with the grid electrode of the first transistor T11-a, namely, the grid electrode signal end G (N-1) of the N-1 th stage grid electrode driving unit is connected; when VGH connection is adopted, the source electrode of the first transistor T11-a is electrically connected to the high voltage end VGH.
It is noted that "-" in the first Q point QN-a and the second Q point QN-b of the present application means a bar, and the suffixes a and b are for distinguishing the first Q point QN-a and the second Q point QN-b, not minus signs. Whereas "-" such as in N-1, N+1 has the meaning of a minus sign, N-1, N, N +1 have a sequential relationship.
The second Q point QN-b has the same function as the QN point connected to the conventional pull-up unit in the related art of fig. 1, and can be used to control the potential of the gate signal terminal of the nth stage gate driving unit. Compared with fig. 1 in the related art, the pull-up control module 102 of the present application may add the second transistor T11-b, the first capacitor C44, the third transistor T43 and the fourth transistor T55.
In one embodiment, the pull-up control module 102 further includes a first capacitor C44. The first end of the first capacitor C44 is electrically connected to the clock signal end CLK (N) input by the nth stage gate driving unit, and the second end of the first capacitor C44 is electrically connected to the first Q point QN-a. The pull-up control module 102 further includes a third transistor T43. The grid electrode of the third transistor T43 is electrically connected to the control end KN of the nth stage grid electrode driving unit, and the potential of the control end KN is opposite to the potential of the second Q point QN-b. The source of the third transistor T43 is electrically connected to the low voltage terminal VGL, and the drain of the third transistor T43 is electrically connected to the first Q-point QN-a. The third transistor T43 and the first capacitor C44 cooperate to make the electric potential of the first Q point QN-a and the electric potential of the second Q point QN-b coincide, thereby better realizing the function of improving the electric leakage of the second Q point QN-b. The pull-up control module 102 further includes a fourth transistor T55. The gate of the fourth transistor T55 is electrically connected to the gate signal terminal G (N-1) of the N-1 th stage gate driving unit, the source of the fourth transistor T55 is electrically connected to the low voltage terminal VGL, and the drain of the fourth transistor T55 is electrically connected to the gate of the third transistor T43. The fourth transistor T55 pulls down the potential of the control terminal KN when the first Q point QN-a and the second Q point QN-b are charged to reduce the influence of the third transistor T43 on the charging of the first Q point QN-a and the second Q point QN-b.
As shown in fig. 3, the nth stage gate driving unit may further include an inverter 103, a pull-down module 104, and a reset module 105.
Referring to fig. 3, the pull-up module 101 includes a fifth transistor T21 and a second capacitor Cbt. The gate of the fifth transistor T21 is electrically connected to the second Q point QN-b and the first end of the second capacitor Cbt, the source of the fifth transistor T21 is electrically connected to the gate signal end of the nth stage gate driving unit, the gate signal end of the nth stage gate driving unit is used for outputting the gate signal of the nth stage gate driving unit, the drain of the fifth transistor T21 is electrically connected to the clock signal end CLK (N), and the clock signal end CLK (N) is used for receiving the clock signal input to the nth stage gate driving unit. The second end of the second capacitor Cbt is electrically connected to the gate signal end of the nth stage gate driving unit.
The inverter 103 includes a sixth transistor T51, a seventh transistor T52, an eighth transistor T53, and a ninth transistor T54. The gate of the sixth transistor T51 is electrically connected to the high voltage terminal VGH, the source of the sixth transistor T51 is electrically connected to the drain of the seventh transistor T52, and the drain of the sixth transistor T51 is electrically connected to the gate of the sixth transistor T51. The gate of the seventh transistor T52 is electrically connected to the second Q-point QN-b, and the source of the seventh transistor T52 is electrically connected to the low voltage terminal VGL. The gate of the eighth transistor T53 is electrically connected to the source of the sixth transistor T51, the source of the eighth transistor T53 is electrically connected to the control terminal KN of the nth stage gate driving unit, and the drain of the eighth transistor T53 is electrically connected to the drain of the sixth transistor T51. The gate of the ninth transistor T54 is electrically connected to the gate of the seventh transistor T52, the source of the ninth transistor T54 is electrically connected to the low voltage terminal VGL, and the drain of the ninth transistor T54 is electrically connected to the control terminal KN of the nth stage gate driving unit.
With continued reference to fig. 4, the pull-down module 104 includes a tenth transistor T41 and an eleventh transistor T42. The gate of the tenth transistor T41 is electrically connected to the gate signal terminal G (n+1) of the n+1th stage gate driving unit, the source of the tenth transistor T41 is electrically connected to the low voltage terminal VGL, and the drain of the tenth transistor T41 is electrically connected to the second Q point QN-b. The gate of the eleventh transistor T42 is electrically connected to the control terminal KN of the nth stage gate driving unit, the source of the eleventh transistor T42 is electrically connected to the low voltage terminal VGL, and the drain of the eleventh transistor T42 is electrically connected to the second Q-point QN-b. The pull-down module 104 further includes a twelfth transistor T32. The gate of the twelfth transistor T32 is electrically connected to the control terminal KN of the nth stage gate driving unit, the source of the twelfth transistor T32 is electrically connected to the low voltage terminal VGL, and the drain of the twelfth transistor T32 is electrically connected to the gate signal terminal G (N) of the nth stage gate driving unit. The reset module 105 includes a thirteenth transistor TrQ and a fourteenth transistor TrG. The gate of the thirteenth transistor TrQ is electrically connected to the Reset signal terminal Reset of the nth stage gate driving unit, the source of the thirteenth transistor TrQ is electrically connected to the low voltage terminal VGL, and the drain of the thirteenth transistor TrQ is electrically connected to the second Q point QN-b. The gate of the fourteenth transistor TrG is electrically connected to the Reset signal terminal Reset of the nth stage gate driving unit, the source of the fourteenth transistor TrG is electrically connected to the low voltage terminal VGL, and the drain of the fourteenth transistor TrG is electrically connected to the gate signal terminal G (N) of the nth stage gate driving unit.
Fig. 4 is a schematic diagram showing an operation timing of an nth stage gate driving unit according to an embodiment of the present application. As shown in fig. 5, at time T1, the potential of the clock signal terminal CLK (N-1) inputted by the N-1 th stage gate driving unit changes from a low potential to a high potential, and the potential of the gate signal terminal G (N-1) of the N-1 th stage gate driving unit changes from a low potential to a high potential, so that both the first transistor T11-a and the second transistor T11-b are in an on state, and thus both the first Q point QN-a and the second Q point QN-b of the N-th stage gate driving unit rise to a first high potential. Since the potential of the control terminal KN is opposite to the potential of the second Q-point QN-b by the inverter 103, the potential of the control terminal KN changes from high potential to low potential, and the third transistor T43 is in an off state. Since the potential of the first Q point QN-a is identical to the potential of the second Q point QN-b, there is no voltage difference between the first Q point QN-a and the second Q point QN-b, so that the second Q point QN-b has no leakage path, no leakage current is generated, and leakage of the second Q point QN-b is suppressed. It should be noted that, since the potential of the clock signal terminal CLK (N) input by the nth stage gate driving unit is low, the gate signal terminal G (N) of the nth stage gate driving unit will not output a high potential at this time.
At time t2, the potential of the gate signal terminal G (N-1) of the N-1 th stage gate driving unit changes from a high potential to a low potential, and the potential of the first Q point QN-a and the potential of the second Q point QN-b are maintained at the first high potential. At this time, the potential of the control terminal KN is low, the clock signal terminal CLK (N-1) input by the N-1 th stage gate driving unit is changed from high to low, and the gate signal terminal G (N) of the N-th stage gate driving unit does not output high.
At time t3, the clock signal terminal CLK (N) of the nth stage gate driving unit changes from low potential to high potential, and the potential of the first Q point QN-a further increases to a second high potential due to the capacitive coupling effect of the first capacitor C44; the potential of the second Q point QN-b is further raised to a second high potential due to the capacitive coupling effect of the second capacitance Cbt. At this time, the potential of the control terminal KN is still at a low potential, the clock signal terminal CLK (N-1) inputted by the N-1 th stage gate driving unit is at a low potential, and the gate signal terminal G (N) of the N-th stage gate driving unit starts to output a high potential.
At time t4, the clock signal terminal CLK (N) of the nth stage gate driving unit changes from high potential to low potential, and the potential of the first Q point QN-a and the potential of the second Q point QN-b further decrease to the first low potential. Since the electric potential of the control terminal KN is still low, the clock signal terminal CLK (N-1) input by the N-1-th stage gate driving unit is low, and the gate signal terminal G (N) of the N-th stage gate driving unit starts to output high electric potential.
At time T5, since the third transistor T43 is turned on, the first Q-point QN-a is further pulled down to the second low potential, that is, the potential of the low potential end; since the tenth transistor T41 is turned on, the second Q-point QN-b is also pulled down further to the second low potential, i.e., the potential of the low potential end. Since the inverted level is reached, the potential of the control terminal KN becomes high by the inverter 103, and the potential of the clock signal terminal CLK (N-1) input to the N-1 th stage gate driving unit changes from low to high, starting a new round of output.
It is noted that the waveforms of fig. 5 are applicable to both diode-connected and VGH-connected methods. When VGH connection is adopted, at the time T2, when the potential of the gate signal end G (N-1) of the N-1 stage gate driving unit is changed from high potential to low potential, both ends of the first transistor T11-a are high potential, no voltage difference exists, and electric leakage is avoided. At time T3, after the potential of the first Q point QN-a is further increased to the second high potential, a voltage difference exists across the first transistor T11-a, so that leakage can be performed through the first Q point QN-a, and the potential of the second node QN-b is ensured.
When diode connection is adopted, at the time T2, when the potential of the gate signal end G (N-1) of the N-1 th stage gate driving unit is changed from high potential to low potential, the voltage difference exists at the two ends of the first transistor T11-a, so that electric leakage can be carried out through the first Q point QN-a, and the potential of the second node QN-b is ensured. And at time T3, after the potential of the first Q point QN-a is further increased to the second high potential, the voltage difference between the two ends of the first transistor T11-a is further increased, and the greater the voltage difference is, the more easily a leakage path is formed, so that the leakage is still preferentially performed through the first Q point QN-a, and the potential of the second node QN-b is ensured. It can be seen that, in either connection, even if the leakage situation is extremely serious, the first Q point QN-a will leak earlier than the second Q point QN-b, so the leakage degree of the second Q point QN-b is reduced compared with the conventional gate driving unit.
In an embodiment, the first capacitor C44 and the second capacitor Cbt are both variable capacitors. By adjusting the capacitance of the first capacitor C44 and the capacitance of the second capacitor Cbt, the potential of the first Q point QN-a and the potential of the second Q point QN-b can be kept as consistent as possible, so that the first Q point QN-a serves as a buffer between the second Q point QN-b and the low potential of the source of the first transistor T11-a, leakage of the second Q point QN-b can be reduced, and the fifth transistor T21 of the pull-up unit can output a stable gate signal of the nth stage gate driving unit.
In the related art, when the pull-up control module 102 adopts the VGH method, the low-potential maintaining stage of QN has a problem that the T11 leakage causes the QN signal to fluctuate. In the present application, the voltage of the high voltage terminal VGH is only leaked to the first Q point QN-a, and the inverter 103 is only controlled by the second Q point QN-b, so that the voltage fluctuation of the first Q point QN-a does not affect the voltage of the control terminal KN. Moreover, since the stage T43 is always in the on state, the voltage fluctuation is smoothed by the VGL signal connected to the stage T43, so as to eliminate the influence of VGH leakage to the QN point on the circuit stability. In addition, when the G (N-1) stage signal turns on the first transistor T11-a and the second transistor T11-b, and the first Q point QN-a and the second Q point QN-b start to be charged from a low potential to a high potential, the fourth transistor T55 is turned on simultaneously to pull the potential of the control terminal KN low, which may weaken the potential competition of the control terminal KN with the potentials of the first Q point QN-a and the second Q point QN-b, so that the charging of the first Q point QN-a and the second Q point QN-b is more sufficient.
Fig. 5 shows a flowchart of a display panel driving method according to an embodiment of the present application. As shown in fig. 5, the display panel driving method is applied to the gate driving circuit, and includes:
step S1: at a first moment, controlling the potential of a gate signal end of the N-1 th stage gate driving unit to change from a low potential to a high potential so that a first Q point QN-a and a second Q point QN-b of the N-th stage gate driving unit are both raised to a first high potential;
At time t1, the potential of the gate signal terminal G (N-1) of the N-1 th stage gate driving unit changes from a low potential to a high potential, so that both the first transistor and the second transistor are in an on state, and thus both the first Q point and the second Q point of the N-th stage gate driving unit rise to a first high potential. Since the potential of the first Q point is identical to the potential of the second Q point, the second Q point has no leakage path, thereby suppressing leakage at the second Q point. Even if the leakage is extremely serious, the first Q point will leak earlier than the second Q point, so the leakage level of the second Q point is reduced compared with the conventional gate driving unit.
Step S2: at a second moment, controlling the potential of a gate signal end of the N-1 level gate driving unit to change from high potential to low potential, so that the potential of the first Q point and the potential of the second Q point are maintained at a first high potential;
at time t2, the potential of the gate signal terminal G (N-1) of the N-1 th stage gate driving unit changes from a high potential to a low potential, and the potential of the first Q point and the potential of the second Q point are maintained at the first high potential.
Step S3: and at a third moment, controlling the clock signal end of the N-th stage grid driving unit to change from low potential to high potential, so that the potential of the first Q point and the potential of the second Q point are coupled to second high potential, wherein the potential of the first Q point and the potential of the second Q point are consistent at the first moment, the second moment and the third moment.
At time t3, the clock signal end of the nth stage gate driving unit is changed from low potential to high potential, and the potential of the first Q point is further increased to second high potential due to the capacitive coupling effect of the first capacitor; the potential of the second Q point is further raised to a second high potential due to the capacitive coupling effect of the second capacitance Cbt.
The gate driving circuit may include a processor, and the display panel driving method may be performed by the processor. For specific details of the display panel driving method, reference may be made to the description of the structure of the gate driving unit described above, and the description is omitted.
In summary, in the embodiment of the application, two pull-up control transistors of a common gate structure are arranged in a pull-up control module, and the source electrode of one pull-up control transistor and the drain electrode of the other pull-up control transistor are electrically connected to a first Q point, the first Q point is electrically connected to a low voltage end of an nth stage gate driving unit, and the potential of the first Q point is consistent with that of a second Q point, so that the leakage degree of the Q point can be reduced, the influence of the leakage of the Q point on the output of gate signals is reduced, and the stability of the gate driving circuit in the severe leakage environments such as high temperature is improved.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The present application is capable of other and further embodiments and its several details are capable of modification and variation in accordance with the present application, as will be apparent to those skilled in the art, without departing from the spirit and essential characteristics of the application, but these are intended to cover all such modifications and variations as fall within the broad scope of the appended claims.

Claims (9)

1.一种栅极驱动电路，其特征在于，所述栅极驱动电路包括多级级联的栅极驱动单元，第N级栅极驱动单元包括：1. A gate driving circuit, characterized in that the gate driving circuit comprises a plurality of cascaded gate driving units, wherein the Nth gate driving unit comprises: 上拉模块，电连接于第二Q点，所述上拉模块用于输出第N级栅极驱动单元的栅极信号，N为正整数；A pull-up module, electrically connected to the second Q point, the pull-up module is used to output a gate signal of an N-th level gate driving unit, where N is a positive integer; 上拉控制模块，包括第一晶体管和第二晶体管，所述第一晶体管的栅极和所述第二晶体管的栅极均电连接于第N-1级栅极驱动单元的栅极信号端，第N-1级栅极驱动单元的栅极信号端用于输出第N-1级栅极驱动单元的栅极信号，所述第一晶体管的源极电连接于高电压端或第N-1级栅极驱动单元的栅极信号端，所述第一晶体管的漏极电连接于第二晶体管的源极；所述第二晶体管的栅极电连接于述第一晶体管的栅极，所述第二晶体管的漏极电连接于该第N级栅极驱动单元的第二Q点，所述第一晶体管的漏极以及所述第二晶体管的源极均电连接于第一Q点；A pull-up control module, comprising a first transistor and a second transistor, wherein the gate of the first transistor and the gate of the second transistor are both electrically connected to the gate signal terminal of the N-1th gate driving unit, the gate signal terminal of the N-1th gate driving unit is used to output the gate signal of the N-1th gate driving unit, the source of the first transistor is electrically connected to the high voltage terminal or the gate signal terminal of the N-1th gate driving unit, the drain of the first transistor is electrically connected to the source of the second transistor; the gate of the second transistor is electrically connected to the gate of the first transistor, the drain of the second transistor is electrically connected to the second Q point of the Nth gate driving unit, and the drain of the first transistor and the source of the second transistor are both electrically connected to the first Q point; 其中，所述第一Q点的电位和所述第二Q点的电位相一致。The potential of the first Q point is consistent with the potential of the second Q point. 2.根据权利要求1所述的栅极驱动电路，其特征在于，第N级栅极驱动单元的所述上拉控制模块还包括：2. The gate driving circuit according to claim 1, characterized in that the pull-up control module of the Nth stage gate driving unit further comprises: 第一电容，所述第一电容的第一端电连接于第N级栅极驱动单元输入的时钟信号端，所述第一电容的第二端电连接于所述第一Q点。A first capacitor, wherein a first end of the first capacitor is electrically connected to a clock signal end inputted by the Nth stage gate driving unit, and a second end of the first capacitor is electrically connected to the first Q point. 3.根据权利要求2所述的栅极驱动电路，其特征在于，第N级栅极驱动单元的所述上拉控制模块还包括：3. The gate driving circuit according to claim 2, wherein the pull-up control module of the Nth-stage gate driving unit further comprises: 第三晶体管，所述第三晶体管的栅极电连接于第N级栅极驱动单元的控制端，所述第三晶体管的源极电连接于低电压端，所述第三晶体管的漏极电连接于所述第一Q点。A third transistor, wherein the gate of the third transistor is electrically connected to the control end of the Nth stage gate driving unit, the source of the third transistor is electrically connected to the low voltage end, and the drain of the third transistor is electrically connected to the first Q point. 4.根据权利要求3所述的栅极驱动电路，其特征在于，第N级栅极驱动单元的所述上拉控制模块还包括：4. The gate driving circuit according to claim 3, characterized in that the pull-up control module of the Nth stage gate driving unit further comprises: 第四晶体管，所述第四晶体管的栅极电连接于第N-1级栅极驱动单元的栅极信号端，所述第四晶体管的源极电连接于低电压端，所述第四晶体管的漏极电连接于所述第三晶体管的栅极。A fourth transistor, wherein the gate of the fourth transistor is electrically connected to the gate signal terminal of the N-1th gate driving unit, the source of the fourth transistor is electrically connected to the low voltage terminal, and the drain of the fourth transistor is electrically connected to the gate of the third transistor. 5.根据权利要求4所述的栅极驱动电路，其特征在于，第N级栅极驱动单元的所述上拉模块包括：5. The gate driving circuit according to claim 4, wherein the pull-up module of the Nth stage gate driving unit comprises: 第五晶体管，所述第五晶体管的栅极电连接于所述第二Q点以及第二电容的第一端，所述第五晶体管的源极电连接于第N级栅极驱动单元的栅极信号端，第N级栅极驱动单元的栅极信号端用于输出第N级栅极驱动单元的栅极信号，所述第五晶体管的漏极电连接于时钟信号端，所述时钟信号端用于接收输入该第N级栅极驱动单元的时钟信号；a fifth transistor, wherein the gate of the fifth transistor is electrically connected to the second Q point and the first end of the second capacitor, the source of the fifth transistor is electrically connected to the gate signal end of the N-th gate driving unit, the gate signal end of the N-th gate driving unit is used to output the gate signal of the N-th gate driving unit, and the drain of the fifth transistor is electrically connected to the clock signal end, and the clock signal end is used to receive the clock signal input to the N-th gate driving unit; 第二电容，所述第二电容的第一端电连接于所述第五晶体管的栅极，所述第二电容的第二端电连接于第N级栅极驱动单元的栅极信号端。A second capacitor, wherein a first end of the second capacitor is electrically connected to the gate of the fifth transistor, and a second end of the second capacitor is electrically connected to the gate signal end of the Nth stage gate driving unit. 6.根据权利要求5所述的栅极驱动电路，其特征在于，所述第一电容和所述第二电容均为可变电容，通过调节所述第一电容的容值和所述第二电容的容值，使所述第一Q点的电位和所述第二Q点的电位保持一致。6. The gate drive circuit according to claim 5 is characterized in that both the first capacitor and the second capacitor are variable capacitors, and the potential of the first Q point and the potential of the second Q point are kept consistent by adjusting the capacitance of the first capacitor and the capacitance of the second capacitor. 7.根据权利要求5所述的栅极驱动电路，其特征在于，第N级栅极驱动单元还包括下拉模块，第N级栅极驱动单元的所述下拉模块包括：7. The gate driving circuit according to claim 5, characterized in that the N-th gate driving unit further comprises a pull-down module, and the pull-down module of the N-th gate driving unit comprises: 第十晶体管，所述第十晶体管的栅极电连接于第N+1级栅极驱动单元的栅极信号端，所述第十晶体管的源极电连接于所述低电压端，所述第十晶体管的漏极电连接于所述第二Q点；a tenth transistor, wherein a gate of the tenth transistor is electrically connected to a gate signal terminal of an N+1th gate driving unit, a source of the tenth transistor is electrically connected to the low voltage terminal, and a drain of the tenth transistor is electrically connected to the second Q point; 第十一晶体管，所述第十一晶体管的栅极电连接于第N级栅极驱动单元的的控制端，所述第十一晶体管的源极电连接于所述低电压端，所述第十一晶体管的漏极电连接于所述第二Q点。An eleventh transistor, wherein the gate of the eleventh transistor is electrically connected to the control end of the Nth-stage gate driving unit, the source of the eleventh transistor is electrically connected to the low voltage end, and the drain of the eleventh transistor is electrically connected to the second Q point. 8.一种显示面板，其特征在于，所述显示面板包括如权利要求1-7任一项所述的栅极驱动电路。8. A display panel, characterized in that the display panel comprises the gate driving circuit according to any one of claims 1 to 7. 9.一种显示面板驱动方法，其特征在于，所述显示面板驱动方法应用于如权利要求1-7任一项所述的栅极驱动电路，所述显示面板驱动方法包括：9. A display panel driving method, characterized in that the display panel driving method is applied to the gate driving circuit according to any one of claims 1 to 7, and the display panel driving method comprises: 在第一时刻，控制第N-1级栅极驱动单元的栅极信号端的电位从低电位变为高电位，以使第N级栅极驱动单元的第一Q点和第二Q点均升高至第一高电位；At a first moment, controlling the potential of the gate signal terminal of the N-1th gate driving unit to change from a low potential to a high potential, so that the first Q point and the second Q point of the Nth gate driving unit are both increased to a first high potential; 在第二时刻，控制第N-1级栅极驱动单元的栅极信号端的电位从高电位变为低电位，使所述第一Q点的电位和第二Q点的电位维持在第一高电位；At the second moment, controlling the potential of the gate signal terminal of the N-1th gate driving unit to change from a high potential to a low potential, so that the potentials of the first Q point and the second Q point are maintained at a first high potential; 在第三时刻，控制第N级栅极驱动单元的时钟信号端从低电位变为高电位，使所述第一Q点的电位以及所述第二Q点的电位被耦合至第二高电位，其中，在第一时刻、第二时刻和第三时刻，所述第一Q点的电位和所述第二Q点的电位相一致。At the third moment, the clock signal end of the Nth stage gate driving unit is controlled to change from a low potential to a high potential, so that the potential of the first Q point and the potential of the second Q point are coupled to the second high potential, wherein at the first moment, the second moment and the third moment, the potential of the first Q point and the potential of the second Q point are consistent.
CN202411139292.7A 2024-08-19 2024-08-19 Gate driving circuit, display panel and display panel driving method Pending CN118800161A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119049426A (en) * 2024-10-31 2024-11-29 惠科股份有限公司 Noise reduction voltage regulating circuit, display panel and noise reduction method
CN119446004A (en) * 2024-10-21 2025-02-14 广州华星光电半导体显示技术有限公司 Display panel and display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119446004A (en) * 2024-10-21 2025-02-14 广州华星光电半导体显示技术有限公司 Display panel and display device
CN119049426A (en) * 2024-10-31 2024-11-29 惠科股份有限公司 Noise reduction voltage regulating circuit, display panel and noise reduction method
CN119049426B (en) * 2024-10-31 2025-02-11 惠科股份有限公司 Noise reduction voltage regulation circuit, display panel and noise reduction method

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