TWI776142B - Chip on film package structure - Google Patents

Abstract

A chip on film package structure includes a flexible film, circuit structure and a chip. The flexible film has a chip bonding area. The circuit structure is disposed on the flexible film and includes a plurality of first leads, a plurality of second leads, and a plurality of third leads. Each of the first leads has a first inner lead portion and a first extension portion, and each of the second leads has a second inner lead portion and a second extension portion. The chip is disposed in a chip bonding area. The chip includes a first region, a second region, and a third region located between the first region and the second region. The chip has a plurality of first bumps located in the first region, a plurality of second bumps located in the second region and a plurality of third bumps located in the third region. The first bumps, the second bumps, and the third bumps are arranged along an edge of the chip, and respectively connect the first inner lead portions, the second inner lead portions, and the third leads. The first inner lead portions extend obliquely from the first region through the edge of the chip and connect the first extension portions at first bending points, the second inner lead portions extend obliquely from the second region through the edge and connect the second extension portions at second extension points, and the third leads extend outward from the third region passing orthogonal to the edge.

Description

Chip-on-Film Package Structure

The present invention relates to a package structure, and more particularly, to a chip on film package structure.

In the chip-on-film structure, the inner lead bonding (ILB) usually utilizes thermocompression bonding technology to produce eutectic bonding between the leads on the flexible film and the bumps on the wafer at high temperature. Further, due to the different thermal expansion coefficients of the flexible film and the chip, the flexible film shrinks to a greater extent when exposed to heat, and the shrinkage will cause the pins to shift from the original design position to the central pin, and the further to the two sides of the chip. The greater the deviation of the pins on the side (ie both ends of the chip length), the design of the pins will add compensation values to the setting positions of the pins from the center pin to the two sides, and the compensation values will be from the center to the two sides. The sides are gradually enlarged so that all pins can still be smoothly aligned with the bumps when the flexible film shrinks.

However, as the chip size increases, the effect of the shrinkage of the flexible film is intensified. Even with the compensation value, the pins close to the two sides of the chip may still have misalignment due to the difference in the width of the pins, resulting in lead Problems with poor engagement between feet and bumps. Therefore, how to effectively suppress the expansion and contraction of the flexible film, reduce the alignment error between the pins and the bumps, and further improve the problem of poor bonding between the pins and the bumps has become an urgent problem to be solved at present. subject.

The invention provides a film-on-chip package structure, which can effectively restrain the expansion and contraction of the flexible film, reduce the alignment error between the pins and the bumps, and further improve the poor bonding between the pins and the bumps. question.

A film-on-chip packaging structure of the present invention includes a flexible film, a circuit structure and a chip. The flexible film has a die bond area. The circuit structure is arranged on the flexible film and includes a plurality of first pins, a plurality of second pins and a plurality of third pins. Each of the first pins has a first inner pin part and a first extension part, and each of the second pins has a second inner pin part and a second extension part. The wafer is disposed in the wafer bonding area. The wafer includes a first area, a second area, and a third area located between the first area and the second area, and has a plurality of first bumps located in the first area and a plurality of second bumps located in the second area The bump and a plurality of third bumps located in the third area. The first bump, the second bump and the third bump are adjacently arranged along the edge of the wafer, and are respectively connected to the first inner pin part, the second inner pin part and the third pin. The first inner lead portion extends obliquely through the edge of the chip from the first area and is connected to the first bending point with the first extension portion, and the second inner lead portion extends obliquely from the second area through the edge and is connected with the first bending point. The second extension portion is connected to the second bending point, and the plurality of third pins extend from orthogonal edges in the third area and extend outward.

In an embodiment of the present invention, the first bump and the second bump extend obliquely along the extending directions of the first inner lead portion and the second inner lead portion, respectively.

In an embodiment of the present invention, the first bending point and the second bending point are located outside the coverage of the wafer and have a gap with the edge of the wafer.

In an embodiment of the present invention, the above-mentioned gap is not less than 30 microns.

In an embodiment of the present invention, the above-mentioned first inner lead portion extends obliquely from the first area to a direction away from the third lead, and the second inner lead portion extends away from the third lead from the second area. The direction of the feet extends diagonally.

In an embodiment of the present invention, the first inner pin portion and the edge form a first included angle, the second inner pin portion and the edge form a second included angle, and the first included angle and the second included angle are greater than zero degrees and less than ninety degrees Spend.

In an embodiment of the present invention, the above-mentioned chip on film package structure further includes a solder mask layer. The solder resist layer is arranged on the flexible film, partially covers the circuit structure, and exposes the chip bonding area.

In an embodiment of the present invention, the above-mentioned solder mask exposes a first bending point and a second bending point.

In an embodiment of the present invention, the above-mentioned chip on film packaging structure further includes an encapsulant. The encapsulant is filled between the chip and the flexible film and covers the chip bonding area.

In an embodiment of the present invention, the above-mentioned encapsulant covers the first bending point and the second bending point.

Based on the above, the lead (the first lead and the second lead) of the present invention can expand and suppress the flexibility by the oblique design of the inner lead part (the first inner lead part and the second inner lead part) The influence range of film expansion and contraction can effectively suppress the expansion and contraction range of the flexible film, reduce the error in the alignment between the pins and the bumps, and further improve the problem of poor bonding between the pins and the bumps.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

FIG. 1 is a schematic top view of a chip on film packaging structure according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of area A of FIG. 1 . Figure 3 is a schematic diagram of a comparison between oblique pins and straight pins. FIG. 4 is a schematic diagram showing a comparison between the oblique bump and the straight bump and pin bonding. For the sake of clarity, the chip 130 , the first bump 131 , the second bump 132 , the third bump 133 and the encapsulant 150 in FIGS. 1 and 2 are represented by perspective drawing.

Please refer to FIG. 1 and FIG. 2 at the same time. In this embodiment, the chip on film package structure 100 includes a flexible film 110 , a circuit structure 120 and a chip 130 . Further, the flexible film 110 has a die bonding area 112 , the chip 130 is disposed in the die bonding area 112 , and the circuit structure 120 is disposed on the flexible film 110 .

The material of the flexible film 110 is, for example, polyimide (PI), polyethylene terephthalate (PET), polyethersulfone (PES), carbonate (polycarbonate, PC) or Other suitable flexible materials, so the chip on film package structure 100 using the flexible film 110 has flexibility.

The circuit structure 120 includes a plurality of first pins 121 , a plurality of second pins 122 and a plurality of third pins 123 , wherein each of the first pins 121 has a first inner pin part 1211 and a first extension part 1212 , Each of the second pins 122 has a second inner pin portion 1221 and a second extension portion 1222 . The material of the circuit structure 120 is, for example, copper or other suitable metals.

The wafer 130 includes a first area A1, a second area A2 and a third area A3 located between the first area A1 and the second area A2, wherein the wafer 130 has a plurality of first bumps 131, The plurality of second bumps 132 in the second area A2 and the plurality of third bumps 133 in the third area A3. In addition, the first bumps 131 , the third bumps 133 and the second bumps 132 are adjacently arranged along an edge E of the wafer 130 and are respectively connected to the first inner lead portion 1211 , the third lead 123 and the Two inner pin parts 1221 . In other words, the first inner lead portion 1211 , the third lead portion 123 and the second inner lead portion 1221 are also arranged adjacent to each other along the edge E of the wafer 130 . For example, the wafer 130 has two opposite short sides and two opposite long sides, and the first bump 131 , the third bump 133 and the second bump 132 may be opposite along the wafer 130 , respectively. The edges E of the two long side sides are arranged adjacently.

In this embodiment, the first inner lead portion 1211 extends obliquely from the first area A1 through the edge E of the wafer 130 and is connected with the first extension portion 1212 at the first bending point B1, and the second inner lead portion 1221 extends obliquely through the edge E from the second area A2 and is connected to the second bending point B2 with the second extension 1222 , and a plurality of third pins 123 extend from the third area A3 to the orthogonal edge E and outwards extend. The present invention can effectively restrain the expansion and contraction of the flexible film 110 by the oblique design of the first inner pin portion 1211 and the second inner pin portion 1221 . In detail, as shown in FIG. 3 , the first pin 121 and the first bump 131 are taken as an example in FIG. 3 . The first pin 121 in this embodiment is designed with the first inner pin portion 1211 obliquely designed. , so that the influence range AR2 of the first inner pin portion 1211 to suppress the expansion and contraction of the flexible film 110 is larger than the influence range AR1 formed by the straight pins 10 , so that a better expansion and contraction suppression effect can be achieved, effectively Therefore, the expansion and contraction of the flexible film 110 is effectively restrained, and the degree of deflection of the first inner pin portion 1211 is reduced, thereby avoiding the alignment error between the first pin 121 and the first bump 131, and improving the first pin portion 1211. The problem of poor bonding between the feet 121 and the first bumps 131 .

In one embodiment, the first bending point B1 and the second bending point B2 are located outside the coverage C of the wafer 130 and may have a gap with the edge E of the wafer 130 . For example, there is a gap G1 between the first bending point B1 and the edge E of the wafer 130 , and there is a gap G2 between the second bending point B2 and the edge E of the wafer 130 . Further, when the gaps (the gap G1 and the gap G2) are small, the bending points (the first bending point B1 and the second bending point B2) are closer to the die bonding area 112, which is easy to cause the pins (the first bending point B1 and the second bending point B2) to be close to the die bonding area 112. The leg 121 and the second lead 122) are broken at the bending point (the first bending point B1 and the second bending point B2) due to the force when they are joined, so the gap (the gap G1 and the gap G2) is, for example, Not less than 30 microns, in order to reduce the probability of the lead (the first lead portion 121 and the second lead 122 ) being easily broken due to force during bonding, thereby improving the reliability of the film-on-chip package structure 100, but this The invention is not limited to this. In addition, the gap G1 and the gap G2 may be the same. Therefore, the first bending point B1 and the second bending point B2 may be aligned on both sides of the wafer 130 , but the invention is not limited thereto. The gap G1 and the gap G2 can be determined according to actual design requirements.

In one embodiment, the first inner pin portion 1211 may extend obliquely from the first area A1 in a direction away from the third pin 123 , and the second inner pin portion 1221 may extend away from the second area A2 The direction of the third pin 123 extends obliquely. In other words, one end of the first inner lead portion 1211 inside the first area A1 may be closer to the third lead 123 than the other end of the first inner lead portion 1211 outside the first area A1, while the second inner lead portion 1211 may be closer to the third lead 123 than the other end of the first inner lead portion 1211 outside the first area A1. One end of the lead portion 1221 located in the second area A2 may be closer to the third lead 123 than the other end of the second inner lead portion 1221 located outside the second area A2.

In addition, the first bumps 131 and the second bumps 132 may extend obliquely in accordance with the extending directions of the first inner pin portion 1211 and the second inner pin portion 1221 , respectively. In other words, the extending direction of the first bump 131 may be parallel to the extending direction of the first inner pin portion 1211 , and the extending direction of the second bump 132 may be parallel to the extending direction of the second inner pin portion 1221 . Therefore, as shown in FIG. 4 , the first pin 121 and the first bump 131 are used as an example in FIG. 4 . The bonding area AR4 between the obliquely extending first bump 131 and the offset first pin 121 is larger than the bonding area AR3 between the straight bump 20 and the offset first pin 121, that is, That is to say, the first bump 131 and the second bump 132 of the present embodiment are arranged obliquely in accordance with the extending directions of the first inner pin portion 1211 and the second inner pin portion 1221 respectively, even if the first pin 121 and the second inner pin portion 1221 are obliquely arranged When the pins 122 are offset during bonding, a sufficient bonding area can still be maintained between the first bump 131 and the first pin 121 and between the second bump 132 and the second pin 122 to ensure the inner pin Bonding quality.

In one embodiment, the first inner pin portion 1211 and the edge E form a first included angle θ1, the second inner pin portion 1221 and the edge E form a second included angle θ2, and the first included angle θ1 and the second included angle θ2 are greater than zero degrees and less than ninety degrees. In other words, the edges E of the first inner pin portion 1211 and the second inner pin portion 1221 are not orthogonal or parallel. For example, the first included angle θ1 and the second included angle θ2 are preferably 45°, but the present invention does not limit the angle between the first included angle θ1 and the second included angle θ2, which may be determined according to actual design requirements.

In one embodiment, since the deviation of the pins is more serious toward the two sides of the wafer 130 , in order to suppress the expansion and contraction of the flexible film 110 in these areas, the first pins 121 and the second pins 122 The distribution range of A1 and A2 may respectively occupy one third of the length of the wafer 130 , that is, the first area A1 and the second area A2 respectively occupy one third of the length of the wafer 130 , but the invention is not limited thereto. The distribution range of the first pins 121 and the second pins 122 can be adjusted according to actual design requirements.

In one embodiment, in order to maintain good electrical properties of the circuit structure 120 , the chip on film package structure 100 may further include a solder resist layer 140 . The solder mask layer 140 may be disposed on the flexible film 110 to partially cover the circuit structure 120 and expose the die bonding area 112 . Further, the solder mask 140 has an opening 142 , and the die bonding area 112 is substantially defined by the opening 142 of the solder mask 140 . In one embodiment, the solder mask layer 140 may expose the first bending point B1 and the second bending point B2.

In one embodiment, in order to avoid the intrusion of moisture and contamination, the chip on film package structure 100 may further include an encapsulant 150 . In particular, the encapsulant 150 in FIG. 1 and FIG. 2 is presented by a perspective drawing method, so only a general distribution range of the encapsulant 150 is shown in a frame. The encapsulant 150 can be filled between the chip 130 and the flexible film 110 and cover the die bonding area 112 . In one embodiment, the encapsulant 150 can cover the first bending point B1 and the second bending point B2. In other words, the first inflection point B1 and the second inflection point B2 do not exceed the edge of the encapsulant 150 .

To sum up, the pins (the first pin and the second pin) of the present invention can be enlarged and suppressed by the oblique design of the inner pin parts (the first inner pin part and the second inner pin part) The influence range of the expansion and contraction of the flexible film can effectively suppress the expansion and contraction of the flexible film, reduce the error in the alignment between the pins and the bumps, and improve the poor bonding between the pins and the bumps. question. In addition, the present invention can make the inner lead part (the first inner lead part and the second inner lead part) and the bump (the first inner lead part) and the bump (the first inner lead part) and the bump (the first Maintain sufficient bonding area between the bump and the second bump) to ensure that when the pins (the first pin and the second pin) are offset, they can still contact the bumps (the first bump and the second bump) ) Smoothly aligned joints to ensure the quality of the inner pin joints.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Straight pins 20: Straight bump 100: Thin film flip chip package structure 110: Flexible film 112: Wafer bonding area 120: Line Structure 121: the first pin 1211: The first inner pin part 1212: First extension 122: the second pin 1221: Second inner pin part 1222: Second extension 123: The third pin 130: Wafer 131: First bump 132: Second bump 133: Third bump 140: Solder mask 142: Opening 150: encapsulating colloid A: area A1: District 1 A2: The second area A3: The third district AR1, AR2: sphere of influence AR3, AR4: Area B1: The first bending point B2: The second bending point C: Coverage D: direction E: edge G1, G2: Gap θ1: the first angle θ2: Second included angle

FIG. 1 is a schematic top view of a chip on film packaging structure according to an embodiment of the present invention. FIG. 2 is an enlarged schematic view of area A of FIG. 1 . Figure 3 is a schematic diagram of a comparison between oblique pins and straight pins. FIG. 4 is a schematic diagram showing a comparison between the oblique bump and the straight bump and pin bonding.

100: Thin film flip chip package structure

110: Flexible film

112: Wafer bonding area

120: Line Structure

121: the first pin

1211: The first inner pin part

1212: First extension

122: the second pin

1221: Second inner pin part

1222: Second extension

123: The third pin

130: Wafer

131: First bump

132: Second bump

133: Third bump

140: Solder mask

142: Opening

150: encapsulating colloid

A: area

A1: District 1

A2: The second area

A3: The third district

B1: The first bending point

B2: The second bending point

C: Coverage

E: edge

Claims (10)

A film-on-chip packaging structure, comprising: a flexible film having a chip bonding area; a circuit structure disposed on the flexible film and comprising a plurality of first pins, a plurality of second pins and a plurality of a third pin, wherein each of the first pins has a first inner pin part and a first extension part, and each of the second pins has a second inner pin part and a second extension part; and a chip, provided In the wafer bonding area, the wafer includes a first area, a second area, and a third area located between the first area and the second area, and has a plurality of areas located in the first area. a plurality of first bumps, a plurality of second bumps in the second area, and a plurality of third bumps in the third area, the plurality of first bumps, the plurality of first bumps Two bumps and the plurality of third bumps are adjacently arranged along an edge of the wafer, and are respectively connected to the plurality of first inner lead portions, the plurality of second inner lead portions and the the plurality of third pins; wherein the first inner pin portion extends obliquely through the edge of the wafer from the first area and is connected to the first bending portion with the first extension portion point, the first extension portion partially extends from the first bending point along the direction orthogonal to the edge and away from the die bonding area, and the second inner lead portion extends from the second area extending obliquely across the edge and connecting with the second extension at a second bending point, the second extension partially extending from the second bending point along the edge perpendicular to the edge and facing away from the wafer The direction of the bonding area extends, and the plurality of third pins extend from the third area perpendicular to the edge and extend outward. The thin film flip chip package structure of claim 1, wherein the plurality of first bumps and the plurality of second bumps conform to the plurality of first inner lead portions and the plurality of second bumps, respectively The extending direction of the inner pin portion extends obliquely. The chip on film package structure of claim 1, wherein the first bending point and the second bending point are located outside the coverage of the wafer and between the edge of the wafer with gaps. The chip on film package structure of claim 3, wherein the gap is not less than 30 microns. The chip on film package structure of claim 1, wherein the first inner lead portion extends obliquely from the first area in a direction away from the plurality of third leads, and the second inner lead portion extends obliquely in a direction away from the plurality of third leads. The lead portion extends obliquely from the second area in a direction away from the plurality of third leads. The chip on film package structure according to claim 1, wherein the first inner lead portion forms a first included angle with the edge, the second inner lead portion forms a second included angle with the edge, and the The first included angle and the second included angle are greater than zero degrees and less than ninety degrees. The chip-on-film package structure according to claim 1, further comprising a solder resist layer disposed on the flexible film, the solder resist layer partially covering the circuit structure and exposing the die bonding area. The chip on film package structure of claim 7, wherein the solder mask layer exposes the first bending point and the second bending point. The chip-on-film packaging structure of claim 1, further comprising an encapsulant, which is filled between the chip and the flexible film and covers the chip bonding area. The chip-on-film packaging structure of claim 9, wherein the encapsulant covers the first bending point and the second bending point.

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