TWI847422B - Chip on film package structure - Google Patents

Abstract

A chip on film package structure includes a chip and a flexible circuit substrate. The chip includes first bumps and second bumps. The flexible circuit substrate includes a flexible base and an upper circuit. The upper circuit includes first leads and second leads arranged along a first edge of a chip bonding area corresponding to a long side of the chip. The first leads are bonded to the first bumps. The second leads are bonded to the second bumps. The chip bonding area includes a first bonding area and a second bonding area adjacent to the first edge. At least one of the first leads located in the first bonding area is a first detection lead. A first gap between the first detection lead and the adjacent second bump is substantially equal to a minimum of the first gaps between the first leads and the second bumps in the second bonding area.

Description

Chip-on-film packaging structure

The present invention relates to a chip-on-film packaging structure.

With the improvement of semiconductor technology, LCD displays have the advantages of low power consumption, light weight, high resolution, high color saturation, and long life. Therefore, they are widely used in mobile phones, LCD screens of laptops or desktop computers, LCD TVs and other electronic products closely related to life. Among them, the driver chip (driver IC) of the display is an indispensable and important component of the LCD display. In response to the needs of various applications of LCD driver chips, tape automatic bonding (TAB) packaging technology is generally used for chip packaging. Chip-On-Film (COF) packaging structure is one of the packaging structures that uses tape automatic bonding technology.

The Chip-On-Film packaging structure is a packaging technology that achieves electrical connection by bonding the chip to the pins on the flexible circuit substrate through conductive bumps, among which inner lead bonding (ILB) is a very critical process. Since the number of pins in the Chip-On-Film packaging structure is large and the layout is quite dense, and the chip has a narrow and long appearance, if one or some of the pins accidentally contact the adjacent conductive bumps due to position offset, it may cause electrical failure of the Chip-On-Film packaging structure. Therefore, how to detect whether the pins accidentally contact the bumps to ensure the overall inner lead bonding quality is a topic that urgently needs to be studied.

The present invention provides a thin film flip chip packaging structure, which can detect whether there is a deviation in the inner pin bonding process through a first detection pin simulating the minimum value of the gap between the pin and the adjacent bump.

At least one embodiment of the present invention provides a thin film chip-on-chip packaging structure. The thin film chip-on-chip packaging structure includes a chip and a flexible circuit substrate. The chip includes a plurality of first bumps and a plurality of second bumps. The first bumps and the second bumps are respectively adjacent to and arranged in two rows along the long side of the chip, wherein the first bumps are farther from the long side of the chip than the second bumps. The chip is bonded to the chip bonding area of the flexible circuit substrate. The flexible circuit substrate includes a flexible substrate and an upper circuit. The flexible substrate has a first surface and a second surface relative to each other. The chip bonding area is located on the first surface. The upper circuit is arranged on the first surface of the flexible substrate. The upper circuit includes a plurality of first pins and a plurality of second pins arranged along the first edge of the chip bonding area corresponding to the long side of the chip. The first pin is bonded to the first bump. The second pin is bonded to the second bump. The chip bonding area includes a first bonding area adjacent to the first edge and a second bonding area. The lateral distance between the first bump corresponding to the first bonding area and the adjacent second bump is greater than the lateral distance between the first bump corresponding to the second bonding area and the adjacent second bump. There is a first gap parallel to the first edge between each first pin and the adjacent second bump. At least one of the first pins located in the first bonding area is a first detection pin. The first gap between the first detection pin and the adjacent second bump is substantially equal to the minimum value of multiple first gaps between multiple first pins and multiple second bumps located in the second bonding area.

Based on the above, by setting a detection pin in an area where the pins and bumps are relatively sparsely arranged (such as a corner near the chip bonding area), and making the gap between the detection pin and the adjacent bump equal to the minimum value of multiple gaps between multiple pins and adjacent bumps in an area where the pins and bumps are relatively densely arranged, by checking whether the detection pin and the adjacent bump are short-circuited, it can be inferred whether the pins and adjacent bumps in other areas have a false contact problem. Therefore, when executing the procedure of inspecting the bonding condition of the pins, personnel or machines only need to inspect the inspection pins located in a fixed area, without having to specifically search for pins and bumps with the minimum gap in other areas, thereby significantly shortening the operation time of the inspection procedure.

FIG. 1 is a schematic top view of a chip-on-film package structure 1 according to an embodiment of the present invention. Referring to FIG. 1 , the chip-on-film package structure 1 includes a chip 10 and a flexible circuit substrate 20. The flexible circuit substrate 20 includes a flexible base 22, an upper circuit 24, and an upper solder-proof layer 27. The upper circuit 24 in FIG. 1 is only used for illustration, and the specific circuit layout of the upper circuit 24 can be adjusted according to actual needs. The chip-on-film package structure 1 may further include a packaging gel filled between the chip 10 and the flexible circuit substrate 20. In FIG. 1 , the chip 10 is shown in a perspective manner, and the packaging gel is omitted.

The flexible substrate 22 has a first surface 22a and a second surface 22b opposite to each other. The upper circuit 24 and the upper solder-proof layer 27 are arranged on the first surface 22a of the flexible substrate 22, wherein the upper solder-proof layer 27 partially covers the upper circuit 24 and exposes the chip bonding area 200 located on the first surface 22a of the flexible substrate 22. The upper circuit 24 extends from the chip bonding area 200 to both ends of the flexible substrate 22. The chip 10 is bonded to the chip bonding area 200 of the flexible circuit substrate 20. In this embodiment, the appearance of the chip 10 is narrow and long, that is, its length and width vary greatly. Most of the upper circuits 24 extend outward from the chip bonding area 200 through the long side of the chip 10.

FIG2A is a partially enlarged top view schematic diagram of the chip bonding area 200 of the flexible circuit substrate 20 of FIG1. In FIG2A, the chip 10 is shown in a perspective manner, thereby showing the bonding state of the upper circuit 24 on the first surface 22a of the flexible substrate 22 and the bump of the chip 10. FIG2B is a bottom view schematic diagram of the flexible circuit substrate 20 of FIG1 corresponding to the chip bonding area 200 of FIG2A. FIG2C is a cross-sectional schematic diagram along the line A-A' of FIG2A.

2A , the chip 10 includes a plurality of first bumps 12 and a plurality of second bumps 14. The first bumps 12 and the second bumps 14 are respectively adjacent to and arranged in two rows along the long side 10a of the chip 10. The first bumps 12 are farther from the long side 10a of the chip 10 than the second bumps 14. In other words, the plurality of first bumps 12 are arranged in a row relatively far from the long side 10a along the extension direction D1 of the long side 10a, and the plurality of second bumps 14 are arranged in a row relatively close to the long side 10a along the extension direction D1 of the long side 10a.

The upper circuit 24 includes a plurality of first pins 242 and a plurality of second pins 244 arranged along the first edge 200a of the chip bonding area 200 corresponding to the long side 10a of the chip 10. The first pins 242 are bonded to the first bumps 12. The second pins 244 are bonded to the second bumps 14. The first pins 242 and the second pins 244 are alternately arranged in the extension direction D1 of the long side 10a.

The chip bonding area 200 includes a first bonding area 202 adjacent to the first edge 200a and a second bonding area 204, and the first bonding area 202 is closer to the corner of the chip bonding area 200 than the second bonding area 204. In this embodiment, there are two first bonding areas 202 and one second bonding area 204, and the two first bonding areas 202 are respectively located on both sides of the second bonding area 204 and are respectively close to two opposite corners of the chip bonding area 200. Generally speaking, the bumps of the chip 10 and the pins of the flexible circuit substrate 20 are arranged sparsely at the corners of the chip bonding area 200, and are arranged densely in the middle area of the chip bonding area 200. That is, the pitch of the bumps and the pitch of the pins are usually designed to be larger at the corners of the chip bonding area 200 than in the middle area. Specifically, in this embodiment, the lateral distance X1 between the first bump 12 and the adjacent second bump 14 corresponding to the first bonding area 202 is greater than the lateral distance X2 between the first bump 12 and the adjacent second bump 14 corresponding to the second bonding area 204. The lateral distances X1 and X2 are the distances from the center of the first bump 12 to the center of the second bump 14 in the direction parallel to the long side 10a of the chip 10 (i.e., the extension direction D1).

A first gap EG1 parallel to the first edge 200a is formed between each first pin 242 and the adjacent second bump 14. The first gap EG1 is the minimum distance from the edge of the first pin 242 to the edge of the adjacent second bump 14 in a direction parallel to the first edge 200a. In this embodiment, a plurality of first gaps EG1 of different sizes are generated between a plurality of first pins 242 and the adjacent second bump 14. Since the lateral distance X1 between the first bump 12 and the adjacent second bump 14 corresponding to the first bonding area 202 is greater than the lateral distance X2 between the first bump 12 and the adjacent second bump 14 corresponding to the second bonding area 204, the multiple first gaps EG1 generated between the multiple first pins 242 and the adjacent second bumps 14 are usually larger in the first bonding area 202 than in the second bonding area 204. During the inner pin bonding process of bonding the chip 10 to the chip bonding area 200 by heat pressing, the flexible substrate 22 is easily expanded or contracted due to temperature changes, so that the first pin 242 and the second pin 244 located in the chip bonding area 200 are offset relative to the corresponding first bump 12 and the second bump 14, resulting in miscontact or poor bonding. When the first gap EG1 between the first pin 242 and the adjacent second bump 14 is smaller, the first pin 242 and the adjacent second bump 14 are more likely to short-circuit due to pin offset.

Generally speaking, when detecting the connection status between the pin and the bump, if the first pin 242 and the second bump 14 corresponding to the smallest first gap EG1 do not short-circuit each other due to pin offset, it can be reasonably inferred that other first pins 242 and adjacent second bumps 14 with equal or larger first gaps EG1 will not short-circuit each other.

In the present embodiment, at least one of the first pins 242 located in the first bonding area 202 is a first detection pin 242a. For example, the structural design of the first detection pin 242a is adjusted so that the first gap EG1a between the first detection pin 242a and the adjacent second bump 14 is substantially equal to the minimum value minEG1 of the plurality of first gaps EG1 between the plurality of first pins 242 and the plurality of second bumps 14 located in the second bonding area 204. Since the pin offset generated near the corner of the chip bonding area 200 is more obvious than the pin offset in the middle area of the chip bonding area 200, that is, in the present embodiment, the pin offset in the first bonding area 202 is greater than the pin offset in the second bonding area 204. Therefore, when the first detection pin 242a and the adjacent second bump 14 in the first bonding area 202 with a larger pin offset are not short-circuited due to the pin offset, it can be reasonably inferred that the first pin 242 and the adjacent second bump 14 with the smallest first gap EG1 between the two in the second bonding area 204 are also not short-circuited, and further inferred that the overall bonding condition of the pin and the bump adjacent to the first edge 200a is good. Therefore, when executing the procedure of inspecting the bonding condition of the pins, personnel or an automated optical inspection (AOI) machine only need to inspect the first inspection pin 242a of the first bonding area 202 located near the corner of the chip bonding area 200, without specifically searching for the position of the minimum value minEG1 of the first gap EG1 in the second bonding area 204. By inspecting a fixed area (i.e., the corner of the chip bonding area 200), the operation time of the inspection procedure can be greatly shortened.

In the present embodiment, the first detection pin 242a includes a first joint portion 242a1 and a first main body portion 242a2 connected to the first joint portion 242a1. The first joint portion 242a1 is connected to the first bump 12. The first main body portion 242a2 extends between two adjacent second bumps 14, and the width W2 of the first main body portion 242a2 is greater than the width W1 of the first joint portion 242a1. In the present embodiment, the first main body portion 242a2 has a groove 242h, which is located between the two adjacent second bumps 14 and separates the first main body portion 242a2 into two first sub-main bodies. By adjusting the width of the first main body 242a2, the first gap EG1a between the first detection pin 242a and the adjacent second bump 14 can be adjusted to be equal to the minimum value minEG1 of the plurality of first gaps EG1 between the plurality of first pins 242 and the plurality of second bumps 14 in the second bonding area 204, so as to simulate the highest risk of misbonding in the second bonding area 204. In this embodiment, since the first main body 242a2 forms a first sub-main body with a line width close to that of the first bonding portion 242a1 through the groove 242h, the problem of uneven heat energy distribution caused by the large width/area difference between the first main body 242a2 and the first bonding portion 242a1 can be avoided.

In this embodiment, the chip further includes a plurality of third bumps 16 and a plurality of fourth bumps 18. The third bumps 16 and the fourth bumps 18 are respectively adjacent to and arranged in two rows along the short side 10b of the chip 10. The third bumps 16 are farther from the short side 10b of the chip 10 than the fourth bumps 18. In other words, the plurality of third bumps 16 are arranged in a row relatively far from the short side 10b along the extension direction D2 of the short side 10b, and the plurality of fourth bumps 18 are arranged in a row relatively close to the short side 10b along the extension direction D2 of the short side 10b.

The upper circuit 24 further includes a plurality of third leads 246 and a plurality of fourth leads 248 arranged along the second edge 200b of the chip bonding area 200 corresponding to the short side 10b. The third lead 246 is bonded to the third bump 16. The fourth lead 248 is bonded to the fourth bump 18. The third lead 246 and the fourth lead 248 are alternately arranged in the extension direction D2 of the short side 10b.

The chip bonding area 200 includes a third bonding area 206 adjacent to the second edge 200b and a fourth bonding area 208. In the present embodiment, the longitudinal distance X3 between the third bump 16 corresponding to the third bonding area 206 and the adjacent fourth bump 18 is greater than the longitudinal distance X4 between the third bump 16 corresponding to the fourth bonding area 208 and the adjacent fourth bump 18. The longitudinal distances X3 and X4 are the distances from the center of the third bump 16 to the center of the fourth bump 18 in the direction parallel to the short side 10b of the chip 10 (i.e., the extension direction D2).

A second gap EG2 parallel to the second edge 200b is formed between each third pin 246 and the adjacent fourth bump 18. The second gap EG2 is the minimum distance from the edge of the third pin 246 to the edge of the adjacent fourth bump 18 in a direction parallel to the second edge 200b. In this embodiment, a plurality of second gaps EG2 of different sizes are generated between a plurality of third pins 246 and the adjacent fourth bump 18. Since the longitudinal distance X3 between the third bump 16 corresponding to the third bonding area 206 and the adjacent fourth bump 18 is greater than the longitudinal distance X4 between the third bump 16 corresponding to the fourth bonding area 208 and the adjacent fourth bump 18, the multiple second gaps EG2 generated between the multiple third pins 246 and the adjacent fourth bump 18 are generally larger in the third bonding area 206 than in the fourth bonding area 208.

In this embodiment, at least one of the third pins 246 in the third bonding region 206 is a second detection pin 246a. For example, the second detection pin 246a is structurally designed so that the second gap EG2a between the second detection pin 246a and the adjacent fourth bump 18 is substantially equal to the minimum value minEG2 of the second gaps EG2 between the third pins 246 and the fourth bumps 18 in the fourth bonding region 208. Therefore, when the second detection pin 246a and the adjacent fourth bump 18 in the third bonding area 206 are not short-circuited due to the pin offset, it can be reasonably inferred that the third pin 246 and the adjacent fourth bump 18 with the smallest second gap EG2 between the two in the fourth bonding area 208 are also not short-circuited, and further inferred that the overall bonding condition of the pin and the bump adjacent to the second edge 200b is good. In the third bonding area 206 where the pins and bumps are relatively sparsely arranged, the second detection pin 246a is set at a position that is convenient for detection. Therefore, when executing the procedure for detecting the pin bonding status, personnel or machines only need to detect the second detection pin 246a, and there is no need to specifically search for the position where the minimum value minEG2 of the second gap EG2 is located in the fourth bonding area 208, thereby greatly shortening the operation time of the detection procedure.

In the present embodiment, the second detection pin 246a includes a second joint portion 246a1 and a second main body portion 246a2 connected to the second joint portion 246a1. The second joint portion 246a1 is connected to the third protrusion 16. The second main body portion 246a2 extends between two adjacent fourth protrusions 18. In the present embodiment, the second main body portion 246a2 has a groove 246h, which is located between the two adjacent fourth protrusions 18 and separates the second main body portion 246a2 into two second sub-main bodies. In the present embodiment, the structure of the second detection pin 246a is the same as that of the first detection pin 242a, and the detailed description of the second detection pin 246a is not repeated here.

In some embodiments, the first detection pin 242a and the second detection pin 246a include dummy pins. In other words, the first detection pin 242a and the second detection pin 246a are not used to transmit signals.

2B and 2C , the flexible circuit substrate 20 further includes a lower circuit 26 and a lower solder barrier layer 28, which are disposed on the second surface 22b of the flexible substrate 22, wherein the lower solder barrier layer 28 covers the lower circuit 26. In this embodiment, most of the first pin 202, the second pin 204, the third pin 206, and the fourth pin 208 overlap the lower circuit 26. By disposing the lower circuit 26, the first pin 202, the second pin 204, the third pin 206, and the fourth pin 208 can be provided with a supporting effect in the inner pin bonding process, thereby improving the yield of the inner pin bonding process.

In this embodiment, the lower circuit 26 has a first unwired area 26a and a second unwired area 26b, and no circuit pattern is set in the first unwired area 26a and the second unwired area 26b. The first unwired area 26a corresponds to a portion of the first bonding area 202 and exposes a portion of the second surface 22b corresponding to the first detection pin 242a and the adjacent second bump 14. The second unwired area 26b corresponds to a portion of the third bonding area 206 and exposes a portion of the second surface 22b corresponding to the second detection pin 246a and the adjacent fourth bump 18. In other words, the first detection pin 242a and the second detection pin 246a do not overlap the lower circuit 26 at least partially. Based on the design of the first unwired area 26a and the second unwired area 26b, it is possible to detect whether a short circuit occurs between the first detection pin 242a and the adjacent second bump 14 and between the second detection pin 246a and the adjacent fourth bump 18 through automatic optical detection from the second surface 22b of the flexible substrate 22. Since the unwired area of the lower circuit 26 cannot provide good support when the chip 10 is bonded to the upper circuit 24, and may affect the inner pin bonding condition, the location selection of the unwired area of the lower circuit 26 is quite limited in the area where the pins of the upper circuit 24 are more densely arranged, and it may not necessarily correspond to the position where the minimum value minEG1 of the first gap EG1 and the minimum value minEG2 of the second gap EG2 are located. However, in this embodiment, the first unwired area 26a and the second unwired area 26b respectively correspond to the first bonding area 202 and the third bonding area 206 where the pins and bumps of the upper circuit 24 are relatively sparsely arranged, thereby reducing the impact of the unwired area on the inner pin bonding, and the location selection of the unwired area is also relatively flexible.

Please refer to Figure 2C. In this embodiment, the lower solder mask 28 has a plurality of openings 28a, and the openings 28a correspond to the first unwired area 26a and the second unwired area 26b, respectively. By exposing the portions of the flexible substrate 22 corresponding to the first unwired area 26a and the second unwired area 26b, the visibility of the first detection pin 242a and the second detection pin 246a on the second surface 22b of the flexible substrate 22 is improved, so as to facilitate the detection process.

In some embodiments, the lower solder barrier layer 28 may not have the opening 28a, that is, the lower solder barrier layer 28 covers the first unwired area 26a and the second unwired area 26b. The present invention does not limit whether the lower solder barrier layer 28 covers the first unwired area 26a and the second unwired area 26b, as long as the personnel and the machine can identify the positional relationship between the first detection pin 242a and the second detection pin 246a and the adjacent bumps through the second surface 22b of the flexible substrate 22.

Referring to FIG. 2C again, the chip-on-film package structure 1 further includes a packaging gel 11, which is at least filled between the chip 10 and the flexible circuit substrate 20 to protect the electrical contacts between the chip 10 and the flexible circuit substrate 20.

FIG. 3 is a partially enlarged top view schematic diagram of a chip bonding area of a flexible circuit substrate according to another embodiment of the present invention. FIG. 4 is a partially enlarged top view schematic diagram of a chip bonding area of a flexible circuit substrate according to yet another embodiment of the present invention. It must be noted that the embodiments of FIG. 3 and FIG. 4 use the component numbers and part of the content of the embodiment of FIG. 2A, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, and will not be repeated here.

Please refer to FIG. 3 . The main difference between the flexible circuit substrate of FIG. 3 and the flexible circuit substrate of FIG. 2A is that the first main body 242a2 of the first detection pin 242a and the second main body 246a2 of the second detection pin 246a in FIG. 3 do not have the slot 246h. In other words, the first main body 242a2 only includes a main body with a width larger than the first joint portion 242a1 and is not separated into a plurality of sub-main bodies with a width similar to the first joint portion 242a1. The second main body 246a2 only includes a main body with a width larger than the second joint portion 242a2 and is not separated into a plurality of sub-main bodies with a width similar to the second joint portion 242a2. The width, area and shape of the first main body 242a2 of the first detection pin 242a and the second main body 246a2 of the second detection pin 246a can be adjusted appropriately according to different considerations such as circuit layout space, structural strength, electrical transmission, heat dissipation, etc., and the present invention is not limited thereto.

Please refer to FIG. 4 . The main difference between the flexible circuit substrate of FIG. 4 and the flexible circuit substrate of FIG. 2A is that the first main body 242a2 of the first detection pin 242a in FIG. 4 has a slot 242h’ and the second main body 246a2 of the second detection pin 246a has a slot 246h’, wherein the slot 242h’ and the slot 246h’ are closed slots, and the first main body 242a2 and the second main body 246a2 are not separated into a plurality of sub-main bodies. The slot 242h’ is at least located between two adjacent second bumps 14, and the slot 246h’ is at least located between two adjacent fourth bumps 18. The shapes and sizes of the slots 242h' and 246h' can be adjusted appropriately according to different considerations such as the layout space, structural strength, electrical transmission, and heat dissipation of the first main body portion 242a2 and the second main body portion 246a2, and the present invention is not limited thereto.

In summary, by setting a detection pin in an area where pins and bumps are relatively sparsely arranged (e.g., a corner near a chip bonding area), and making the gap between the detection pin and an adjacent bump equal to the minimum value of multiple gaps between multiple pins and adjacent bumps in an area where pins and bumps are relatively densely arranged, by checking whether the detection pin and the adjacent bump are short-circuited by mutual contact, it can be inferred whether the pins and adjacent bumps in other areas have a false contact problem. Therefore, when executing the procedure of inspecting the bonding condition of the pins, personnel or machines only need to inspect the inspection pins located in a fixed area, without having to specifically search for pins and bumps with the minimum gap in other areas, thereby significantly shortening the operation time of the inspection procedure.

1: Film flip chip packaging structure 10: chip 10a: long side 10b: short side 11: packaging glue 12: first bump 14: second bump 16: third bump 18: fourth bump 20: flexible circuit substrate 22: flexible substrate 22a: first surface 22b: second surface 24: upper circuit 26: lower circuit 26a: first unwired area 26b: second unwired area 27: upper soldering layer 28: lower soldering layer 28a: opening 200: chip bonding area 202: first bonding area 204: second bonding area 206: third bonding area 208: fourth joint area 200a: first edge 200b: second edge 242: first pin 242a: first detection pin 242a1: first joint part 242a2: first main body 242h, 242h’, 246h, 246h’: slot 244: second pin 246: third pin 246a: second detection pin 246a1: second joint part 246a2: second main body 248: fourth pin D1, D2: extension direction EG1, EG1a: first gap EG2, EG2a: second gap minEG1, minEG2: minimum value W1, W2: width X1, X2: horizontal spacing X3, X4: vertical spacing

FIG. 1 is a schematic top view of a thin film chip-on-chip package structure according to an embodiment of the present invention. FIG. 2A is a partially enlarged schematic top view of the chip bonding area of the flexible circuit substrate of FIG. 1. FIG. 2B is a schematic bottom view of the chip bonding area of the flexible circuit substrate of FIG. 1 corresponding to FIG. 2A. FIG. 2C is a schematic cross-sectional view along line A-A’ of FIG. 2A. FIG. 3 is a partially enlarged schematic top view of the chip bonding area of the flexible circuit substrate according to another embodiment of the present invention. FIG. 4 is a partially enlarged schematic top view of the chip bonding area of the flexible circuit substrate according to another embodiment of the present invention.

10: chip 10a: long side 10b: short side 12: first bump 14: second bump 16: third bump 18: fourth bump 24: upper circuit 200: chip bonding area 202: first bonding area 204: second bonding area 206: third bonding area 208: fourth bonding area 200a: first edge 200b: second edge 242: first pin 242a: first detection pin 242a1: first bonding part 242a2: first main body 242h, 246h: slot 244: second pin 246: third pin 246a: second detection pin 246a1: second joint 246a2: second main body 248: fourth pin D1, D2: extension direction EG1, EG1a: first gap EG2, EG2a: second gap minEG1, minEG2: minimum value W1, W2: width X1, X2: horizontal spacing X3, X4: vertical spacing

Claims (10)

A thin film flip chip packaging structure includes: a chip, including a plurality of first bumps and a plurality of second bumps, the plurality of first bumps and the plurality of second bumps are respectively adjacent to and arranged in two rows along a long side of the chip, wherein the plurality of first bumps are farther from the long side than the plurality of second bumps; and a flexible circuit substrate, wherein the chip is bonded to a chip bonding area of the flexible circuit substrate, and the flexible circuit substrate includes: a flexible substrate, having a first surface and a second surface opposite to each other, and the chip bonding area is located on the first surface; and an upper circuit, arranged on the first surface of the flexible substrate, the upper circuit including a plurality of first pins and a plurality of second pins arranged along a first edge of the chip bonding area corresponding to the long side, the first pins being bonded to the first bumps. The chip bonding area includes a first bonding area and a second bonding area adjacent to the first edge, the lateral distance between the first bonding area and the adjacent second bonding area is greater than the lateral distance between the first bonding area and the adjacent second bonding area, each of the first leads and the adjacent second bonding area has a first gap parallel to the first edge, at least one of the first leads in the first bonding area is a first detection pin, and the first gap between the first detection pin and the adjacent second bonding area is substantially equal to the minimum value of the multiple first gaps between the multiple first leads and the multiple second bonding areas. A chip-on-film package structure as described in claim 1, wherein the first bonding area is closer to a corner of the chip bonding area than the second bonding area. A thin film chip package structure as described in claim 1, wherein the number of the first bonding areas is two, located on both sides of the second bonding area respectively. The chip-on-film package structure as described in claim 1, wherein the flexible circuit substrate further includes a lower circuit disposed on the second surface of the flexible substrate, the lower circuit having an unwired area, the unwired area corresponding to a portion of the first bonding area and exposing a portion of the second surface of the flexible substrate corresponding to the first detection pin and the adjacent second bump. The thin film chip package structure as described in claim 4, wherein the flexible circuit substrate further includes a lower soldering layer, the lower soldering layer covers the lower circuit and has an opening, and the opening corresponds to the unwired area. A chip-on-film package structure as described in claim 1, wherein the first detection pin includes a first joint portion and a first main portion, the first joint portion is connected to the first bump, the first main portion extends between two adjacent second bumps, and the width of the first main portion is greater than the width of the first joint portion. A thin film chip package structure as described in claim 6, wherein the first main body has a groove, and the groove is at least located between two adjacent second bumps. A thin film flip chip package structure as described in claim 1, wherein the chip further includes a plurality of third bumps and a plurality of fourth bumps, which are respectively adjacent to and arranged in two rows along a short side of the chip, wherein the plurality of third bumps are farther from the short side than the plurality of fourth bumps, and the upper circuit further includes a plurality of third pins and a plurality of fourth pins arranged along a second edge of the chip bonding area corresponding to the short side, wherein the third pin is bonded to the third bump, and the fourth pin is bonded to the fourth bump, wherein the chip bonding area includes a third bonding area adjacent to the second edge and a fourth bonding area corresponding to the third bonding area. The longitudinal distance between the third bump in the third bonding area and the adjacent fourth bump is greater than the longitudinal distance between the third bump corresponding to the fourth bonding area and the adjacent fourth bump, each of the third pins and the adjacent fourth bump has a second gap parallel to the second edge, at least one of the third pins in the third bonding area is a second detection pin, and the second gap between the second detection pin and the adjacent fourth bump is substantially equal to the minimum value of the multiple second gaps between the multiple third pins and the multiple fourth bumps in the fourth bonding area. The thin film chip package structure as described in claim 8, wherein the flexible circuit substrate further includes a lower circuit, which is arranged on the second surface of the flexible substrate, and the lower circuit has a first unwired area and a second unwired area, wherein the first unwired area corresponds to a part of the first bonding area, and exposes a part of the second surface of the flexible substrate corresponding to the first detection pin and the adjacent second bump, and the second unwired area corresponds to a part of the third bonding area, and exposes a part of the second surface of the flexible substrate corresponding to the second detection pin and the adjacent fourth bump. The thin film chip package structure as described in claim 9, wherein the flexible circuit substrate further includes a lower soldering layer, the lower soldering layer covers the lower circuit and has a plurality of openings, and the openings correspond to the first unwired area and the second unwired area respectively.

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