TWI804103B - Chip on film package structure - Google Patents

Abstract

A chip on film package structure includes a flexible circuit board and a chip. The flexible circuit board includes a flexible substrate and a circuit structure. The circuit structure is disposed on the flexible substrate and includes a plurality of first leads, a plurality of second leads and a plurality of supporting patterns. The first leads are disposed on a first surface of the flexible substrate, and the second leads and the supporting patterns are disposed on a second surface of the flexible substrate. Each of the supporting patterns has a plurality of supporting leads. The chip is electrically connected to first inner lead portions of the first leads through a plurality of bumps. An orthographic projection of the supporting leads on the first surface partially overlaps with part of the bumps and part of the first inner lead portions. Each of the first inner lead portions has a first width, each of the supporting leads has a second width, and the second width is greater than or equal to the first width and less than or equal to 1.5 times of the first width.

Description

Thin Film Chip-on-Chip Packaging Structure

The present invention relates to a package structure, and in particular to a chip-on-film package structure.

Chip on Film (COF) packaging structure is a common packaging type of driving chips of liquid crystal displays. Nowadays, in order to increase the pin layout space, double-sided copper foil flexible substrates are beginning to be favored. Both the upper surface and the lower surface of the double-sided copper foil flexible substrate are covered with lines. When the width of the support pins on the lower surface is greatly different from the width of the inner pins on the upper surface, it may cause flexibility. The uneven stress on the upper surface and the lower surface of the substrate may cause warpage, and the inner pins may be bonded due to the uneven support of the support pins on the lower surface for the inner pins on the upper surface. (Inner Lead Bonding, ILB) produces the problem of broken feet or poor bonding with the bumps of the chip. In addition, when the support pins on the lower surface are designed to extend in the same direction as the inner pins on the upper surface, the support pins and inner pins may have different degrees of displacement due to the difference in the copper process between the upper surface and the lower surface , so that the overlapping area of the support pin and the inner pin is reduced, which in turn creates the risk of uneven or partially unsupported support.

The present invention provides a thin film chip-on-chip packaging structure, the supporting pattern can provide a relatively uniform supporting force, and can avoid the problem of broken legs or poor bonding of the inner pins due to uneven support when the inner pins are bonded, and can further improve Overall structure and electrical reliability.

The film-on-chip packaging structure of the present invention includes a flexible circuit carrier and a chip. The flexible circuit carrier includes a flexible substrate and a circuit structure. The flexible substrate has a first surface and a second surface opposite to each other and a chip bonding area. The circuit structure is configured on the flexible substrate and includes a plurality of first leads, a plurality of second leads and a plurality of supporting patterns. The first leads are arranged on the first surface, and each first lead has a first inner lead portion. The second pins and the supporting pattern are arranged on the second surface. Each second pin has a second inner pin portion. Each supporting pattern has a plurality of supporting line segments. The first inner lead portion and the second inner lead portion are located in the chip bonding area. The support line segments are locally located within the die bonding area. The chip is arranged on the first surface and located in the chip bonding area, and is electrically connected to the first inner lead part through a plurality of bumps. The orthographic projection of the supporting line segment on the first surface partially overlaps with part of the protrusion and part of the first inner pin. Each first inner lead portion has a first width, each support line segment has a second width, and the second width is greater than or equal to the first width and less than or equal to 1.5 times the first width.

In an embodiment of the present invention, the extending direction of the above-mentioned supporting line segment is inclined to the extending direction of the partially overlapping protrusion and the first inner pin portion.

In an embodiment of the present invention, the above-mentioned orthographic projection of the second inner lead portion on the first surface partially overlaps with the protrusion and the first inner lead portion. Each second inner lead portion has a third width, and the third width is greater than or equal to the first width and less than or equal to 1.5 times the first width.

In an embodiment of the present invention, the extending direction of the part of the second inner pin part is inclined to the extending direction of the partially overlapping protrusion and the first inner pin part.

In an embodiment of the present invention, the above-mentioned wafer bonding area has two opposite long sides and two opposite short sides. The first lead and the second lead extend from the chip bonding area through two long sides or two short sides and toward opposite ends of the flexible substrate.

In an embodiment of the present invention, the orthographic projections of the above-mentioned part of the supporting pattern on the first surface are located on two short sides.

In an embodiment of the present invention, each supporting pattern mentioned above has a connecting line segment. Each support line segment of each support pattern is connected to the connection line segment with at least one end.

In an embodiment of the present invention, the above-mentioned wafer bonding area has two opposite long sides and two opposite short sides, and the orthographic projection of a part of the support pattern on the first surface is located on the two short sides, and the connecting line segment is at least Locally parallel to the two short sides.

In an embodiment of the present invention, the support line segments of the above-mentioned support pattern on the first surface are inclined to the two short sides in the above-mentioned orthographic projection on the two short sides.

In an embodiment of the invention, the above-mentioned supporting patterns are dummy patterns.

Based on the above, in the thin film chip-on-chip package structure of the present invention, the orthographic projection of the support line segment of the support pattern on the second surface of the flexible substrate on the first surface of the flexible substrate and part of the first inner lead portion Partial overlap, and the second width of the support line segment is greater than or equal to the first width of the first inner lead part and less than or equal to 1.5 times the first width of the first inner lead part. In this way, the support patterns on the second surface of the flexible substrate and the first inner pins on the first surface of the flexible substrate can have a more consistent overlapping area, thereby providing a more uniform support force, which can The problem of broken legs or poor bonding with the bumps on the first inner pin portion during inner pin bonding can be avoided, thereby improving the structural and electrical reliability of the FOC packaging structure of the present invention.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in every different form, and should not be limited to the embodiments described herein. The thickness, size or magnitude of layers or regions in the drawings may be exaggerated for clarity.

FIG. 1 is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention. FIG. 2 is a schematic bottom view of the chip-on-film packaging structure in FIG. 1 . FIG. 3 is an enlarged schematic view of area A of the thin film chip-on-chip package structure in FIG. 2 . For convenience of description, FIG. 1 shows the orthographic projection positions of the corresponding components in FIG. 2 with dotted lines.

Please refer to FIG. 1 , FIG. 2 and FIG. 3 at the same time. In this embodiment, the film-on-chip packaging structure 10 includes a flexible circuit carrier 100 and a chip 200 . The flexible circuit carrier 100 includes a flexible substrate 110 and a circuit structure 120 . The flexible substrate 110 has a first surface 112 and a second surface 114 opposite to each other, and a chip bonding area 116 . The circuit structure 120 is configured on the flexible substrate 110 and includes a plurality of first leads 122 , a plurality of second leads 124 and a plurality of supporting patterns 126 . The first leads 122 are disposed on the first surface 112, and each first lead 122 has a first inner lead portion 122a. The second pins 124 and the supporting pattern 126 are disposed on the second surface 114 . Each second pin 124 has a second inner pin portion 124a. Each supporting pattern 126 has a plurality of supporting line segments 126a. The first inner lead portion 122 a and the second inner lead portion 124 a are located in the die bonding area 116 . The support line segment 126 a is partially located within the die bonding area 116 . The chip 200 is disposed on the first surface 112 and located in the chip bonding area 116 , and the chip 200 is electrically connected to the first inner lead portion 122 a through a plurality of bumps 210 .

In particular, please refer to FIG. 3 again. In this embodiment, the orthographic projection of the support line segment 126 a on the first surface 112 partially overlaps with a part of the protrusion 210 and a part of the first inner lead portion 122 a. Each first inner pin portion 122a has a first width W1, each support segment 126a has a second width W2, and the second width W2 is greater than or equal to the first width W1 and less than or equal to 1.5 times the first width W1. Thereby, the supporting pattern 126 on the second surface 114 of the flexible substrate 110 can provide a relatively uniform supporting force, and can avoid internal pin bonding (that is, bonding the bumps 210 on the chip 200 to the When the first inner lead portion 122 a is eutectic bonded), the first inner lead portion 122 a may be broken or poorly bonded, thereby improving the structural reliability of the thin film chip-on-chip package structure 10 of this embodiment.

In detail, please refer to FIG. 1 and FIG. 2 at the same time. In this embodiment, the flexible circuit carrier 100 is embodied as a double-sided circuit substrate. As shown in FIG. 1 , for clarity, the orthographic projection of the first pin 122 on the flexible substrate 110 in this embodiment does not overlap or only partially overlaps that of the second pin 124 on the flexible substrate 110 Orthographic projection, but the present invention is not limited thereto. In other embodiments, the orthographic projection of the first pins 122 on the flexible substrate 110 may also overlap the orthographic projection of the second pins 124 on the flexible substrate 110 as much as possible, so that the flexible The stress distribution on the first surface 112 and the second surface 114 of the substrate 110 is relatively uniform, which still belongs to the protection scope of the present invention.

Furthermore, the material of the flexible substrate 110 in this embodiment is, for example, polyethylene terephthalate (PET), polyimide (Polyimide, PI), polyethersulfone (PES), carbonate resin (polycarbonate, PC) or other suitable flexible materials. The material of the circuit structure 120 may include copper, nickel, gold or silver, or other conductive metal materials. The chip 200 may be a driver chip or any suitable chip, wherein the chip 200 is electrically connected to the first inner pin portion 122a through the bump 210 . In other words, the chip 200 is flip-chip bonded to the first pins 122 .

Please refer to FIG. 1 to FIG. 3 at the same time, the extending direction D2 of the supporting line segment 126 a of the supporting pattern 126 in this embodiment is inclined to the extending direction D1 of the partially overlapping bump 210 and the first inner pin portion 122 a. Through the obliquely extending design of the support line segment 126a, the area where the support line segment 126a overlaps the bump 210 and the first inner pin portion 122a can be increased, so as to provide an effective force when the bump 210 is engaged with the first inner pin portion 122a. support. In this way, it is possible to avoid the conventional design of the supporting pins on the second surface and the inner pins on the first surface to extend in the same direction, resulting in the difference between the supporting pins and the inner pins due to the difference in the copper process. Different degrees of displacement of the feet reduce the overlapping area between the support pins and the inner pins, which in turn causes problems of uneven support or local lack of support. Here, the extending direction D1 is, for example, a direction parallel to the long side of the die bonding region 116 , and the extending direction D2 and the extending direction D1 have an included angle greater than 0 degrees and less than 90 degrees. That is to say, the supporting line segment 126a of this embodiment is inclined at an acute angle relative to the first inner pin portion 122a. In other words, the supporting line segment 126a of this embodiment is not parallel to the first inner pin portion 122a.

Furthermore, the orthographic projection of the second inner lead portion 124 a on the first surface 112 in this embodiment partially overlaps with the bump 210 and the first inner lead portion 122 a. Each second inner pin portion 124a has a third width W3, and the third width W3 is greater than or equal to the first width W1 and less than or equal to 1.5 times the first width W1. In other words, the width dimension range of the second inner pin portion 124a in this embodiment is the same as the width dimension range of the support line segment 126a. The extending direction D3 of a part of the second inner pin portion 124a is inclined to the extending direction D1 of the protruding block 210 and the first inner pin portion 122a partially overlapped therewith. Here, the extension direction D3 and the extension direction D1 have an included angle greater than 0 degrees and less than 90 degrees. That is to say, part of the second inner pin portion 124a in this embodiment is inclined at an acute angle relative to the first inner pin portion 122a.

Please refer to FIG. 1 and FIG. 2 at the same time, the wafer bonding area 116 of this embodiment has two opposite long sides 116a, 116b and two opposite short sides 116c, 116d. The first pin 122 and the second pin 124 extend from the chip bonding area 116 through the two long sides 116 a , 116 b or the two short sides 116 c , 116 d to opposite ends S1 , S2 of the flexible substrate 110 . Here, the terminal S1 is an output terminal, and the terminal S2 is an input terminal. In addition, as shown in FIGS. 1 to 3 , the orthographic projections of part of the supporting pattern 126 on the first surface 112 are located on the two short sides 116c and 116d , but the present invention does not limit the position of the supporting pattern 126 . In other non-illustrated embodiments, the orthographic projection of the supporting pattern 126 on the first surface 112 may also be located at the two long sides 116 a , 116 b of the chip bonding region 116 . In short, the position of the support pattern 126 can be adjusted according to the wiring space, and is not limited to a specific position.

In addition, please refer to FIG. 3 , in this embodiment, each supporting pattern 126 has a connecting line segment 126b, and each supporting line segment 126a of each supporting pattern 126 is connected to the connecting line segment 126b through at least one end E1. Further, the support pattern 126 shown in FIG. 3 is a closed pattern, that is, the connecting line segment 126b completely surrounds the surrounding of the supporting pattern 126. Therefore, the opposite ends E1 and E2 of the supporting line segment 126a are connected to the connecting line segment 126b. But the present invention is not limited thereto. In other embodiments, the supporting pattern 126 can also be a non-closed pattern, that is, the connecting line segment 126b only partially surrounds the surrounding of the supporting pattern 126, and the supporting line segment 126a is only connected to the connecting line segment 126b by one end E1, and the other end E2 Then it is an open end, which still belongs to the intended protection scope of the present invention. In other words, the shape and style of the supporting pattern 126 can be adjusted according to the wiring space, and is not limited to a specific pattern. More specifically, the orthographic projection of part of the support pattern 126 on the first surface 112 is located at the two short sides 116c, 116d of the die bonding area 116 and the connecting line segment 126b is at least partially parallel to the two short sides 116c, 116d. The orthographic projections on the first surface 112 are located at the two short sides 116 c and 116 d of the die bonding region 116 , and the support line segments 126 a of the support patterns 126 are inclined to the two short sides 116 d and 116 d. Here, the supporting patterns 126 are, for example, dummy patterns, but the invention is not limited thereto. The supporting line segment 126 a and the connecting line segment 126 b are, for example, integrally formed structures, which are not limited here.

FIG. 4 is an enlarged schematic view of a local area of a chip-on-film packaging structure according to another embodiment of the present invention. As shown in FIG. 4 , in this embodiment, the supporting pattern 126 ′ is a rectangular and non-closed supporting pattern, that is, the connecting line segment 126 b only partially surrounds the supporting pattern 126 ′, and here, the connecting line segment 126 b only surrounds the supporting pattern 126 ' of the three sides. In this case, part of the supporting line segment 126a is connected to the connecting line segment 126b through the end E1, and the other end E2 is an open end and not connected to the connecting line segment 126b, so that the supporting pattern 126' partially presents a non-closed structure, but this The invention is not limited thereto. In short, the shape and style of the supporting pattern 126, 126' can be adjusted according to the wiring space, and is not limited to a specific pattern.

To sum up, in the thin film chip-on-chip package structure of the present invention, the orthographic projection of the support line segment of the support pattern on the second surface of the flexible substrate on the first surface of the flexible substrate and part of the first inner leads The legs are partially overlapped, and the second width of the support line segment is greater than or equal to the first width of the first inner lead part and less than or equal to 1.5 times the first width of the first inner lead part. In this way, the support patterns on the second surface of the flexible substrate and the first inner pins on the first surface of the flexible substrate can have a more consistent overlapping area, thereby providing a more uniform support force, which can The problem of broken legs or poor bonding with the bumps on the first inner pin portion during inner pin bonding can be avoided, thereby improving the structural and electrical reliability of the FOC packaging structure of the present invention.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10: Film-on-chip packaging structure 100: Flexible circuit carrier board 110: flexible substrate 112: first surface 114: second surface 116: Chip bonding area 116a, 116b: long sides 116c, 116d: short side 120: Line structure 122: The first pin 122a: the first inner pin part 124: Second pin 124a: the second inner pin part 126, 126': support pattern 126a: Support line segment 126b: Connecting line segments E1, E2: end 200: chip 210: Bump A: area D1, D2, D3: Extension direction S1, S2: terminal W1, W2, W3: Width

FIG. 1 is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention. FIG. 2 is a schematic bottom view of the chip-on-film packaging structure in FIG. 1 . FIG. 3 is an enlarged schematic view of area A of the thin film chip-on-chip package structure in FIG. 2 . FIG. 4 is an enlarged schematic view of a local area of a chip-on-film packaging structure according to another embodiment of the present invention.

10: Film-on-chip packaging structure

100: Flexible circuit carrier board

110: flexible substrate

112: first surface

116: Chip bonding area

116a, 116b: long sides

116c, 116d: short side

120: Line structure

122: The first pin

122a: the first inner pin part

124: Second pin

124a: the second inner pin part

126: support pattern

200: chip

210: Bump

S1, S2: terminal

Claims (9)

A chip-on-film packaging structure, comprising: a flexible circuit carrier, including: a flexible substrate having a first surface and a second surface opposite to each other and a chip bonding area; and a circuit structure configured on the flexible substrate, and includes a plurality of first pins, a plurality of second pins and a plurality of supporting patterns, the first pins are arranged on the first surface, and each of the first pins has A first inner pin portion, the second pins and the supporting patterns are arranged on the second surface, each of the second pins has a second inner pin portion, and each of the supporting patterns has a plurality of supports line segments, the first inner lead portions and the second inner lead portions are located in the wafer bonding area, the supporting line segments are partially located in the wafer bonding area; and a chip is disposed on the first surface and Located in the chip bonding area and electrically connected to the first inner pins through a plurality of bumps; wherein the orthographic projection of the support line segments on the first surface is part of the bumps and part of the first An inner lead portion partially overlaps, each of the first inner lead portions has a first width, each of the support line segments has a second width, and the second width is greater than or equal to the first width and less than or equal to 1.5 times the The first width, wherein the extending direction of the supporting line segments is inclined to the extending direction of the partially overlapping protrusions and the first inner pins. The chip-on-chip packaging structure as claimed in claim 1, wherein the orthographic projection of the second inner leads on the first surface partially overlaps with the bumps and the first inner leads, and each of the The second inner pin portion has a third width, which is greater than or equal to the first width and less than or equal to 1.5 times the first width. The chip-on-chip packaging structure as claimed in claim 2, wherein the extending direction of some of the second inner lead portions is inclined to the extending direction of the partially overlapping bumps and the first inner lead portions. The chip-on-chip packaging structure as claimed in claim 1, wherein the chip bonding region has two opposite long sides and two opposite short sides, and the first leads and the second leads are bonded from the chip The region passes through the two long sides or the two short sides and extends toward opposite ends of the flexible substrate. The chip-on-film packaging structure as claimed in claim 4, wherein the orthographic projections of some of the supporting patterns on the first surface are located on the two short sides. The thin film chip-on-chip package structure as claimed in claim 1, wherein each of the supporting patterns has a connecting line segment, and the supporting line segment of each supporting pattern is connected to the connecting line segment with at least one end. The thin film chip-on-chip packaging structure as claimed in claim 6, wherein the chip bonding area has two opposite long sides and two opposite short sides, and the orthographic projections of some of the supporting patterns on the first surface are located on the first surface. The two short sides and the connecting line segments are at least partially parallel to the two short sides. The thin film chip-on-chip packaging structure as claimed in claim 7, wherein the support line segments of the support patterns on the two short sides are inclined to the two short sides in the orthographic projection on the first surface. The chip-on-film packaging structure according to claim 1, wherein the supporting patterns are dummy patterns.

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