TWI767392B - SYSTEM AND METHOD FOR AUTOMATIC ALLOCATING PCIe BANDWIDTH - Google Patents

Abstract

A system and a method for automatic allocating PCIe bandwidth, the system includes a PCIe riser card, an Intelligent Platform Management Interface, a BIOS, and a CPU. The PCIe riser card is used to connect a PCIe device and generating an identification code accordingly. The intelligent platform management interface is electrically connected to the PCIe riser card and has a baseboard management controller. The BIOS is used to send an identification code query command to the baseboard management controller to obtain the identification code, and determine a bandwidth corresponding to the identification code with an identification code bandwidth comparison table. The CPU is electrically connected to the basic input/output system and the PCIe riser card, and is used to set a port branch according to the bandwidth, and initialize a plurality of root ports of the CPU so that the root ports correspond to the bandwidth of the PCIe device.

Description

PCIe bandwidth automatic allocation system and method

The present invention relates to an automatic bandwidth allocation system and method, in particular to a PCIe bandwidth automatic allocation system and method.

Generally speaking, a server model often has quite a few different configurations. The PCIe device connected to the IIO root port of the CPU is usually assembled and allocated the corresponding bandwidth through a riser card. Among them, since different PCIe devices have different bandwidth requirements, it is very difficult for the BIOS to take into account all situations when performing bandwidth allocation.

In the prior art, in order to solve the problem of bandwidth allocation of PCIe devices, there are mainly three ways: First, the first one is through the configuration of fixed models, so that the IIO root port allocates a fixed bandwidth to the corresponding PCIe devices; Then, the second is to determine the bandwidth required by the PCIe device through the model information burned in the FRU (Field Replace Unit), and then allocate the corresponding bandwidth to the PCIe device; finally, the third is to pass The reserved GPIO (General-purpose input/output) is used to distinguish various model configurations.

As mentioned above, in the existing bandwidth allocation improvement methods for PCIe devices, the first and third methods often have the disadvantage of being inflexible. For example, in the first method, since the fixed model configuration can only be applied to one bandwidth, it will limit the bandwidth types of PCIe devices that can be installed in the server; while the third method requires hardware There are enough GPIO pins reserved in the design, but in fact, the number of GPIOs is limited, and most of the GPIOs have their own special purposes.

However, although the second method is more flexible in use, because the second method relies too much on the correctness of the information in the FRU, when the model information of the FRU is programmed incorrectly, the allocation of PCIe bandwidth will also be wrong. As a result, the PCIe device cannot be used normally; in addition, if the second method is adopted, the BIOS also needs to store all model configurations and PCIe bandwidth allocation information in advance, so as to effectively allocate the bandwidth allocation of PCIe devices according to various model configurations. .

In view of the fact that in the prior art solutions for bandwidth allocation of PCIe devices, there are inflexible problems due to the method of configuring the corresponding bandwidth through a fixed model and the method of distinguishing the bandwidth through GPIO , and the use of FRU programming information to allocate bandwidth may lead to the risk of human error, and it is also necessary to pre-store various model configurations and bandwidth allocation information of PCIe devices in the BIOS. Therefore, the existing The solutions are very inconvenient; therefore, the main purpose of the present invention is to provide a PCIe bandwidth automatic allocation system, which can effectively and automatically determine the bandwidth required by the PCIe device, and then control the CPU to perform corresponding settings.

In order to solve the problems of the prior art, the necessary technical means adopted by the present invention is to provide a PCIe bandwidth automatic allocation system, which includes a PCIe riser card, an intelligent platform management interface (IPMI) and a basic input output system (BIOS).

The PCIe riser card is used for inserting a PCIe device, and the PCIe riser card generates an identification code according to the inserted PCIe device.

The intelligent platform management interface is electrically connected to the PCIe riser card, and has a baseboard management controller (BMC), and the baseboard management controller reads the PCIe when receiving an identification code query command The identification code of the riser card.

The basic input output system is electrically connected to the baseboard management controller, and is used to send the identification code query command to the baseboard management controller to obtain the identification code, and determine the corresponding identification code according to an identification code bandwidth comparison table one bandwidth.

The CPU is electrically connected to the basic input output system and the PCIe riser card, and is used to perform a bifurcation setting according to the bandwidth, and to initialize a plurality of root ports of the CPU so that the root ports correspond to The bandwidth of the PCIe device.

In an auxiliary technical means derived from the above-mentioned necessary technical means, the intelligent platform management interface further includes an integrated circuit controller, and the integrated circuit controller is disposed between the PCIe riser card and the baseboard management control between the devices for electrically connecting to the PCIe riser card and the baseboard management controller.

Preferably, the intelligent platform management interface further includes an I/O expander, and the I/O expander is disposed between the IC controller and the PCIe riser card for electrically connecting the IC The inter-circuit controller and the PCIe riser card. In addition, the I/O expander is an I/O expander (I2C IO Expander) based on an I2C interface, and the I/O expander is connected to the PCIe riser card and the integrated circuit controller through an I2C interface.

In order to solve the problem of the prior art, another necessary technical means adopted by the present invention is to provide a PCIe bandwidth automatic allocation method, which includes the following steps (A) to (E).

First, step (A) is to initialize an intelligent platform management interface, so that a basic input output system sends an identification code query command to a baseboard management controller; then, step (B) is that the baseboard management controller according to the identification code The query command reads an identification code corresponding to a PCIe device from a PCIe riser card; then, step (C) is to determine a bandwidth corresponding to the identification code according to an identification code bandwidth comparison table; and then, step (D) is to perform branch setting of a connection port of a CPU according to the bandwidth; finally, step (E) is to initialize a plurality of root ports of the CPU so that the root ports correspond to the bandwidth of the PCIe device.

In an auxiliary technical means derived from the above-mentioned necessary technical means, a step (A0) is further included before the step (A), and the step (A0) is to insert the PCIe device into the PCIe riser card.

As described above, the present invention uses the basic input output system to drive the baseboard management controller to read the identification code of the PCIe device from the PCIe adapter card, and then uses the identification code bandwidth comparison table to compare the identification code, and then the corresponding identification code can be obtained. Based on the bandwidth of the PCIe device, to control the port branch settings of the CPU, it can effectively initialize the root port to connect to the PCIe device correspondingly, and effectively allow the PCIe riser card to be plugged into PCIe devices of various bandwidths. It can effectively avoid human error in operation, which is very convenient.

The specific embodiments adopted by the present invention will be further described by the following embodiments and drawings.

Please refer to the first figure, which is a system schematic diagram of the PCIe bandwidth automatic allocation system provided by the preferred embodiment of the present invention. As shown in the figure, a PCIe (Peripheral Component Interconnect Express) bandwidth automatic allocation system 100 includes a PCIe riser card 1, an intelligent platform management interface (Intelligent Platform Management Interface, IPMI) 2, and a basic input output system (Basic Input/Output System, BIOS) 3, a platform path controller 4 and a CPU (Central Processing Unit, central processing unit) 5.

The PCIe riser card 1 is used for inserting a PCIe device 200 , and the PCIe riser card 1 generates an identification code according to the inserted PCIe device 200 . In this embodiment, the PCIe riser card 1 is based on an I ² C (Inter-Integrated Circuit) interface and has a riser card (Riser Card) of a PCIe slot.

The intelligent platform management interface 2 includes an input/output expander 21 , an IC controller 22 and a baseboard management controller (BMC) 23 .

The I/O expander 21 is electrically connected to the PCIe riser card 1, the IC controller 22 is electrically connected to the I/O expander 21, and the baseboard management controller 23 is electrically connected to receiving an identification Read the identification code of PCIe riser card 1 during the code query command. In this embodiment, the I/O expander 21 is an I/O expander (I ² C IO Expander) based on the I ² C interface, and the inter-integrated circuit controller 22 is an I ² C controller, and the input and output The expander 21 is connected to the PCIe riser card 1 and the IC controller 22 through an I ² C interface. Baseboard Management Controller (BMC) 23.

The basic input output system 3 is electrically connected to the baseboard management controller 23, and has a built-in identification code bandwidth comparison table 31, and the basic input output system 3 is used to send the identification code query command to the baseboard management controller 23 to obtain Corresponding to the identification code of the PCIe device 200 , a bandwidth corresponding to the identification code is determined according to the identification code bandwidth comparison table 31 .

Based on the above, in this embodiment, the identification code bandwidth comparison table 31 is shown in Table 1 below.

Table I: slot location PCIe[0:7] PCIe[8:15] Pin and ID order A8 A30 A29 B12 A8 A30 A29 B12 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bandwidth Identifier X16 0 1 1 1 0 0 1 0 X8X8 0 1 1 0 0 1 1 0 X4X4X8 0 1 0 0 0 1 1 0 X8X4X4 0 1 1 0 0 1 0 0 X4X4X4X4 0 1 0 0 0 1 0 0

As shown in Table 1 above, when the identification code is 01110010 (from bit0 to bit7), the corresponding bandwidth is X16; when the identification code is 01100110 (from bit0 to bit7), the corresponding bandwidth is X8X8; When the code is 01000110 (from bit0 to bit7), the corresponding bandwidth is X4X4X8; when the identification code is 01100100 (from bit0 to bit7), the corresponding bandwidth is X8X4X4; when the identification code is 01000100 (from bit0 to bit7) ), the corresponding bandwidth is X4X4X4X4. Wherein, in this embodiment, the identification code used to identify the bandwidth is defined according to the pins corresponding to PCIe interfaces of different bandwidths, but is not limited to this embodiment, and can also be based on the PCIe interface at different bandwidths. The identification code difference is used to define the identification code bandwidth comparison table 31 .

The platform path controller 4 is electrically connected to the BIOS 3 ; wherein, the platform path controller 4 is electrically connected to the BIOS 3 through a Serial Peripheral Interface Bus (SPI).

The CPU 5 is electrically connected to the platform path controller 4 and the PCIe riser card 1 , so as to be electrically connected to the BIOS 3 through the platform path controller 4 and to identify the bandwidth of the PCIe device 200 in the BIOS 3 Afterwards, a bifurcation setting is performed according to the bandwidth, and a plurality of root ports (not shown) are initialized, so that the root ports correspond to the bandwidth of the PCIe device 200 . The CPU 5 is electrically connected to the platform routing controller 4 through a DMI (Direct Media Interface) interface.

Please continue to refer to the second figure, which is a flowchart showing the steps of the PCIe bandwidth automatic allocation method provided by the preferred embodiment of the present invention. As shown in the first and second figures, the PCIe bandwidth automatic allocation method of the present invention includes the following steps: first, step S101 is to insert the PCIe device 200 into the PCIe riser card 1; then, step S102 is to initialize the intelligent The platform management interface 2 enables the basic input output system 3 to send an identification code query command to the baseboard management controller 23; then, in step S103, the baseboard management controller 23 reads the corresponding PCIe device from the PCIe riser card 1 according to the identification code query command 200 identification code; then, step S104 is to judge the bandwidth corresponding to the identification code according to the identification code bandwidth comparison table; then, step S105 is to perform the branch setting of the connection port of the CPU according to the bandwidth; finally, step S106 is to initialize the CPU The multiple root ports make the root ports correspond to the bandwidth of the PCIe device.

As can be seen from the above description, since the PCIe bandwidth automatic allocation system 100 and the PCIe bandwidth automatic allocation method of the present invention can use the basic input output system 3 to send an identification code query command to the PCIe riser card 1 when the PCIe device 200 is inserted. The baseboard management controller 23, so that the baseboard management controller 23 reads the identification code corresponding to the PCIe device 200 from the PCIe riser card 1, and the basic input output system 3 further uses the identification code bandwidth comparison table 31 to compare and identify The code is used to know the bandwidth of the PCIe device 200 , so that the CPU can perform port branch settings accordingly, so as to initialize the corresponding root port so that the CPU 5 can establish a bidirectional transmission channel with the PCIe device 200 with a suitable bandwidth.

To sum up, compared with the prior art, in order to make the bandwidth of the PCIe device correspond to the CPU, the three solutions adopted have inconvenient problems; the present invention uses the basic input output system to drive the baseboard management controller to switch from PCIe The identification code of the PCIe device is read on the interface card, and then the identification code is compared with the identification code bandwidth comparison table, and the bandwidth corresponding to the PCIe device can be obtained. The initialized root port of the device is correspondingly connected to the PCIe device, which effectively allows the PCIe riser card to be plugged into PCIe devices of various bandwidths, and also effectively avoids human operation errors, which is very convenient.

Through the detailed description of the preferred embodiments above, it is hoped that the features and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various modifications and equivalent arrangements within the scope of the claimed scope of the present invention.

100:PCIe bandwidth automatic allocation system 1: PCIe riser card 2: Intelligent platform management interface 21: Input and output expander 22: Controller between ICs 23: Baseboard Management Controller 3: Basic Input Output System 31: Identification code bandwidth comparison table 4: Platform Path Controller 5: CPU 200: PCIe device

The first figure shows a system schematic diagram of the PCIe bandwidth automatic allocation system provided by the preferred embodiment of the present invention; and The second figure is a flowchart showing the steps of the PCIe bandwidth automatic allocation method provided by the preferred embodiment of the present invention.

100:PCIe bandwidth automatic allocation system 1: PCIe riser card 2: Intelligent platform management interface 21: Input and output expander 22: Controller between ICs 23: Baseboard Management Controller 3: Basic Input Output System 31: Identification code bandwidth comparison table 4: Platform Path Controller 5: CPU 200: PCIe device

Claims (6)

A PCIe bandwidth automatic allocation system, including: a PCIe riser card for inserting a PCIe device, and the PCIe riser card generates an identification code according to the inserted PCIe device; An Intelligent Platform Management Interface (IPMI) is electrically connected to the PCIe riser card and has a Baseboard Management Controller (BMC) that receives Read the identification code of the PCIe riser card during an identification code query command; A basic input output system (BIOS), which is electrically connected to the baseboard management controller, is used for sending the identification code query command to the baseboard management controller to obtain the identification code, and judges according to an identification code bandwidth comparison table a bandwidth corresponding to the identification code; and a CPU, electrically connected to the basic input output system and the PCIe riser card, for performing a bifurcation setting according to the bandwidth, and initializing a plurality of root ports of the CPU, so that the root ports The port corresponds to the bandwidth of the PCIe device. The PCIe bandwidth automatic allocation system as claimed in claim 1, wherein the intelligent platform management interface further comprises an IC controller, and the IC controller is disposed between the PCIe riser card and the substrate The management controller is electrically connected to the PCIe riser card and the baseboard management controller. The PCIe bandwidth automatic allocation system as claimed in claim 2, wherein the intelligent platform management interface further comprises an input/output expander, and the input/output expander is disposed between the IC controller and the PCIe switch The cards are used to electrically connect the inter-integrated circuit controller and the PCIe riser card. The PCIe bandwidth automatic allocation system according to claim 3, wherein the I/O expander is an I/O expander (I ² C IO Expander) based on an I ² C interface, and the I/O expander is an I/O expander based on an I 2 C interface. ² The C interface is connected to the PCIe riser card and the controller between the integrated circuit. A PCIe bandwidth automatic allocation method, comprising the following steps: (A) initialize an intelligent platform management interface, so that a basic input output system sends an identification code query command to a baseboard management controller; (B) the baseboard management controller reads an identification code corresponding to a PCIe device from a PCIe riser card according to the identification code query instruction; (C) Judging a bandwidth corresponding to the identification code according to an identification code bandwidth comparison table; (D) performing a port branch setting of a CPU according to the bandwidth; and (E) Initializing a plurality of root ports of the CPU so that the root ports correspond to the bandwidth of the PCIe device. The PCIe bandwidth automatic allocation method according to claim 5, further comprising a step (A0) before the step (A), and the step (A0) is to insert the PCIe device into the PCIe riser card.

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