CN119166560A - Bus bandwidth allocation method, device, server, electronic device and storage medium - Google Patents
Bus bandwidth allocation method, device, server, electronic device and storage medium Download PDFInfo
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- CN119166560A CN119166560A CN202411035536.7A CN202411035536A CN119166560A CN 119166560 A CN119166560 A CN 119166560A CN 202411035536 A CN202411035536 A CN 202411035536A CN 119166560 A CN119166560 A CN 119166560A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1678—Details of memory controller using bus width
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The application provides a bus bandwidth allocation method, a device, a server, electronic equipment and a storage medium, and relates to the technical field of computers, wherein the method comprises the steps of providing detection voltage for bus equipment inserted into a bus equipment slot and controlling the switching frequency of the detection voltage; the method comprises the steps of obtaining a switching frequency detection value of each data channel in a bus device slot, determining a bus bandwidth allocation value corresponding to the bus device based on the switching frequency detection value of each data channel, and allocating bus bandwidth for the bus device based on the bus bandwidth allocation value. The method and the device provided by the application can accurately determine the bandwidth of the bus equipment and realize automatic allocation, thereby avoiding the waste of bus resources.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a bus bandwidth allocation method, apparatus, server, electronic device, and storage medium.
Background
PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, high-speed serial computer expansion bus standard) interfaces on the server motherboard generally adopt PCIe X8 slots and PCIe X16 slots, facilitating later-stage plugging of different kinds of expansion cards. Even if the golden finger on the expansion card is X2 or X4, the golden finger can be plugged into a PCIe X8 slot or a PCIe X16 slot.
At present, the bandwidth directly provided by the processor to the PCIe X8 slot and the PCIe X16 slot is the maximum bandwidth, and the maximum bandwidth can not be effectively identified when an expansion card with a small number of data channels (Lane) is inserted, so that PCIe bus resources are wasted.
Therefore, how to implement automatic bandwidth allocation of PCIe bus devices is a technical problem to be solved in the industry.
Disclosure of Invention
The application provides a bus bandwidth allocation method, a device, a server, electronic equipment and a storage medium, which are used for solving the technical problem of how to realize automatic bandwidth allocation of PCIe bus equipment.
The application provides a bus bandwidth allocation method, which comprises the following steps:
Providing a detection voltage to the bus equipment inserted into the bus equipment slot, and controlling the switching frequency of the detection voltage;
acquiring a switching frequency detection value of each data channel in the bus equipment slot;
Determining a bus bandwidth allocation value corresponding to the bus device based on the switching frequency detection value of each data channel;
and allocating bus bandwidth for the bus device based on the bus bandwidth allocation value.
In some embodiments, the supplying the detection voltage to the bus device inserted into the bus device slot and controlling the switching frequency of the detection voltage includes:
the first voltage control instruction is used for controlling the power supply equipment to provide detection voltage for the bus equipment;
and the switching frequency control instruction is used for controlling the power supply control equipment to set the switching frequency to control the switching frequency of the detection voltage.
In some embodiments, the determining, based on the detected switching frequency values of the data channels, a bus bandwidth allocation value corresponding to the bus device includes:
determining a switching frequency detection value of each data channel in the bus equipment slot and a channel position of each data channel;
determining a data channel with adjacent channel positions and a switching frequency detection value consistent with the set switching frequency as a target data channel;
and determining a bus bandwidth allocation value corresponding to the bus device based on the number of the target data channels.
In some embodiments, before the providing the detection voltage to the bus device inserted into the bus device slot and controlling the switching frequency of the detection voltage, the method further includes:
And determining the detection voltage based on the working voltage of each bus device, wherein the detection voltage is smaller than the working voltage of each bus device.
In some embodiments, the sending a switching frequency control instruction to the power control device includes:
determining the set switching frequency corresponding to each bus device, wherein the set switching frequencies corresponding to each bus device are different;
Generating switching frequency control instructions corresponding to each bus device based on the set switching frequencies corresponding to each bus device;
transmitting a switching frequency control instruction corresponding to each bus device to a power control device corresponding to each bus device, so that the power control device controls the switching frequency of the detection voltage of each bus device;
or generating a switching frequency control instruction corresponding to the current bus equipment;
transmitting a switching frequency control instruction corresponding to the current bus device to a power control device corresponding to the current bus device, so that the power control device controls the switching frequency of the detection voltage of the current bus device;
and under the condition that the bus bandwidth allocation value corresponding to the current bus device is determined, switching the current bus device to the next bus device.
In some embodiments, the allocating bus bandwidth for the bus device based on the bus bandwidth allocation value comprises:
the second voltage control instruction is used for controlling the power supply equipment to provide working voltage for the bus equipment;
And under the condition that the bus equipment works normally, allocating bus bandwidth for the bus equipment based on the bus bandwidth allocation value.
The application provides a bus bandwidth allocation device, comprising:
the voltage generation module is used for providing detection voltage for the bus equipment inserted into the bus equipment slot and controlling the switching frequency of the detection voltage;
the frequency detection module is used for obtaining the switching frequency detection value of each data channel in the bus equipment slot;
The bandwidth determining module is used for determining a bus bandwidth allocation value corresponding to the bus equipment based on the switching frequency detection value of each data channel;
And the bandwidth allocation module is used for allocating bus bandwidth for the bus equipment based on the bus bandwidth allocation value.
The application provides a server, which comprises a processor, power equipment, power control equipment and a bus equipment slot;
The bus equipment slot is used for inserting bus equipment;
the power supply device is used for providing detection voltage for the bus device;
the power supply control device is used for controlling the switching frequency of the detection voltage;
The processor is connected with the power supply device, the power supply control device and the bus device slot and is used for executing the bus bandwidth allocation method and allocating bus bandwidth for the bus device.
The application provides an electronic device, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor realizes the bus bandwidth allocation method when executing the computer program.
The present application provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the bus bandwidth allocation method.
The bus bandwidth allocation method, the device, the server, the electronic equipment and the storage medium provided by the application provide detection voltage for the bus equipment inserted into the bus equipment slot and control the switching frequency of the detection voltage, acquire the switching frequency detection value of each data channel in the bus equipment slot, determine the bus bandwidth allocation value corresponding to the bus equipment based on the switching frequency detection value of each data channel, allocate bus bandwidth for the bus equipment based on the bus bandwidth allocation value, detect the switching frequency of each data channel in the bus equipment slot due to the detection voltage with different switching frequencies provided for the bus equipment, determine the number of the data channels actually used by the bus equipment by comparing the switching frequency detection values of each data channel, further determine the bus bandwidth allocation value, accurately determine the bandwidth of the PCIe bus equipment and realize automatic allocation, avoid the direct allocation of the maximum bandwidth by the processor according to the bus equipment slot and avoid the waste of PCIe bus resources.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the application or the technical solutions of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a bus bandwidth allocation method provided by the present application.
Fig. 2 is a schematic structural diagram of a bus bandwidth allocation device provided by the present application.
Fig. 3 is a schematic structural diagram of a server provided by the present application.
Fig. 4 is a second flowchart of a bus bandwidth allocation method according to the present application.
Fig. 5 is a circuit connection diagram of bus bandwidth allocation provided by the present application.
Fig. 6 is a circuit configuration diagram of a power supply apparatus provided by the present application.
Fig. 7 is a schematic structural diagram of an electronic device provided by the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like herein are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
PCIe is a high-speed serial computer expansion card standard, and is used in servers to connect a central processing unit (Central Processing Unit, CPU) to various expansion cards, such as graphics cards, sound cards, and network adapters. Bandwidth refers to the amount of data that can be transmitted over a period of time and is typically used to describe the performance of a network or data transmission path. Bus bandwidth refers to the amount of data that a bus connecting the various components in a computer system can transfer. For example, the bandwidth of the PCIe bus determines the data transfer rates that it can support and the efficiency of communication between devices. The bandwidth of the PCIe bus is closely related to the version of the PCIe bus and the number of data lanes (Lane).
In the related art, the bandwidth provided by the central processing unit directly to the PCIe X8 slot and the PCIe X16 slot is the maximum bandwidth, and the maximum bandwidth can not be effectively identified when an expansion card with a small number of data channels (Lane) is inserted, so that the processor also allocates the maximum bandwidth, which results in PCIe bus resource waste.
In view of the shortcomings of the related art, fig. 1 is a schematic flow chart of a bus bandwidth allocation method according to the present application, as shown in fig. 1, the method includes steps 110, 120, 130 and 140.
Step 110, providing a detection voltage to the bus device inserted into the bus device slot, and controlling the switching frequency of the detection voltage.
Specifically, the execution body of the bus bandwidth allocation method provided by the embodiment of the application is a bus bandwidth allocation device. The device may be implemented in software, such as a bus bandwidth allocation program running in a processor of a server, or may be a device for performing a bus bandwidth allocation method, such as a central processing unit, and a tablet, desktop, or server, etc. that includes the central processing unit.
The following embodiments describe a bus bandwidth allocation method by taking a server as an example. The server adopts PCIe bus to connect the central processing unit and various bus devices. Bus devices refer to devices that support connections to a central processor by way of a bus, such as a network adapter, memory controller, graphics processor, disk array control card, and the like.
And a bus device slot is arranged in the main board of the server. The bus device is provided with a specific number and arrangement of golden fingers (metal contact parts), the bus device slot is provided with corresponding metal contact areas, the bus device is inserted into the slot, the golden fingers are in contact with the metal contact areas, and reliable communication and data transmission between the bus device and the main board can be realized.
The detection voltage is a voltage for detecting the bandwidth of the bus device. For example, at normal operating voltages (e.g., 3.3 volts, 5 volts, or 12 volts), the data channel (PCIe Lane) port on the device side is low (0 volts) after power-up, and an electrical signal is initiated by the Host (Host) side for communication. However, under abnormal working voltage (for example, 1 volt), the data channel ports at the device end can output a certain level to the outside through the connection circuit inside the device due to the fact that the voltage is too low, and in this state, the part between each data channel port of the device and the power supply (VCC) port of the device can be approximately regarded as a resistor with a larger resistance value. Here, the abnormal operation voltage may be used as the detection voltage.
The switching frequency refers to a frequency at which a power supply is controlled to be turned on or off, and is generally expressed in units of hertz (Hz).
When the bus device is inserted into a bus device slot of a running server (host), or when the server which has been inserted into the bus device is powered on, a processor in the server may send an instruction to the power device for controlling the power device to supply a detection voltage to the bus device and controlling the power control device to control the switching frequency of the detection voltage.
Step 120, obtaining the switching frequency detection value of each data channel in the bus device slot.
Specifically, a data channel (Lane) refers to a pair of differential lines of a device physical layer transmission line for bidirectional communication.
When the detection voltage is provided for the bus device, the bus device cannot work normally under abnormal working voltage at the moment, and only serves as a resistor, and the detection voltage is output to the bus device slot through the bus device. The voltage detection and the detection of the switching frequency corresponding to the voltage can be carried out on each data channel in the bus equipment slot, and the switching frequency detection value of each data channel is obtained.
And 130, determining a bus bandwidth allocation value corresponding to the bus device based on the switching frequency detection value of each data channel.
In particular, it is possible to determine which data channels are connected to the bus device and the number of data channels connected to the bus device based on the switching frequency detection value of each data channel.
According to the number of data channels connected with the bus device, the number of data channels actually used by the bus device can be determined, and further, the bus bandwidth allocation value is determined. The bus bandwidth allocation value is the bus bandwidth allocated by the processor to the bus device.
For example, when the bus is PCIe, the bus device slots are mainly divided into four slot specifications of X1, X4, X8, and X16. Different slot specifications represent the physical size and bandwidth capabilities of the slot. X1 represents a lane of slot physical size 1 data lane, providing a bandwidth of 1 PCIe data lane (typically 500 megabytes per second, full duplex). X4 represents the lane of the slot having a physical size of 4 data lanes, providing the bandwidth of 4 PCIe data lanes (typically 2 gigabytes per second, full duplex), the remainder, and so on. A certain bus device slot is a PCIe X16 slot, meaning that the bus device slot has 16 data lanes (Lane). When a certain bus device is plugged into the slot, a detection voltage of 1 volt (V) is provided for the bus device, the switching frequency is controlled to be 1 kilohertz (kHz), the switching frequency detection value of 8 data channels can be detected to be 1 kHz, and all the 8 data channels are adjacent, then it can be determined that the bus device uses 8 data channels, the slot specification is X8, and the bus bandwidth of 8 times X1 needs to be provided, namely 4 gigabytes per second.
Step 140, allocating bus bandwidth for the bus device based on the bus bandwidth allocation value.
In particular, after determining the bus bandwidth allocation value, a processor in the server may allocate bus bandwidth for the bus device.
It should be noted that, in the embodiment of the present application, the server motherboard may configure a plurality of bus device slots, and slot specifications of each bus device slot may be different, and bus devices inserted into each bus device slot may also be different.
The bus bandwidth allocation method provided by the embodiment of the application is also suitable for inserting different bus devices into the bus device slots, and respectively allocating bus bandwidths for the bus devices. The switching frequency of the detection voltage can be controlled, so that the switching frequencies of the detection voltages of all the bus devices are different, and different bus devices can be distinguished through the switching frequencies.
The bus bandwidth allocation method provided by the embodiment of the application provides detection voltage for the bus equipment inserted into the bus equipment slot, controls the switching frequency of the detection voltage, acquires the switching frequency detection value of each data channel in the bus equipment slot, determines the bus bandwidth allocation value corresponding to the bus equipment based on the switching frequency detection value of each data channel, allocates bus bandwidth for the bus equipment based on the bus bandwidth allocation value, detects the switching frequency of each data channel in the bus equipment slot by providing detection voltages with different switching frequencies for the bus equipment, determines the number of data channels actually used by the bus equipment by comparing the switching frequency detection values of each data channel, further determines the bus bandwidth allocation value, can accurately determine the bandwidth of the PCIe bus equipment and realize automatic allocation, avoids a processor from directly allocating the maximum bandwidth according to the bus equipment slot and avoids PCIe bus resource waste.
It should be noted that each embodiment of the present application may be freely combined, exchanged in order, or separately executed, and does not need to rely on or rely on a fixed execution sequence.
In some embodiments, providing a detection voltage to a bus device inserted into a bus device slot and controlling a switching frequency of the detection voltage includes:
the first voltage control instruction is used for controlling the power supply equipment to provide detection voltage for the bus equipment;
And the switching frequency control instruction is used for controlling the power supply control device to set the switching frequency of the switching frequency control detection voltage.
Specifically, a power supply device and a power supply control device are generally included in a motherboard of the server. The power supply device and the power supply control device are respectively connected with the processor in the main board.
The processor may send a first voltage control instruction to the power supply device. The first voltage control instruction is used for controlling the power supply device to provide detection voltage for the bus device. The detection voltage may be less than the normal operating voltage of the bus device so that the bus device may be approximated as a resistor having a larger resistance value.
The processor also sends switching frequency control instructions to the power control device. The switching frequency control instruction is for controlling the power supply control device to set the switching frequency of the switching frequency control detection voltage. The set switching frequency may be set as desired, e.g., different bus devices set different set switching frequencies, so that the processor may identify the bandwidth required by different bus devices in the bus device slot at the same time.
The bus bandwidth allocation method provided by the embodiment of the application realizes the provision of the detection voltage for the bus equipment by sending the first voltage control instruction to the power supply equipment, and realizes the control of the switching frequency of the detection voltage by sending the switching frequency control instruction to the power supply control equipment.
In some embodiments, determining a bus bandwidth allocation value corresponding to a bus device based on the switching frequency detection value of each data channel includes:
Determining a switching frequency detection value of each data channel in the bus equipment slot and a channel position of each data channel;
Determining a data channel with adjacent channel positions and consistent switching frequency detection value with the set switching frequency as a target data channel;
Based on the number of target data channels, a bus bandwidth allocation value corresponding to the bus device is determined.
Specifically, the switching frequency of the voltage of each data channel in the bus device slot may be detected, to obtain a switching frequency detection value. The processor may set a channel frequency status register for storing the switching frequency detection values of the respective data channels. Channel location refers to the physical location of a data channel on a socket.
The processor may acquire the switching frequency detection value of each data channel from the channel frequency status register, compare the switching frequency detection values of each data channel, and if there are a plurality of data channels, the data channels satisfy that the channel positions are adjacent, and the switching frequency detection value is consistent with the set switching frequency, the data channels may be determined as the target data channels. The target data channel is the data channel actually used by the bus device.
According to the number of the target data channels, the number of the actually used data channels can be determined, and then the bus bandwidth allocation value is determined. For example, if there are 8 data channels in the PCIe X16 slot, where the channel positions of the 8 data channels are closely adjacent, and the detected switching frequency values of the 8 data channels are consistent with the set switching frequency, it may be determined that the 8 data channels are actually used by the bus device, and the slot specification is X8, and it is required to provide 8 times of bus bandwidth of X1.
According to the bus bandwidth allocation method provided by the embodiment of the application, the bus bandwidth allocation value corresponding to the bus equipment is determined according to the number of the data channels with adjacent channel positions and the switching frequency detection value consistent with the set switching frequency, so that the accuracy of determining the bus bandwidth allocation value is improved.
In some embodiments, before providing the detection voltage to the bus device inserted into the bus device slot and controlling the switching frequency of the detection voltage, the method further comprises:
and determining a detection voltage based on the working voltage of each bus device, wherein the detection voltage is smaller than the working voltage of each bus device.
Specifically, each bus device slot may be detected, and an operating voltage of each bus device inserted into each bus device slot may be obtained. In determining the detection voltage, a voltage value smaller than the operating voltage of the respective bus device may be selected as the detection voltage. For example, the operating voltages of the respective bus devices are 3.3 volts, 5 volts, and 12 volts, respectively, and 1 volt may be selected as the detection voltage.
The bus bandwidth allocation method provided by the embodiment of the application has the advantages that the detection voltage is smaller than the working voltage of each bus device, so that the voltage is only used for determining the bus bandwidth and the normal operation of the bus device is not influenced.
In some embodiments, sending a switching frequency control instruction to a power control device includes:
determining the set switching frequency corresponding to each bus device, wherein the set switching frequencies corresponding to each bus device are different;
Generating switching frequency control instructions corresponding to each bus device based on the set switching frequencies corresponding to each bus device;
Transmitting switching frequency control instructions corresponding to each bus device to power control devices corresponding to each bus device, so that the power control devices control the switching frequency of the detection voltage of each bus device;
or generating a switching frequency control instruction corresponding to the current bus equipment;
Transmitting a switching frequency control instruction corresponding to the current bus equipment to power control equipment corresponding to the current bus equipment so as to enable the power control equipment to control the switching frequency of the detection voltage of the current bus equipment;
And under the condition that the bus bandwidth allocation value corresponding to the current bus device is determined, switching the current bus device to the next bus device.
Specifically, the embodiment of the application provides two methods for sending a switching frequency control instruction to power supply control equipment.
The first method is suitable for parallel detection of bus devices in the bus device slots. The processor may set different set switching frequencies for each bus device such that one set switching frequency is used to detect one bus device.
And generating switching frequency control instructions corresponding to each bus device according to the set switching frequency corresponding to each bus device, and sending the switching frequency control instructions to power supply control devices corresponding to each bus device so that the power supply control devices control the switching frequency of the detection voltage of each bus device.
The second method is suitable for sequentially detecting the bus devices in the bus device slots according to a certain detection sequence. In each detection, a corresponding detection duration may be set for completing the detection within the detection duration.
Firstly, determining current bus equipment in a current detection process, and generating a switching frequency control instruction corresponding to the current bus equipment. Since sequential detection is employed in the method, two bus devices are not detected at the same time, and thus the switching frequencies corresponding to the respective bus devices may be the same.
And sending a switching frequency control instruction corresponding to the current bus equipment to power control equipment corresponding to the current bus equipment, so that the power control equipment controls the switching frequency of the detection voltage of the current bus equipment.
And under the condition that the bus bandwidth allocation value corresponding to the current bus device is determined, switching the current bus device to the next bus device. By the method, the bus bandwidth allocation values of the bus devices are determined one by one according to a certain detection sequence.
According to the bus bandwidth allocation method provided by the embodiment of the application, the plurality of bus devices can be detected simultaneously by setting different set switching frequencies, and each bus device can be detected sequentially according to a certain detection sequence, so that the accuracy of determining the bus bandwidth allocation value is improved.
In some embodiments, allocating bus bandwidth to a bus device based on a bus bandwidth allocation value comprises:
the second voltage control instruction is used for controlling the power supply equipment to provide working voltage for the bus equipment;
In the case of normal operation of the bus device, the bus device is allocated bus bandwidth based on the bus bandwidth allocation value.
Specifically, after determining the bus bandwidth allocation value of the bus device, the processor may send a second voltage control instruction to the power device, where the instruction is used to control the power device to provide an operating voltage to the bus device, so that the bus device may operate normally.
Under the condition that the bus equipment works normally, the processor allocates bus bandwidth for the bus equipment according to the bus bandwidth allocation value, so that the allocated bus bandwidth can meet the requirements of the bus equipment, and PCIe bus resource waste is avoided.
The apparatus provided by the embodiments of the present application will be described below, and the apparatus described below and the method described above may be referred to correspondingly.
Fig. 2 is a schematic structural diagram of a bus bandwidth allocation device according to the present application, as shown in fig. 2, the device includes:
a voltage generation module 210 for providing a detection voltage to the bus device inserted into the bus device slot and controlling a switching frequency of the detection voltage;
a frequency detection module 220, configured to obtain a switching frequency detection value of each data channel in the bus device slot;
a bandwidth determining module 230, configured to determine a bus bandwidth allocation value corresponding to the bus device based on the switching frequency detection value of each data channel;
The bandwidth allocation module 240 is configured to allocate bus bandwidth to the bus device based on the bus bandwidth allocation value.
The bus bandwidth allocation device provided by the embodiment of the application provides detection voltage for bus equipment inserted into a bus equipment slot and controls the switching frequency of the detection voltage, acquires the switching frequency detection value of each data channel in the bus equipment slot, determines the bus bandwidth allocation value corresponding to the bus equipment based on the switching frequency detection value of each data channel, allocates bus bandwidth for the bus equipment based on the bus bandwidth allocation value, detects the switching frequency of each data channel in the bus equipment slot by providing detection voltages with different switching frequencies for the bus equipment, determines the number of actually used data channels of the bus equipment by comparing the switching frequency detection values of each data channel, further determines the bus bandwidth allocation value, can accurately determine the bandwidth of the PCIe bus equipment and realize automatic allocation, avoids a processor from directly allocating the maximum bandwidth according to the bus equipment slot and avoids PCIe bus resource waste.
In some embodiments, the voltage generation module is to:
the first voltage control instruction is used for controlling the power supply equipment to provide detection voltage for the bus equipment;
And the switching frequency control instruction is used for controlling the power supply control device to set the switching frequency of the switching frequency control detection voltage.
In some embodiments, the bandwidth determination module is to:
Determining a switching frequency detection value of each data channel in the bus equipment slot and a channel position of each data channel;
Determining a data channel with adjacent channel positions and consistent switching frequency detection value with the set switching frequency as a target data channel;
Based on the number of target data channels, a bus bandwidth allocation value corresponding to the bus device is determined.
In some embodiments, the voltage generation module is further to:
and determining a detection voltage based on the working voltage of each bus device, wherein the detection voltage is smaller than the working voltage of each bus device.
In some embodiments, the voltage generation module is specifically configured to:
determining the set switching frequency corresponding to each bus device, wherein the set switching frequencies corresponding to each bus device are different;
Generating switching frequency control instructions corresponding to each bus device based on the set switching frequencies corresponding to each bus device;
Transmitting switching frequency control instructions corresponding to each bus device to power control devices corresponding to each bus device, so that the power control devices control the switching frequency of the detection voltage of each bus device;
or generating a switching frequency control instruction corresponding to the current bus equipment;
Transmitting a switching frequency control instruction corresponding to the current bus equipment to power control equipment corresponding to the current bus equipment so as to enable the power control equipment to control the switching frequency of the detection voltage of the current bus equipment;
And under the condition that the bus bandwidth allocation value corresponding to the current bus device is determined, switching the current bus device to the next bus device.
In some embodiments, the bandwidth allocation module is specifically configured to:
the second voltage control instruction is used for controlling the power supply equipment to provide working voltage for the bus equipment;
In the case of normal operation of the bus device, the bus device is allocated bus bandwidth based on the bus bandwidth allocation value.
Fig. 3 is a schematic diagram of a server according to the present application, and as shown in fig. 3, the server 300 includes a processor 310, a power device 320, a power control device 330, and a bus device slot 340.
And the bus device slot is used for inserting the bus device.
And the power supply device is used for providing detection voltage for the bus device.
And a power supply control device for controlling the switching frequency of the detection voltage.
And the processor is connected with the power supply device, the power supply control device and the bus device slot and is used for executing the bus bandwidth allocation method in the embodiment and allocating bus bandwidth for the bus device.
According to the server provided by the embodiment of the application, as the processor executes the bus bandwidth allocation method in the embodiment, the bandwidth of the PCIe bus device can be accurately determined and automatic allocation is realized, so that the processor is prevented from directly allocating the maximum bandwidth according to the bus device slot, and the PCIe bus resource waste is avoided.
Fig. 4 is a second flowchart of the bus bandwidth allocation method provided by the present application, as shown in fig. 4, the method is suitable for a server, and is specifically implemented by a basic input output system (Basic Input Output System, BIOS). The server and bus device employ a PCIe bus, then the bus device may also be referred to as a PCIe device. The method comprises the following specific steps:
step 410, inserting the PCIe device into a PCIe device slot in the server motherboard.
After the PCIe devices are inserted into the slots, data channel (Lane) ports of all PCIe devices are connected to a data channel (Lane) port of a Root port (PCIe Root port) of a Central Processing Unit (CPU) in the motherboard.
And step 420, setting eFUSE chips corresponding to the slots of each PCIe device.
The switch chip is used for controlling the on-off of the power supply and outputting voltages with different frequencies. The switch chip may be an eFUSE (electronic Fuse) chip or the like.
FIG. 5 is a circuit diagram of bus bandwidth allocation provided by the present application, as shown in FIG. 5, including a Central Processing Unit (CPU), power devices (DC/DC chips), power control devices (eFUSE chips), and PCIe device slots.
The BIOS system code runs in the central processing unit, and a system management Bus (SYSTEM MANAGEMENT Bus, SMBUS) of the central processing unit is connected with the power supply device and the switch chip. The BIOS forms switching signals with different frequencies by sending different switching commands to the power supply equipment and the switching chip connected with the MBUS bus.
Fig. 6 is a circuit structure diagram of a power supply device provided by the present application, as shown in fig. 6, U1 is a switching voltage regulator of a buck power management monolithic integrated circuit, which can output a driving current of 3 amperes (a), and has good linearity and load regulation characteristics, and a fixed output version has voltages of 3.3V, 5V and 12V, and is adapted to a slot position of a PCIe device. VIN is a power supply end, GND is a grounding end, 3.3V/5V/12V is an output end, and the middle of the VIN is provided with rectifying and voltage-stabilizing inductors L1 and L2 and diodes D1, D2 and D3. Capacitors C1, C2 and C3 are used for filtering. The output end of the switching voltage regulator U1 is connected with a resistor R1 to form a PCIe device slot power supply switching circuit, and the identification BIOS sends an opening signal to the switching circuit. The switch S1 is a switch chip and is used for controlling the on-off of the power supply and outputting voltages with different frequencies.
In step 430, at the start-up time, the BIOS uses an integrated circuit bus (Inter-INTEGRATED CIRCUIT, IIC) interface to set the output voltage of the power supply device for supplying power to the PCIe device to be 1V.
The power supply device may be a DC/DC (Direct Current/Direct Current) chip capable of converting a Direct voltage into a Direct voltage of a different voltage class.
In step 440, the BIOS sends a power-on signal at a different frequency to each eFUSE chip using the integrated circuit bus interface, and each PCIe device receives the 1V voltage power at the different frequency.
In step 450, the BIOS reads PCIe Lane frequency status register in CPU, and records that the bandwidth of the device is Xn when the same frequency starting signal exists in adjacent Lane on n CPUs, for example, the BIOS reads the starting signal with the same frequency exists in Lane connected with 4 CPU ends in one PCIe X16 device slot, and records that the bandwidth of the device is X4.
The frequency signals acquired by all Lanes of a certain PCIe X16 and the device bandwidth information in the device slot are shown in Table 1.
Table 1 device bandwidth information table
As can be clearly seen from the table, the BIOS reads that 4 identical frequency signals exist in adjacent Lane on the CPU after the BIOS is started, and the PCIe bandwidth is directly distributed to be X4, so that the PCIe devices can be randomly combined to achieve the purpose of use.
Step 460, the BIOS restores the DC/DC chip to the normal level output, allocates the bandwidth required by each PCIe device, allocates the bandwidth allocated by the BIOS as shown in the table as X4, combines each PCIe device with an independent power supply switch circuit or eFUSE chip, detects the CPU PCIe Lane frequency status register by BIOS software, acquires the same frequency starting signal existing in the adjacent Lane on the CPU, and realizes the automatic allocation of the PCIe device bandwidth.
According to the method provided by the embodiment of the application, only the power supply switch circuit of the PCIe equipment slot position is required to be established or the eFUSE chip is additionally arranged, and each switch circuit of the PCIe equipment slot position or the eFUSE chip after the startup is identified through the BIOS to send the starting signals with different frequencies, so that the total number of the equipment inserted by the PCIe equipment slot position can be quickly confirmed, and then a total bandwidth value can be directly allocated, the specific slot position can be identified, the identification precision is higher, the bandwidth allocation is more accurate and quicker, the bandwidth allocation efficiency is improved, and the effect that one PCIe slot is inserted with a plurality of equipment and is directly not influenced by the bandwidth can be realized.
Fig. 7 is a schematic structural diagram of an electronic device provided in the present application, as shown in fig. 7, the electronic device may include a Processor (Processor) 710, a communication interface (Communications Interface) 720, a Memory (Memory) 730, and a communication bus (Communications Bus) 740, where the Processor 710, the communication interface 720, and the Memory 730 complete communication with each other through the communication bus 740. Processor 710 may invoke logic commands in memory 730 to perform the methods described in the embodiments above, such as:
The method comprises the steps of providing detection voltage for bus equipment inserted into a bus equipment slot, controlling the switching frequency of the detection voltage, obtaining the switching frequency detection value of each data channel in the bus equipment slot, determining a bus bandwidth allocation value corresponding to the bus equipment based on the switching frequency detection value of each data channel, and allocating bus bandwidth for the bus equipment based on the bus bandwidth allocation value.
In addition, the logic commands in the memory described above may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in the form of a software product stored in a storage medium, comprising several commands for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present application. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes.
The processor in the electronic device provided by the embodiment of the application can call the logic instruction in the memory to realize the method, and the specific implementation mode is consistent with the implementation mode of the method, and the same beneficial effects can be achieved, and the detailed description is omitted here.
The embodiments of the present application also provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the methods provided by the above embodiments.
The specific embodiment is consistent with the foregoing method embodiment, and the same beneficial effects can be achieved, and will not be described herein.
The embodiments of the present application provide a computer program product comprising a computer program which, when executed by a processor, implements a method as described above.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
It should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present application, and not for limiting the same, and although the present application has been described in detail with reference to the above-mentioned embodiments, it should be understood by those skilled in the art that the technical solution described in the above-mentioned embodiments may be modified or some technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solution of the embodiments of the present application.
Claims (10)
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| CN119621349B (en) * | 2025-02-13 | 2025-09-26 | 苏州元脑智能科技有限公司 | Resource allocation method, server, storage medium and program product |
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