TWI763591B - Semiconductor device with copper-manganese liner and method for preparing the same - Google Patents

Abstract

The present disclosure provides a semiconductor device with a copper-manganese liner and a method for preparing the semiconductor device. The semiconductor device includes a first well region and a second well region disposed in a semiconductor substrate. The semiconductor device also includes a first dielectric layer disposed over the semiconductor substrate and covering the first well region and the second well region, and a gate structure disposed over the first dielectric layer and between the first well region and the second well region. The semiconductor device further includes a conductive structure disposed over and separated from the first well region by a portion of the first dielectric layer. The conductive feature includes a barrier layer and a conductive plug disposed over the barrier layer, and the barrier layer includes copper-manganese (CuMn). The first well region, the conductive structure and the portion of the first dielectric layer form an anti-fuse structure.

Description

Semiconductor element with copper-manganese lining layer and preparation method thereof

This application claims priority to and benefits from US Official Application Serial No. 17/232,992, filed April 16, 2021, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device and a manufacturing method thereof. In particular, it relates to a semiconductor element with a copper-manganese lining layer and a method for making the same.

For many modern applications, semiconductor components are indispensable. With the advancement of electronic technology, the size of semiconductor devices has become smaller and smaller, while providing better functions and including a larger number of integrated circuits. Due to the miniaturization of semiconductor devices, different types and sizes of semiconductor devices that implement different functions are integrated and packaged in a single module. Furthermore, many fabrication steps are performed in the integration of various types of semiconductor devices.

However, the fabrication and integration of these semiconductor devices involves many complex steps and operations. Integration in these semiconductor elements becomes increasingly complex. The increase in the complexity of the fabrication and integration of these semiconductor devices can result in defects such as voids formed in conductive structures due to difficulty in filling high aspect ratio openings. Accordingly, there has been continuous improvement in these The need for the manufacturing process of semiconductor components in order to deal with these defects.

The above description of the "prior art" only provides background art, and does not acknowledge that the above description of the "prior art" discloses the subject matter of the present disclosure, and does not constitute the prior art of the present disclosure, and any description of the above "prior art" is should not be part of this case.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor element has a first well region and a second well region, and is arranged in a semiconductor substrate. The semiconductor device also has a first dielectric layer disposed on the semiconductor substrate and covering the first well region and the second well region; and a gate structure disposed on the first dielectric layer and in the between the first well area and the second well area. The semiconductor device also has a conductive structure disposed on the first well region and separated from the first well region by a portion of the first dielectric layer. The conductive structure includes a barrier layer and a conductive plug, the conductive plug is disposed on the barrier layer, and the barrier layer includes copper manganese. The first well region, the conductive structure, and the portion of the first dielectric layer form an antifuse structure.

In one embodiment, the conductive plug of the conductive structure comprises copper. In one embodiment, the barrier layer covers a lower surface and sidewalls of the conductive plug. In one embodiment, the semiconductor device further includes a gate conductive plug disposed on the gate structure, wherein the conductive plug and the gate conductive plug of the conductive structure comprise different materials.

In one embodiment, the semiconductor device further includes a second dielectric layer disposed on the first dielectric layer, wherein the gate structure, the conductive structure and the gate conductive plug are disposed on the second dielectric layer, and wherein the first dielectric layer and the second dielectric layer comprise different materials. In one embodiment, the semiconductor device further includes a deep well region disposed in the semiconductor substrate, wherein the first well region and the second well region are disposed in the deep well region. In one embodiment, the The first well region and the second well region have a first conductivity type, and the deep well region has a second conductivity type opposite to the first conductivity type.

Another embodiment of the present disclosure provides a method for fabricating a semiconductor device. The preparation method includes forming a first well region and a second well region in a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate and covering the first well region and the second well region; forming a a gate structure on the first dielectric layer and between the first well region and the second well region; and forming a conductive structure on the first well region and through a portion of the first dielectric layer Separated from the first well region, wherein the conductive structure has a barrier layer and a conductive plug, the conductive plug is disposed on the barrier layer, and the barrier layer comprises copper manganese, wherein the first well region, The conductive structure and the portion of the first dielectric layer form an antifuse structure.

In one embodiment, the conductive structure includes copper, and the barrier layer covers a lower surface and sidewalls of the conductive plug.

In one embodiment, the fabrication method of the semiconductor device further includes forming a gate conductive plug on the gate structure, wherein the conductive plug and the gate conductive plug of the conductive structure comprise different materials.

In one embodiment, the fabrication method of the semiconductor device further includes forming a second dielectric layer on the first dielectric layer, wherein the gate structure, the conductive structure and the gate conductive plug are disposed on the second dielectric layer. In the dielectric layer, and wherein the first dielectric layer and the second dielectric layer comprise different materials.

In one embodiment, the method for fabricating the semiconductor device further includes forming a deep well region in the semiconductor substrate, wherein the first well region and the second well region are disposed in the deep well region.

In one embodiment, the first well region and the second well region have a first conductive type, and the deep well region has a second conductivity type opposite to the first conductivity type.

In one embodiment, the method for fabricating the semiconductor device further includes forming a third dielectric layer on the second dielectric layer; and forming a plurality of conductive layers in the third dielectric layer.

The present disclosure provides some embodiments of a semiconductor device and a method of fabricating the same. In some embodiments, the semiconductor device has a conductive structure (eg, an electrode or a conductive plug) and a copper-manganese lining or barrier layer, the conductive structure is disposed in a dielectric layer, the copper-manganese lining A layer or barrier layer separates the conductive structure from the dielectric layer. In some embodiments, the conductive structure includes copper, and the copper-manganese liner or barrier layer is configured to reduce or prevent voids from forming in the conductive structure, thereby reducing contact resistance and improving the Electromigration reliability of conductive structures. Therefore, device performance can be improved.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor element has a first electrode and a second electrode disposed in a first dielectric layer. The semiconductor element also has a first pad separating the first electrode from the first dielectric layer. The semiconductor element also has a fuse link disposed in the first dielectric layer. The fuse link is disposed between the first electrode and the second electrode, and is electrically connected to the first electrode and the second electrode, and wherein the fuse link and the first pad comprise copper manganese.

In one embodiment, the first electrode and the second electrode comprise copper. In one embodiment, the semiconductor device further includes a second pad separating the second electrode from the first dielectric layer, wherein the second pad comprises copper manganese. In one embodiment, the first pad, the second pad and the fuse link are connected to form a continuous structure. In one embodiment, an upper surface of the first pad and an upper surface of the first electrode are coplanar.

In one embodiment, the semiconductor element further includes a second dielectric layer, provided on the first dielectric layer; and a plurality of conductive contacts disposed in the second dielectric layer, wherein a first group of the plurality of conductive contacts is electrically connected to the first electrode, and the A second set of the plurality of conductive contacts is electrically connected to the second electrode. In one embodiment, the semiconductor device further includes a patterned mask disposed between the first dielectric layer and the second dielectric layer, wherein an upper surface of the fuse link and the patterned mask One of the upper surfaces is coplanar.

Yet another embodiment of the present disclosure provides a method for fabricating a semiconductor device. The preparation method includes forming an opening structure in a first dielectric layer. The opening structure has a first part, a second part and a third part, the third part is disposed between the first part and the second part, and physically connects the first part and the second part . The manufacturing method also includes forming a liner material to line the first portion and the second portion of the open-cell structure and completely fill the third portion of the open-cell structure. The backing material contains copper manganese. The preparation method further includes filling the first part and the second part of the opening structure with a conductive material after the spacer material is formed; and performing a planarization process on the spacer material and the conductive material .

In one embodiment, the first portion of the hole structure has a first width, the second portion of the hole structure has a second width, and the third portion of the hole structure has a third width , the second width and the third width are parallel to each other, and the first width and the second width are both larger than the third width. In one embodiment, forming the opening structure in the first dielectric layer includes using a patterned mask as an etch mask, and wherein the planarization process is performed until the patterned mask is exposed. In one embodiment, the conductive material includes copper.

In one embodiment, after the planarization process is performed, a remaining portion of the liner material in the third portion of the opening structure is configured as a fuse link, and the conductive material is in the opening structure A remaining portion in the first portion is configured as a first electrode, and a remaining portion of the conductive material in the second portion of the aperture structure is configured as a second electrode, wherein the first The electrode, the second electrode and the fuse link form a fuse structure. In one embodiment, the fabrication method further includes forming a second dielectric layer on the fuse structure; and forming a plurality of conductive contacts to pass through the second dielectric layer, wherein among the plurality of conductive contacts A first group of the plurality of conductive contacts is electrically connected to the first electrode, and a second group of the plurality of conductive contacts is electrically connected to the second electrode.

The present disclosure provides some embodiments of a semiconductor device and a method of fabricating the same. In some embodiments, the semiconductor device has a conductive structure (eg, an electrode or a conductive plug) and a copper-manganese lining or barrier layer, the conductive structure is disposed in a dielectric layer, the copper-manganese lining A layer or barrier layer separates the conductive structure from the dielectric layer. In some embodiments, the conductive structure includes copper, and the copper-manganese liner or barrier layer is configured to reduce or prevent voids from forming in the conductive structure, thereby reducing contact resistance and improving the performance of the conductive structure Electromigration reliability. Therefore, device performance can be improved.

The foregoing has outlined rather broadly the technical features and advantages of the present disclosure in order that the detailed description of the present disclosure that follows may be better understood. Additional technical features and advantages that form the subject of the scope of the present disclosure are described below. It should be understood by those skilled in the art to which this disclosure pertains that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims.

10: Preparation method

100: Semiconductor Components

103: first dielectric layer

105: Patterned Masks

110: Opening structure

110a: Part 1

110b: Part II

110c: Part III

120: Opening structure

120a: Part 1

120b: Part II

120c: Part III

123: Padding material

125a: First pad

125b: Second pad

125c: fuse link

133: Conductive Materials

135a: first electrode

135b: second electrode

141: Second Dielectric Layer

143: Conductive Contacts

200: Semiconductor Components

201: Semiconductor substrates

203: Insulation structure

205: Deep Well District

207: First Dielectric Layer

207': part

209: Gate Dielectric Layer

211: gate electrode layer

213: Gate structure

215: Gate spacer

217: The first well area

219: The second well area

221: Second Dielectric Layer

223: Patterned Mask

230: Opening

240: Opening

243: Barrier Materials

245: Barrier Layer

253: Conductive Materials

255: Conductive plug

257: Conductive Structure

263: Patterned Mask

270: Opening

280: Opening

283: Gate conductive plug

291: Third Dielectric Layer

293: Conductive layer

295: Conductive layer

30: Preparation method

300: Antifuse structure

S11: Steps

S13: Steps

S15: Steps

S17: Steps

S19: Steps

S21: Steps

S23: Step

S31: Step

S33: Step

S35: Steps

S37: Step

S39: Steps

S41: Steps

S43: Step

T1: upper surface

T2: Top surface

T3: Top surface

T4: Top surface

W1: width

W2: width

W3: width

A more complete understanding of the disclosure of the present application can be obtained by referring to the embodiments and the scope of the application in conjunction with the drawings, and the same reference numerals in the drawings refer to the same elements.

FIG. 1 is a schematic top view illustrating a semiconductor device according to some embodiments of the present disclosure.

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device along the line A-A' of FIG. 1 according to some embodiments of the present disclosure.

FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device along the line B-B' of FIG. 1 according to some embodiments of the present disclosure.

4 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

FIG. 5 is a schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure.

FIG. 6 is a schematic flowchart illustrating the fabrication methods of semiconductor devices according to some other embodiments of the present disclosure.

7 is a schematic top view illustrating an intermediate stage of forming an opening structure in a first dielectric layer during semiconductor device formation according to some embodiments of the present disclosure.

FIG. 8 is a schematic cross-sectional view illustrating an intermediate stage of forming a semiconductor device along the line A-A' of FIG. 7 in some embodiments of the present disclosure.

FIG. 9 is a schematic cross-sectional view illustrating an intermediate stage of forming a semiconductor device along line B-B' of FIG. 7 according to some embodiments of the present disclosure.

10 is a schematic cross-sectional view illustrating an intermediate stage of forming a liner material in an aperture structure during semiconductor device formation along the same cross-section of FIG. 8 in some embodiments of the present disclosure.

11 is a schematic cross-sectional view illustrating an intermediate stage of forming a liner material in an aperture structure during semiconductor device formation along the same cross-section of FIG. 9 in some embodiments of the present disclosure.

FIG. 12 is a schematic cross-sectional view illustrating an intermediate stage of filling the aperture structure with a conductive material during formation of a semiconductor device along the same cross-section of FIG. 10 according to some embodiments of the present disclosure.

13 is a schematic cross-sectional view illustrating an intermediate stage of filling the aperture structure with a conductive material during the formation of semiconductor devices along the same cross-section of FIG. 11 in some embodiments of the present disclosure.

14 is a schematic top view illustrating an intermediate stage of performing a planarization process during semiconductor device formation according to some embodiments of the present disclosure.

15 is a schematic cross-sectional view illustrating an intermediate stage of forming a semiconductor device along line A-A' of FIG. 14 in some embodiments of the present disclosure.

FIG. 16 is a schematic cross-sectional view illustrating an intermediate stage of forming a semiconductor device along line B-B' of FIG. 14 according to some embodiments of the present disclosure.

17 is a schematic cross-sectional view illustrating an intermediate stage of forming a first dielectric layer on a semiconductor substrate during semiconductor device formation according to some other embodiments of the present disclosure.

18 is a schematic cross-sectional view illustrating intermediate stages of forming a gate structure on a first dielectric layer and forming a plurality of wells in a semiconductor substrate during semiconductor device formation according to some other embodiments of the present disclosure.

19 is a schematic cross-sectional view illustrating intermediate stages of forming a second dielectric layer on the first dielectric layer and forming an opening in the second dielectric layer during semiconductor device formation according to some other embodiments of the present disclosure.

20 is a schematic cross-sectional view illustrating intermediate stages of sequentially forming a barrier material and a conductive material in openings during semiconductor device formation in some other embodiments of the present disclosure.

21 is a schematic cross-sectional view illustrating intermediate stages of planarizing barrier and conductive materials during semiconductor device formation according to some other embodiments of the present disclosure.

22 is a schematic cross-sectional view illustrating an intermediate stage of forming a gate conductive plug on the gate structure during semiconductor device formation in some other embodiments of the present disclosure.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are for illustration only, and are not intended to limit the scope of the present disclosure. for example In other words, the description where the first part is formed on the second part may include embodiments in which the first and second parts are in direct contact, and may also include additional parts formed between the first and second parts such that the first and second parts are formed in direct contact with each other. Embodiments in which the first and second parts do not come into direct contact. Additionally, embodiments of the present disclosure may repeat reference numerals and/or letters in many instances. These repetitions are for the purpose of simplicity and clarity, and do not in themselves represent a specific relationship between the various embodiments and/or the configurations discussed, unless the context specifically indicates otherwise.

Furthermore, for ease of description, spaces such as "beneath", "below", "lower", "above", "upper", etc. may be used herein. Relative terms are used to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 is a schematic top view illustrating a semiconductor device 100 according to some embodiments of the present disclosure. 2 and 3 are schematic cross-sectional views, respectively illustrating semiconductor devices along the line A-A' and the line B-B' of FIG. 1 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100 is a fuse structure. As shown in FIG. 1 to FIG. 3, the semiconductor device 100 has a first dielectric layer 103; a patterned mask 105 disposed on the first dielectric layer 103; and a second dielectric layer 141 disposed on the pattern on the mask 105. It should be understood that the second dielectric layer 141 shown in FIGS. 2 and 3 is not shown in the top view of FIG. 1 in order to simplify the drawing.

Furthermore, the semiconductor device 100 has a first electrode 135a, a second electrode 135b, a first pad 125a, a second pad 125b, and a fuse link 125c, and the fuse link 125c is disposed on the first dielectric layer 103. In some embodiments, according to some embodiments, the first The electrode 135a, the second electrode 135b, the first pad 125a, the second pad 125b, and the lower portions of the fuse link 125c are embedded in the first dielectric layer 103, and the first electrode 135a, the second electrode 135b, the first The pads 125 a , the second pads 125 b , and the respective upper portions of the fuse links 125 c are embedded in the patterned mask 105 .

In some embodiments, the first electrode 135a is separated from the second electrode 135b, and the fuse link 125c is disposed between the first electrode 135a and the second electrode 135b and is electrically connected to the first electrode 135a and the second electrode electrode 135b. In some embodiments, the first electrode 135a is surrounded by the first pad 125a, and the second electrode 135b is surrounded by the second pad 125b. In some embodiments, the sidewalls and the lower surface of the first electrode 135a are covered by the first pad 125a, and the sidewalls and lower surface of the second electrode 135b are covered by the second pad 125b. In other words, the first electrode 135a is separated from the first dielectric layer 103 and the patterned mask 105 by the first pad 125a, and the second electrode 135b is separated from the first dielectric layer by the second pad 125b 103 and the patterned mask 105 are separated.

It should be understood that the first pad 125a, the second pad 125b and the fuse link 125c are physically connected to form a continuous structure with no interface therebetween. The dotted lines indicating the boundaries of the first pad 125a, the second pad 125b, and the fuse link 125c in FIG. 1 are for clarity of the present disclosure. There is no obvious interface between the first pad 125a, the second pad 125b and the fuse link 125c. In some embodiments, the fabrication techniques of the first pad 125a, the second pad 125b and the fuse link 125c include the same process and include the same material. In some embodiments, for example, the first pad 125a, the second pad 125b, and the fuse link 125c include copper manganese, and the first electrode and the second electrode include copper.

Still referring to FIGS. 1 to 3 , the semiconductor device 100 further has a plurality of conductive contact points 143 disposed in the second dielectric layer 141 . In some embodiments, the conductive contacts A first group of the conductive contacts 143 is disposed on the first electrode 135a and is electrically connected to the first electrode 135a, and a second group of the conductive contacts 143 is disposed on the second electrode 135b and is electrically connected to the first electrode 135b. Two electrodes 135b. Although only three conductive contacts 143 are shown on each of the first and second electrodes 135a and 135b in FIG. 1, any number of conductive contacts 143 may be provided on the first and second electrodes 135a and 135b.

FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device 200 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 200 has an antifuse structure 300, which will be described in detail later.

As shown in FIG. 4, the semiconductor device 200 has a semiconductor substrate 201; a plurality of insulating structures 203 disposed in the semiconductor substrate 201; a deep well region 205 disposed in the semiconductor substrate 201 and between the insulating structures 203; and A first well area 217 and a second well area 219 are provided in the deep well area 205 . In some embodiments, the first well region 217 and the second well region 219 have a first conductivity type, the deep well region 205 has a second conductivity type, and the second conductivity type is opposite to the first conductivity type. For example, the deep well region 205 is lightly doped with a p-type dopant, while the first well region 217 and the second well region 219 are heavily doped with an n-type dopant.

Furthermore, in some embodiments, the semiconductor device 200 has a first dielectric layer 207 disposed on the semiconductor substrate 201 and covering the first well region 217 and the second well region 219; a gate structure 213 and a conductive structure 257 , disposed on the first dielectric layer 207 ; and a gate conductive plug 283 , disposed on the gate structure 213 . In some embodiments, the gate structure 213 is disposed between the first well region 217 and the second well region 219 , and the conductive structure 257 is disposed on the first well region 217 . It should be understood that the conductive structure 257 is separated from the first well region 217 by a portion of the first dielectric layer 207 .

In some embodiments, the gate structure 213 has a gate dielectric layer 209 and A gate electrode layer 211 is disposed on the gate dielectric layer 209 . In some embodiments, a plurality of gate spacers 215 are disposed on opposite sidewalls of the gate structure 213 . In addition, the conductive structure 257 has a barrier layer 245 and a conductive plug 255 , and the conductive plug 255 is disposed on the barrier layer 245 . In some embodiments, the barrier layer 245 covers a lower surface of the conductive plug 255 and each sidewall. In some embodiments, the barrier layer 245 includes copper manganese, and the conductive plug 255 includes copper, for example.

Still referring to FIG. 4, the semiconductor device 200 further has a second dielectric layer 221 disposed on the first dielectric layer 207; a third dielectric layer 291 disposed on the second dielectric layer 221; and a conductive layer 293 and 295 are disposed in the third dielectric layer 291 . In some embodiments, the gate structure 213 , the conductive structure 257 , and the gate conductive plug 283 are disposed in the second dielectric layer 221 . In some embodiments, the conductive layer 293 is disposed on the conductive structure 257 and is electrically connected to the conductive structure 257, and the conductive layer 295 is disposed on the gate structure 213 and is electrically connected to the gate structure through the gate conductive plug 283 213.

In some embodiments, the first dielectric layer 207 has a portion 207' sandwiched between the conductive structure 257 and the first well region 217. It should be understood that the first well region 217 , the conductive structure 257 , and the portion 207 ′ of the first dielectric layer 207 together form the antifuse structure 300 . The conductive structure 257 can be regarded as the upper electrode of the antifuse structure 300 , and the first well region 217 can be regarded as the lower electrode of the antifuse structure 300 .

5 is a schematic flowchart illustrating a method 10 for fabricating a semiconductor device (eg, the semiconductor device 100 ) according to some embodiments of the present disclosure, and the fabrication method 10 includes steps S11 , S13 , S15 , S17 , S19 , and S21 . 6 is a schematic flowchart illustrating a method 30 for fabricating a semiconductor device (eg, the semiconductor device 200 ) according to some other embodiments of the present disclosure, and the fabrication method 30 includes steps S31 , S33 , S35 , S37 , S39 , S41 , and S43 . Steps S11 to S21 of FIG. 5 and FIG. 6 The steps S31 to S43 of 1 are described in detail in conjunction with the following figures.

FIG. 7 is a schematic top view illustrating an intermediate stage of forming an opening structure 120 in a first dielectric layer 103 during the formation of the semiconductor device 100 according to some embodiments of the present disclosure. FIG. 8 is a schematic cross-sectional view illustrating an intermediate stage of forming a semiconductor device along the line A-A' of FIG. 7 in some embodiments of the present disclosure. FIG. 9 is a schematic cross-sectional view illustrating an intermediate stage of forming a semiconductor device along line B-B' of FIG. 7 according to some embodiments of the present disclosure. As shown in FIG. 7 to FIG. 9 , a first dielectric layer 103 is provided, and a patterned mask 105 having an opening structure 110 is formed on the first dielectric layer 103 .

In some embodiments, the first dielectric layer 103 includes silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other dielectric materials. The first dielectric layer 103 may be formed on a semiconductor substrate (not shown), such as a portion of an interlayer dielectric (ILD) layer or an interlayer metal dielectric (IMD) layer in a semiconductor wafer. In addition, the opening structure 110 in the patterned mask 105 has a first portion 110a, a second portion 110b and a third portion 110c, and the third portion 110c is disposed between the first portion 110a and the second portion 110b and connected to the first part 110a and the second part 110b.

As shown in FIGS. 7 to 9 , according to some embodiments, an etching process is performed using the patterned mask on the first dielectric layer 103 as an etching mask, so that an opening structure 110 is formed on the first dielectric layer 103 . in the dielectric layer 103 . The corresponding steps are shown in step S11 of the method 10 shown in FIG. 5 . In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof, and the opening structure 110 is transformed from the patterned mask 105 to the first dielectric layer 103 to form the opening structure 120 .

In some embodiments, the opening structure 120 does not pass through the first dielectric layer 103 . Similar to the pattern of the aperture structure 110 in the patterned mask 105, the aperture structure 120 has a first portion 120a, a second portion 120b, and a third portion 120c, and the third portion 120c is disposed on the first portion 120a. between the part 120a and the second part 120b and connected to the first part 120a and the second part 120b. In some embodiments, the first portion 110 a of the hole structure 110 and the first portion 120 a of the hole structure 120 have a width W1 (please refer to FIG. 8 ), and the third portion 110 c of the hole structure 110 and the hole structure 120 have a width W1 (please refer to FIG. 8 ). The third portion 120c has a width W2 (please refer to FIG. 9 ), and the width W1 is greater than the width W2.

Since the contours of the second portion 110b of the hole structure 110 and the second portion 120b of the hole structure 120 are similar to the first portion 110a of the hole structure 110 and the first portion 120a of the hole structure 120, they are not shown. A schematic cross-sectional view along the second portions 110b and 120b. In some embodiments, the second portion 110b of the hole structure 110 and the second portion 120b of the hole structure 120 have a width (not shown), which is substantially the same as the width W1 in FIG. 8 . Therefore, the widths of the second portions 110b and 120b are also greater than the widths W2 of the third portions 110c and 120c. It should be understood that the widths W1, W2 and W3 are parallel to each other.

10 is a schematic cross-sectional view illustrating the formation of a liner material 123 in the aperture structure 110 during formation of the semiconductor device 100 along the same cross-section (ie, cross-section AA') of FIG. 8 according to some embodiments of the present disclosure intermediate stage. 11 is a schematic cross-sectional view illustrating the formation of a liner material 123 in the aperture structure 120 during the formation of the semiconductor device 100 along the same cross-section (ie, cross-section BB') of FIG. 9 according to some embodiments of the present disclosure. intermediate stage. As shown in FIGS. 10 and 11 , a liner material 123 is conformally deposited in the apertured structures 110 and 120 and on the upper surface of the patterned mask 105 . The corresponding steps are shown in step S13 of the method 10 shown in FIG. 5 .

The first parts 110 a and 120 a and the second parts 110 b and 120 b of the opening structures 110 and 120 have widths which are larger than the widths of the third parts 110 c and 120 c of the opening structures 110 and 120 . Thus, the third portions 110c, 120c are completely filled with the cushion material 123, while the first portions 110a, 120a and the second portions 110b, 120b are partially filled with the cushion material 123. In some embodiments, the sidewalls of the first portion 110a and the second portion 110b and the lower surfaces of the first portion 120a and the second portion 120b and The side walls are lined with a backing material 123 . In some embodiments, the liner material 123 includes copper-manganese, and the fabrication technique includes a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process ) process or a combination thereof.

12 is a schematic cross-sectional view illustrating that a conductive material 133 fills the middle of the opening structure 110 during the formation of the semiconductor device 100 along the same cross-section line (ie, cross-section line AA') of FIG. 10 according to some embodiments of the present disclosure stage. 13 is a schematic cross-sectional view illustrating an intermediate stage of filling the opening structure with a conductive material 133 during the formation of the semiconductor device 100 along the same cross-section (ie, cross-section AA') of FIG. 11 according to some embodiments of the present disclosure .

As shown in FIGS. 12 and 13 , a conductive material 133 is formed in the aperture structures 110 , 120 and on the upper surface of the patterned mask 105 . The corresponding steps are shown in step S15 of the method 10 shown in FIG. 5 . In some embodiments, the conductive material 133 includes copper, and the fabrication technique includes a deposition process, such as a CVD process, an ALD process, a PVD process, a sputtering process, a plating process, or a combination thereof. It should be understood that, according to some embodiments, the remaining first portions 110 a , 120 a and the remaining second portions 110 b , 120 b of the opening structures 110 , 120 are completely filled with the conductive material 133 .

FIG. 14 is a schematic top view illustrating an intermediate stage of performing a planarization process during the formation of semiconductor device 100 in some embodiments of the present disclosure. 15 is a schematic cross-sectional view illustrating an intermediate stage of forming a semiconductor device along line A-A' of FIG. 14 in some embodiments of the present disclosure. FIG. 16 is a schematic cross-sectional view illustrating an intermediate stage of forming a semiconductor device along line B-B' of FIG. 14 according to some embodiments of the present disclosure. As shown in FIGS. 14-16 , a planarization process is performed on the liner material 123 and the conductive material 133 until the patterned mask 105 is exposed. The corresponding steps are shown in step S17 of the method 10 shown in FIG. 5 .

The planarization process may include a chemical mechanical polishing (CMP) process. in some real In an embodiment, the planarization process removes excess portions of the liner material 123 and the conductive material 133 outside the opening structure 110 in the patterned mask 105 and outside the opening structure 120 in the first dielectric layer 103 . As a result, a remaining portion of the gasket material 123 in the first portion 110a, 120a of the open-cell structures 110, 120 is configured as the first gasket 125a, the gasket material 123 in the second portion of the open-cell structure 110, 120 is configured as the first gasket 125a A remaining portion of the portion 110b, 120b is configured as the second pad 125b, and a remaining portion of the pad material 123 in the third portion 110c, 120c of the aperture structure 110, 120 is configured as a fuse link 125c.

Furthermore, after the planarization process is performed, a remaining portion of the conductive material 133 in the first portions 110a, 120a of the opening structures 110, 120 is configured as the first electrode 135a, and the conductive material 133 is in the opening structure 110 A remaining portion of the second portions 110b, 120b of , 120 is configured as a second electrode 135b. As shown in FIGS. 15 and 16 , the patterned mask 105 has an upper surface T1, the first electrode 135a has an upper surface T2, the first pad 125a has an upper surface T3, and the fuse link 125c has an upper surface T4 . In some embodiments, the upper surfaces T1, T2, T3, T4 are substantially coplanar with each other. In the present disclosure, the word "substantially" means preferably at least 90%, more preferably 95%, still more preferably 98%, and most preferably 99%.

Referring to FIGS. 1 to 3 , according to some embodiments, after the planarization process, the second dielectric layer 141 is formed on the patterned mask 105 . The corresponding steps are shown in step S19 of the method 10 shown in FIG. 5 . The second dielectric layer 141 may include silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other dielectric materials, and the fabrication technique may include a deposition process, such as a CVD process, an ALD process, a PVD process, A spin coating process or a combination thereof.

As shown in FIGS. 1 to 3 , according to some embodiments, after the second dielectric layer 141 is formed, a plurality of conductive contact points 143 are formed to pass through the second dielectric layer 141 and then contact the first electrode 135 a and the second electrode 135 a electrode 135b. The corresponding steps are shown in the steps in the method 10 shown in FIG. 5 Step S21. In some embodiments, the conductive contacts 143 comprise a conductive material such as tungsten, aluminum, titanium, tantalum, gold, silver, copper, or combinations thereof.

In some embodiments, the fabrication techniques of the conductive contacts 143 include forming a plurality of openings (not shown) in the second dielectric layer 141 to expose the first dielectric electrodes 135a and the second electrodes 135b surface; and filling the openings with a conductive material. The fabrication technique of the openings may include an etching process using a patterned mask as an etch mask, and the fabrication technique of the conductive material may include a deposition process, such as a CVD process or an ALD process. Then, a planarization process, such as chemical mechanical polishing, may be performed to remove any excess material on the upper surface of the second dielectric layer 141 .

After the conductive contacts 143 are formed, the semiconductor element 100 is obtained. In this embodiment, the first pad 125a and the second pad 125b include copper manganese, and the first electrode 135a and the second electrode 135b include copper. The copper-manganese liners (ie, the first and second liners 125a and 125b ) can reduce or prevent a plurality of voids from being formed in the first and second electrodes 135a and 135b, thereby reducing contact resistance and reducing contact resistance. The electromigration reliability of the first electrode 135a and the second electrode 135b is improved. Therefore, device performance can be improved. In addition, since the fabrication techniques of the fuse link 125c, the first pad 125a, and the second pad 125b may include using the same process and may include the same material, the fabrication cost may be reduced.

17-22 are schematic cross-sectional views illustrating intermediate stages during the formation of the semiconductor device 200 in some other embodiments of the present disclosure. As shown in FIG. 17, a semiconductor substrate 201 is provided. The semiconductor substrate 201 can be a semiconductor wafer, such as a silicon wafer.

Alternatively or additionally, the semiconductor substrate 201 may include elemental semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of elemental semiconductor materials may include crystal silicon, polycrystalline silicon silicon), amorphous silicon, germanium and/or diamond, but not limited thereto. Examples of compound semiconductor materials may include silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or antimonide Indium (indium antimonide), but not limited thereto. Examples of alloy semiconductor materials may include silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInAs) ( GaInP) and gallium indium arsenide phosphide (GaInAsP), but not limited thereto.

In some embodiments, the semiconductor substrate 201 includes an epitaxial layer. For example, the semiconductor substrate 201 has an epitaxial layer covering the bulk semiconductor. In some embodiments, the semiconductor substrate 201 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer, and a semiconductor layer, and the buried oxide layer The material layer is located on the substrate, the semiconductor layer is located on the buried oxide layer, and the semiconductor-on-insulator substrate is such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (silicon germanium) -on-insulator, SGOI) substrate or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates may be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and/or other suitable methods.

Still referring to FIG. 17 , according to some embodiments, the insulating structures 203 are formed in the semiconductor substrate 201 to define a plurality of active regions, and the insulating structures 203 are shallow trench isolation (STI) structures. In addition, the insulating structures 203 may include silicon oxide, silicon nitride, silicon oxynitride or other applicable dielectric materials, and the fabrication technology of the insulating structures 203 may include forming a patterned mask (not shown) on the semiconductor substrate 201; by using the patterned mask as a The etch mask etches the semiconductor substrate 201 to form openings (not shown); deposits a dielectric material in the openings and on the semiconductor substrate 201; and planarizes the dielectric material until the semiconductor substrate 201 is exposed until.

Furthermore, in some embodiments, deep well regions 205 are formed in the active regions defined by the insulating structures 203 . In some embodiments, the fabrication technique of the deep well region 205 includes one or more ion implantation processes, and a plurality of P-type dopants or a plurality of N-type dopants can be implanted in the semiconductor substrate 201 to form the deep well region 205. The implantation of P-type dopants or N-type dopants depends on the conductivity type of the semiconductor device 200, P-type dopants such as boron, gallium or indium, and N-type dopants such as phosphorus or arsenic.

Still referring to FIG. 17 , according to some embodiments, a first dielectric layer 207 is formed on the semiconductor substrate 201 and covers the insulating structures 203 and the deep well region 205 . In some embodiments, the first dielectric layer 207 may include silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other dielectric materials, and the fabrication technique includes a deposition process, such as a CVD process, an ALD process process, a PVD process, a spin coating process, or a combination thereof.

Next, as shown in FIG. 18, according to some embodiments, a gate structure 213 having a gate dielectric layer 209 and a gate electrode layer 211 is formed on the first dielectric layer 207, and a plurality of gate spacers are formed on on opposite side walls of the gate structure 213 . The corresponding steps are shown in step S33 of the method 30 shown in FIG. 6 . In some embodiments, the gate dielectric layer 209 includes silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, a dielectric material having a high dielectric constant (high-k), or a combination thereof, and the gate electrode Layer 211 includes polysilicon, a metal material (eg, aluminum, copper, tungsten, titanium, tantalum), a metal silicide material, or a combination thereof.

In some embodiments, the fabrication technique of the gate structure 213 includes sequentially forming a gate dielectric material (not shown) and a gate electrode material (not shown) through a plurality of deposition processes on the first dielectric layer 207 . Deposition processes may include CVD, ALD, PVD, sputtering, electroplating, or combinations thereof. Then, an etching process is performed on the gate dielectric material and the gate electrode material using a patterned mask (not shown) as an etching mask. The etching process may include a wet etching process, a dry etching process, or a combination thereof. After the gate structure 213 is formed, the patterned mask can be removed.

In some embodiments, the gate spacers 215 comprise silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, other applicable dielectric materials, or combinations thereof. In some embodiments, the fabrication techniques for the gate spacers 215 include conformally depositing a spacer material (not shown) on the top surface and sidewalls of the gate structure 213 and on the first dielectric layer 207 on the upper surface. The deposition process may include a CVD process, a PVD process, an ALD process, a spin coating process or other applicable processes. Then, the spacer material is etched by an anisotropic etching process that vertically removes the same amount of the spacer material at all locations, leaving the gate spacers 215 on the sidewalls of the gate structure 213 superior. In some embodiments, the etching process is a dry etching process.

Furthermore, after the gate spacers 215 are formed, the first well region 217 and the second well region 219 are formed in the semiconductor substrate 201 . In some embodiments, the first well region 217 and the second well region 219 are formed in the deep well region 205 and on opposite sides of the gate structure 213 . The corresponding steps are shown in step S35 of the method 30 shown in FIG. 6 . In some embodiments, the fabrication technique of the first well region 217 and the second well region 219 includes an ion implantation process using the gate structure 213 and the gate spacers 215 as an implantation mask.

Some of the dopants used to form the first well region 217 and the second well region 219 are similar to or the same as the dopants used to form the deep well region 205, and their detailed descriptions are not repeated herein. In some embodiments, the conductivity types of the dopants in the first well region 217 are the same as those in the first well region 217 The conductivity types of the dopants in the second well region 219 , and the conductivity types of the dopants in the first well region 217 are opposite to those in the deep well region 205 . In addition, the implantation dose of the first well region 217 and the second well region 219 may be greater than the implantation dose of the deep well region 205 .

Next, as shown in FIG. 19 , according to some embodiments, a second dielectric layer 221 is formed on the first dielectric layer 207 and covers the gate structure 213 and the gate spacers 215 . The corresponding steps are shown in step S37 of the method 30 shown in FIG. 6 . The second dielectric layer 221 may include silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other dielectric materials, and the fabrication technique includes a deposition process, such as a CVD process, an ALD process, a PVD process, A spin coating process or a combination thereof. In some embodiments, the second dielectric layer 221 and the first dielectric layer 207 comprise different materials.

Still referring to FIG. 19, according to some embodiments, a patterned mask 223 having an opening 230 is formed on the second dielectric layer 221, and the patterned mask 223 is used as an etch mask on the second dielectric layer 221. An etching process is performed on the electrical layer 221 to transform the opening 230 from the patterned mask 223 to the second dielectric layer 221 and to obtain an opening 240 exposing the first dielectric layer 207 . In some embodiments, the openings 230 , 240 are formed on the first well region 217 . In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof.

As shown in FIG. 20, according to some embodiments, after the opening 240 is formed in the second dielectric layer 221, a barrier material 243 and a conductive material 253 are sequentially formed in the openings 230, 240 and patterning on the upper surface of the mask 223. In some embodiments, conductive material 253 is separated from first dielectric layer 207 , second dielectric layer 221 , and patterned mask 223 by barrier material 243 .

In some embodiments, the barrier material 243 comprises copper manganese, and its fabrication technique Including a deposition process, such as a CVD process, an ALD process, a PVD process or a combination thereof. In some embodiments, the conductive material 253 includes copper, and the fabrication technique includes a deposition process, such as a CVD process, an ALD process, a PVD process, a sputtering process, a plating process, or combinations thereof.

Next, as shown in FIG. 21 , according to some embodiments, a planarization process, such as a CMP process, is performed on the patterned mask 223 , the barrier material 243 and the conductive material 253 to remove the second dielectric layer 221 any excess material on the upper surface in order to obtain the conductive structure 257 with the conductive plug 255 and the barrier layer 245. The corresponding steps are shown in step S39 of the method 30 shown in FIG. 6 .

Still referring to FIG. 21, according to some embodiments, a patterned mask 263 having an opening 270 is formed on the second dielectric layer 221, and the patterned mask 263 is used as an etch mask on the second dielectric layer 221. An etching process is performed on the two dielectric layers 221 to transform the opening 270 from the patterned mask 263 to the second dielectric layer 221 , and an opening 280 exposing the gate structure 213 is obtained. In some embodiments, a portion of the gate electrode layer 211 is exposed through the opening 280 . In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof.

As shown in FIG. 22 , according to some embodiments, after the opening 280 on the gate structure 213 is formed, a gate conductive plug 283 is formed to fill the opening 280 . The corresponding steps are shown in step S41 of the method 30 shown in FIG. 6 . In some embodiments, the gate conductive plug 283 includes a conductive material such as tungsten, aluminum, titanium, tantalum, gold, silver, copper, or combinations thereof. The fabrication technique of the gate conductive plug 283 may include a deposition process (eg, CVD, ALD, or PVD) followed by a planarization process (eg, CMP).

Referring back to FIG. 4 , according to some embodiments, the third dielectric layer 291 is formed on the second dielectric layer 221 , and the conductive layers 293 , 295 are formed in the third dielectric layer 291 . its corresponding The steps are shown in step S43 of the method 30 shown in FIG. 6 . Some materials and processes used to form the third dielectric layer 291 are similar to or the same as those used to form the second dielectric layer 221 , and detailed descriptions thereof will not be repeated herein.

In some embodiments, conductive layer 293 is formed on and electrically connected to conductive structure 257 , and conductive layer 295 is formed on and electrically connected to gate conductive plug 283 . In some embodiments, the conductive layers 293, 295 comprise a conductive material such as tungsten, aluminum, titanium, tantalum, gold, silver, copper, or combinations thereof. The fabrication techniques of the conductive layers 293, 295 may include using a patterned mask as an etching mask to form a plurality of openings (not shown) in the third dielectric layer 291; forming a conductive material in the openings. in the holes and on the third dielectric layer 291; and performing a planarization process (eg, CMP) to remove any excess material on the upper surface of the third dielectric layer 291.

After the conductive layers 293 and 295 are formed, the semiconductor element 200 having the antifuse structure 300 is obtained. In this embodiment, the barrier layer 245 includes copper-manganese, and the conductive plug 255 includes copper. The copper-manganese liners (ie, the barrier layer 245 ) can reduce or avoid the formation of multiple voids in the conductive plug 255 , thereby reducing contact resistance and improving the electromigration reliability of the conductive plug 255 . Therefore, device performance can be improved.

The present disclosure provides some embodiments of semiconductor devices 100 , 200 and methods of making the same. In some embodiments, the copper manganese liners (eg, the first and second electrodes 135a and 135b in the semiconductor device 100 , and the conductive plugs 255 in the semiconductor device 200 ) surround the copper conductive structures (eg, The first pad 125a and the second pad 125b in the semiconductor device 100, and the barrier layer 245 in the semiconductor device 200) can reduce or avoid the formation of multiple voids in the conductive structures, thereby reducing contact resistance And improve the electromigration reliability of the conductive structure. Therefore, device performance can be improved.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor element has a first well region and a second well region, and is arranged in a semiconductor substrate. The semiconductor device also has a first dielectric layer disposed on the semiconductor substrate and covering the first well region and the second well region; and a gate structure disposed on the first dielectric layer and in the between the first well area and the second well area. The semiconductor device also has a conductive structure disposed on the first well region and separated from the first well region by a portion of the first dielectric layer. The conductive structure includes a barrier layer and a conductive plug, the conductive plug is disposed on the barrier layer, and the barrier layer includes copper manganese. The first well region, the conductive structure, and the portion of the first dielectric layer form an antifuse structure.

Another embodiment of the present disclosure provides a method for fabricating a semiconductor device. The preparation method includes forming a first well region and a second well region in a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate and covering the first well region and the second well region; forming a a gate structure on the first dielectric layer and between the first well region and the second well region; and forming a conductive structure on the first well region and through a portion of the first dielectric layer Separated from the first well region, wherein the conductive structure has a barrier layer and a conductive plug, the conductive plug is disposed on the barrier layer, and the barrier layer comprises copper manganese, wherein the first well region, The conductive structure and the portion of the first dielectric layer form an antifuse structure.

Some embodiments provided by the present disclosure have several advantageous features. By forming a copper-manganese liner around the conductive structure, the formation of voids in the conductive structure can be reduced or avoided, thereby reducing contact resistance and improving the electromigration reliability of the conductive structure. Therefore, device performance can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the scope of the claims. example For example, many of the above-described processes may be implemented in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, processes, machines, manufactures, processes, machines, manufacturing, and A composition of matter, means, method, or step. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included within the scope of the claims of this application.

200: Semiconductor Components

201: Semiconductor substrates

203: Insulation structure

205: Deep Well District

207: First Dielectric Layer

207': part

209: Gate Dielectric Layer

211: gate electrode layer

213: Gate structure

215: Gate spacer

217: The first well area

219: The second well area

221: Second Dielectric Layer

245: Barrier Layer

255: Conductive plug

257: Conductive Structure

283: Gate conductive plug

291: Third Dielectric Layer

293: Conductive layer

295: Conductive layer

300: Antifuse structure

Claims (15)

A semiconductor device, comprising: a first well region and a second well region, arranged in a semiconductor substrate; a first dielectric layer, arranged on the semiconductor substrate and covering the first well region and the second well region region; a gate structure disposed on the first dielectric layer and between the first well region and the second well region, wherein the gate structure includes a gate dielectric layer and a gate electrode layer, the gate dielectric layer is disposed on the first dielectric layer, the gate electrode layer is disposed on the gate dielectric layer; and a conductive structure is disposed on the first well region, and is formed by A portion of the first dielectric layer is separated from the first well region, wherein the conductive structure includes a barrier layer and a conductive plug, the conductive plug is disposed on the barrier layer, and the barrier layer includes copper manganese; wherein the first well region, the conductive structure and the portion of the first dielectric layer form an antifuse structure. The semiconductor device of claim 1, wherein the conductive plug of the conductive structure comprises copper. The semiconductor device of claim 1, wherein the barrier layer covers a lower surface and each sidewall of the conductive plug. The semiconductor device according to claim 1, further comprising a gate conductive plug disposed on the gate On the pole structure, the conductive plug and the gate conductive plug of the conductive structure comprise different materials. The semiconductor device according to claim 4, further comprising a second dielectric layer disposed on the first dielectric layer, wherein the gate structure, the conductive structure and the gate conductive plug are disposed on the second dielectric layer In the electrical layer, and wherein the first dielectric layer and the second dielectric layer comprise different materials. The semiconductor device of claim 1, further comprising a deep well region disposed in the semiconductor substrate, wherein the first well region and the second well region are disposed in the deep well region. The semiconductor device of claim 6, wherein the first well region and the second well region have a first conductivity type, and the deep well region has a second conductivity type, the second conductivity type and the first conductivity type Type is the opposite. A preparation method of a semiconductor element, comprising: forming a first well region and a second well region in a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate and covering the first well region and the second well region well region; forming a gate structure on the first dielectric layer and between the first well region and the second well region; and forming a conductive structure on the first well region and through the first well region A portion of the dielectric layer is separated from the first well region, wherein the conductive structure has a barrier layer and a conductive plug, the conductive plug is disposed on the barrier layer, and the barrier layer includes copper manganese; wherein the first well region, the conductive structure, and the portion of the first dielectric layer form an antifuse structure; and wherein the gate structure is formed on the first dielectric layer and between the first well region and the first dielectric layer. Between the second well regions includes: sequentially forming a gate dielectric material and a gate electrode material on the first dielectric layer; using a patterned mask as an etching mask on the gate dielectric An etching process is performed on the electrical material and the gate electrode material to form a gate dielectric layer and a gate electrode layer; and the patterned mask is removed. The manufacturing method of a semiconductor device as claimed in claim 8, wherein the conductive plug of the conductive structure comprises copper. The manufacturing method of a semiconductor device as claimed in claim 8, wherein the barrier layer covers a lower surface and each sidewall of the conductive plug. The method for fabricating a semiconductor device according to claim 8, further comprising forming a gate conductive plug on the gate structure, wherein the conductive plug and the gate conductive plug of the conductive structure comprise different materials. The method for manufacturing a semiconductor device according to claim 11, further comprising forming a second dielectric layer on the first dielectric layer, wherein the gate structure, the conductive structure and the gate conductive plug is disposed in the second dielectric layer, and wherein the first dielectric layer and the second dielectric layer comprise different materials. The method for fabricating a semiconductor device according to claim 8, further comprising forming a deep well region in the semiconductor substrate, wherein the first well region and the second well region are disposed in the deep well region. The method for fabricating a semiconductor device according to claim 13, wherein the first well region and the second well region have a first conductivity type, and the deep well region has a second conductivity type, the second conductivity type and the The first conductivity type is the opposite. The method for fabricating a semiconductor device according to claim 12, further comprising: forming a third dielectric layer on the second dielectric layer; and forming a plurality of conductive layers in the third dielectric layer.

Images