JP2004228146A - Semiconductor device and electrode forming method thereof - Google Patents

Abstract

An object of the present invention is to suppress the occurrence of aluminum spikes before writing while stabilizing the initial yield while keeping the writing voltage of an anti-fuse element within an allowable range.
An insulating film is formed on a semiconductor substrate having a first semiconductor region constituting a first element which can be programmed by invasion of a fluid metal into a junction, and a part of the insulating film is selectively formed. A first contact hole exposing the first semiconductor region is opened at the bottom thereof, and the first contact hole including the oxide layer formed by irradiating first plasma and then exposing to an oxidizing atmosphere is formed. Without removing the reaction suppression layer, a film containing the fluid metal as a main component is deposited in the first contact hole, and connected to the first semiconductor region via the first reaction suppression layer. The problem is solved by forming a first electrode made of the fluid metal to be formed.
[Selection diagram] Fig. 1

Description

【００３８】
表１において「Ａｒエッチ無」と示したのは、コンタクトホール底部の反応抑制層を残したまま、１ｗｔ％のＳｉを含むＡｌＳｉ膜、もしくは０．５ｗｔ％のＣｕを含むＡｌＣｕ膜を堆積して電極を形成した場合である。「Ａｒエッチ有」と示したのは、比較のために、Ａｒイオンによるエッチングを行い、コンタクトホール底面の反応抑制層を除去してから電極を形成した場合である。この場合には、酸化物層およびダメージ層の両方を含んだ反応抑制層全体を除去することを意図して、ＳｉＯ_２ 換算で５ｎｍ以上のエッチングを行った。
電極をＡｌＳｉ膜で形成した場合には、Ａｒエッチングを行った場合でも行わない場合でも、１００％の初期歩留りが得られる。これは、ＡｌＳｉ膜中に、製造工程中の熱処理（最高４００℃程度）における固溶度を超えるＳｉが含まれているため、反応抑制層が存在しない場合であってもＡｌスパイクが発生したためであると理解できる。一方、ＡｌＣｕ膜で電極を形成した場合には、Ａｒエッチングを行うと初期歩留りが０％となる。これは、Ａｒエッチングによって反応抑制層が除去された半導体領域の表面に、Ｓｉを含まないＡｌＣｕ膜が直接接触するため、製造工程中に、Ａｌスパイクが高い密度で発生したためであると理解できる。これに対して、Ａｒエッチングを行わない場合には、９６％と、１００％に近い初期歩留りが得られ、反応抑制層の存在によってＡｌスパイク発生が効果的に抑制されたことがわかる。
【００３９】
書き込みに必要な書き込み電圧は、Ａｒエッチングを行ってＡｌＳｉ膜からなる電極を形成した場合は平均１１．５Ｖであるのに対して、Ａｒエッチングを行わない場合には、電極材料によらず、平均１６Ｖと高くなる。反応抑制層の存在によって流動性金属の半導体領域内への侵入が抑制されたためであると解釈される。しかし、書き込み電圧上昇の程度は、大きくなく、実用的に対応できる範囲である。
このように、反応抑制層を意識的に残留させることによって、ＡｌＣｕのようなＳｉを含まないＡｌ膜を使用して電極を形成した場合であっても、実用的な書込電圧の範囲内で、初期歩留りを大幅に高められることがわかった。なお、表１に示した例では処理歩留りは１００％に達していないが、これは、電極面積が６４００μｍ２と極めて大きいためであり、以下に述べるように、電極の面積やレイアウトの最適化によってさらに高い初期歩留りが得られることが分かった。
【００４０】
表２に、Ｃｘ＝Ｃｙ＝１．４μｍのコンタクトホールに対して、さまざまな面積のＡｌＣｕ膜による電極を形成した場合の初期歩留りを示す。ここでは、電極面積の影響を明確にするため、１ないし２ｎｍのＡｒエッチングを行った場合の結果を示す。このエッチング量では、反応抑制層は、薄くなるが完全には除去されない。
【表２】

【００４１】
表２から、電極面積が小さくなるほど初期歩留りが上昇し、１８μｍ^２ 、すなわち、Ｃｘ＝Ｃｙ＝１．４μｍのコンタクトホール面積に対して約９倍の電極面積の場合には、１００％に達することがわかる。これは、コンタクトホールの寸法を一定に保った状態で電極面積が小さくすることによって、コンタクトホール底部において接触する半導体領域の面積に対する電極面積の比が小さくなり、半導体領域からのＳｉ吸い上げ量が減少し、その結果、Ａｌスパイクの発生が抑制されたものと理解できる。この結果から、アンチヒューズを構成する半導体領域に接続するコンタクトホールの面積に対する電極面積の比を所定の値以下、表２の例では約９倍以下に保てば、高い初期歩留りを得ることができると考えられる。
【００４２】
しかし、実際の半導体集積回路において、アンチヒューズ素子に接続される電極の面積を所定値以下に保つことは容易ではない。アンチヒューズ素子のコンタクトホールに接続される電極は、通常、アンチヒューズ素子を半導体集積回路上の他の素子に接続する配線としても使用されるため、接続対象の素子の位置によって電極面積が変化してしまうからである。
電極面積を所定値以下に保つためには、電極１４、１６を、アンチヒューズ素子の半導体領域に接続するための電極としてのみ使用し、他の素子との接続のためには別の配線を利用することが有効である。このためには、具体的には図３（ａ）の平面図および図３（ｂ）の断面図に示したように、第１の配線層に形成した、コンタクトホール１８、２０底部でソース、ドレイン領域１５、１７に接続する電極１４、１６上に、第２の層間絶縁膜４０を形成し、この層間絶縁膜４０の、コンタクトホール１８、２０の近傍に位置に、第１層の配線と第２層の配線とを接続する層間接続孔４８、５０を設け、この層間接続孔４８、５０を埋め込むプラグ４５、４７によって、第１層の配線１４、１６を第２層の配線５４、５６に接続し、他の素子との接続は、この第２層の配線５４、５６を介してのみ行う。すなわち、電極１４、１６は、コンタクトホール１８、２０と、プラグ４５、４７との間の接続のためにのみに使用し、他の素子への接続のためには使用しない。プラグ４５、４７を、プラグ２５と同様に、バリアメタル膜（拡散防止膜）４１、４３およびタングステン膜４２、４４で形成することにより、コンタクトホール１８、２０の底部で接続されたソース、ドレイン領域１５、１７から吸い上げたＳｉの拡散がバリアメタル膜４１、４３によって遮断される。これによって、ソース、ドレイン領域１５、１７と反応してアルミスパイク発生の原因となるＡｌＣｕ電極の面積を、第１配線層に形成された１４、１６の部分のみに限定することができる。この結果、アルミスパイク発生に影響を与える電極面積とコンタクトホール面積との比を、他の素子との接続のために使用する配線部分の長さが変化しても、確実に、所定値以下に維持することができる。
【００４３】
より具体的には、図３に示したコンタクトホール１８、２０を有するアンチヒューズ素子と、このコンタクトホール１８、２０の面積に対して所定の面積を有する第１層の配線１４、１６と、コンタクトホール１８、２０の近傍に配置された、プラグ４５、４７とを、１つの単位（セル）として用意し、アンチヒューズ素子を利用する半導体装置を設計する際には、これを単位として利用する。これにより、設計する半導体装置の構成に依存せず、アンチヒューズ素子に接続する電極の面積とコンタクトホールの面積との比を一定値に維持することができる。コンタクトホール１８、２０のそれぞれと、対応するプラグ４５、４７との間の距離に特に限定はないが、使用する製造プロセスが許容する範囲で、必要以上に大きなマージンを設けずに、なるべくその間の距離を短くして、第１配線層の電極１４、１６の寸法を小さくすることが好ましい。
【００４４】
層間接続孔４８、５０の寸法によっては、タングステン膜４２、４４を用いてプラグを形成することが不要な場合もある。この場合には、シリコンの拡散を防止するためのバリアメタル膜４１、４３のみを形成し、層間接続孔４８、５０内から第２の層間絶縁膜４０上にかけて、例えばＡｌＣｕ膜を堆積し、パターニングすることによって、第２層の配線５４、５６を形成してもよい。この場合でもバリアメタル膜（拡散防止膜）４１、４３によってソース、ドレイン領域１５、１７から吸い上げたシリコンが拡散する範囲が第１配線層の電極１４、１６の範囲に制限されるため、シリコンスパイクの発生が抑制される。
また、何らかの理由によってコンタクトホールの面積に対する電極の面積の比が大きくなる場合に、電極の面積を実質的に小さくしてアルミスパイクの発生を防止する方法として、素子分離領域上にダミーの多結晶シリコン膜を配置し、アンチヒューズ素子の半導体領域に接続される電極に接続する方法がある。ＡｌＣｕ等のＳｉを含まない膜で配線を形成した場合でも、接続したダミーの多結晶シリコン膜からシリコンが供給されるため、拡散領域１２ａ、１２ｂからのシリコンの吸い上げ量が抑制され、アルミスパイク発生が抑制される。
【００４５】
この場合、図４（ａ）の平面図および図４（ｂ）の断面図に示されたように、例えばゲート電極１３形成と同時に、素子分離領域１９上に多結晶シリコン膜５１、５２を形成し、アンチヒューズ素子用のコンタクトホール１８、２０の開口と同時に、これらの多結晶シリコン膜に接続するためのコンタクトホール５８、６０を開口する。そして、コンタクトホール１８、２０内へのＡｌＣｕ膜堆積と同時に、コンタクトホール５８、６０内にもＡｌＣｕ膜を堆積し、パターニングを行って、電極１４、１６を、アンチヒューズ素子用のコンタクトホール１８、２０のそれぞれから対応する多結晶シリコン膜用のコンタクトホール５８、６０にかけて配置され、その間を接続するように形成する。この場合、多結晶シリコン膜用のコンタクトホール５８、６０の底部にも、アンチヒューズ素子用のコンタクトホール１８、２０底部の反応抑制層３２と同様の、反応抑制層６２が残留する。
【００４６】
この時、多結晶シリコン膜５１、５２を接続することによって実効的に電極面積を小さくする効果を有効に利用するためには、図４（ａ）の平面図に例示されたように、アンチヒューズに接続するコンタクトホール１８、２０の個数に比較して、多結晶シリコン膜に接続するコンタクトホール５８、６０の個数を多くすることが好ましい。具体的には、コンタクトホール１８、２０の寸法とコンタクトホール５８、６０の寸法とが同一である場合、個数の比を少なくとも３倍もしくはそれ以上に、もしくは、さらに好ましくは１０倍程度もしくはそれ以上にする。コンタクトホール１８、２０の寸法とコンタクトホール５８、６０の寸法とが異なる場合には、コンタクトホールの合計面積の比が、上記のような値になるようにすればよい。
【００４７】
アンチヒューズ素子用のコンタクトホール１８、２０のそれぞれと、対応する多結晶シリコン膜用のコンタクトホール５８、６０との間の距離に、特に限定はない。しかし、使用する製造プロセスが許容する範囲で、必要以上に大きなマージンを設けずに、なるべくその間の距離を短くすることにより、多結晶シリコン膜からのＳｉ供給の効果を効果的に生かして、アンチヒューズ素子のコンタクトホール面積に対する電極面積を実効的に減少させることができる。
ダミーとして使用する多結晶シリコン膜は、１層目の多結晶シリコン層を利用して、ゲート電極と同時に形成してもいいし、第２層の多結晶シリコン層を利用して、容量素子の上部電極や高抵抗素子と同時に形成してもよい。
さらに、他の素子と分離された半導体（Ｓｉ）基板表面領域をダミーとして使用することも可能である。例えば、ソースをＧＮＤ電位に固定したＮチャンネルＭＯＳ型トランジスタをアンチヒューズ素子として使用する場合、ソース領域は、Ｓｉ基板表面のＰウエル領域内に形成したＰ^＋ 拡散領域に接続し、このＰウエルにＧＮＤ電位を供給する。ドレイン領域には、Ｎウエル領域内に形成したＮ^＋ 拡散領域に接続する。書込時には、このＮウエルにも書込のための高電圧を印加する。一方読出時には、このＮウエルには電圧を印加せず、ドレインと同電位にする。
【００４８】
以上詳細に説明したように、本実施形態によれば、コンタクト接続部において、ＡｌＣｕ配線とＳｉ基板の間に反応抑制層を残すことにより、また、さらに、ヒューズ素子用の電極（寸法／レイアウト）を最適化することにより、書き込み電圧を許容範囲内に保ちながら、書き込み前のアルミスパイクの発生を抑制し、初期歩留りを安定化させることが可能となった。
【００４９】
以上、本発明の半導体装置及びその電極形成方法について、詳細に説明したが、本発明は、以上の実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において、各種の改良や変更を行ってもよいのはもちろんである。
例えば、プログラム可能な素子としては、例示したＮチャンネルＭＯＳトランジスタ型アンチヒューズ素子だけではなく、ＰチャンネルＭＯＳトランジスタ型や、ＰＮ接合ダイオード（ツェナーザップダイオード）型等、様々なものが使用できる。前述のように、ＮチャンネルＭＯＳトランジスタ型の場合には、書き込み時に負となるソース電極の流動性金属が、ソース電極が接続される半導体領域であるソース拡散領域から、チャンネル領域を通過し、ドレイン−チャンネル間のＰＮ接合部に侵入して、接合を破壊することによって書き込みが行われる。ＰＮ接合ダイオードにおいては、例えば逆方向電圧印加で書き込みを行う場合、カソード電極に対して負の電圧が印加されるアノード電極の流動性金属が、アノード電極が接続される半導体領域であるＰ^＋ 拡散領域から、このＰ^＋ 拡散領域と、それに隣接して設けられたＮ拡散領域との間、もしくは、Ｐ^＋ 拡散領域に隣接して設けられたＰ拡散領域と、さらにそれに隣接して設けられたＮ^＋ 拡散領域との間に形成されるＰＮ接合部に侵入して、接合を破壊することによって書き込みが行われる。
【００５０】
破壊される接合部は、例示したＭＯＳトランジスタ型アンチヒューズ素子では、半導体基板内に形成される。すなわち、半導体基板自体の表面領域内に接合部が存在する。ＰＮ接合型でも、同様に、半導体基板内に接合部を設けることが可能である。しかし例えば、半導体基板上に、その表面に形成された素子分離用フィールド絶縁膜を介して、形成した多結晶シリコン膜内に、アンチヒューズ素子として使用するＭＯＳトランジスタやＰＮ接合ダイオードを形成することも可能である。ただし、プラズマ照射後に酸化性雰囲気にさらすことによって、安定した膜質の反応抑制層を形成し、書き込み電圧を許容範囲内に保ちながら初期歩留りを安定させるためには、少なくとも書き込み時に負側になる電極が接続される半導体領域は、半導体基板自体の表面領域に形成されることが好ましい。
【００５１】
アンチヒューズ素子に接続する電極は、流動性金属がアルミニウムである場合に限っても、例示したＡｌＣｕの他にも、純Ａｌ、およびその他様々なＡｌを主成分とするＡｌ合金膜を利用して形成することができる。ただし、反応抑制層によってアルミスパイクの発生を抑制して初期歩留りを安定させる効果は、反応抑制層が無い場合にはアルミスパイクが発生する可能性の高い、純ＡｌまたはＳｉを含まないＡｌ合金膜を利用した場合に顕著に発揮される。もしくは、Ｓｉを含むとしても、電極形成後の製造工程において行われる熱処理温度における固溶度に比較して含有量が小さく、反応抑制層が無い場合にはアルミスパイクが発生する可能性が高いという意味で、実質的にＳｉを含まないＡｌ合金膜を利用する場合にも、反応抑制層の効果が顕著に発揮される。
アンチヒューズ素子の接合部に侵入させて書き込みを行う流動性金属としては、アルミニウムの他に、例えば特許文献２に記載されたように、チタン等のシリサイドを形成する金属や、金、銅、銀などが使用可能である。
【００５２】
【発明の効果】
以上、説明した通り、本発明によれば、アンチヒューズ素子の書き込み電圧を許容範囲内に保ちながら、書き込み前におけるアルミスパイクの発生を抑制し、初期歩留りの安定化を図ることが可能となる。
【図面の簡単な説明】
【図１】（ａ）〜（ｈ）は、本発明の半導体装置の電極形成方法による半導体装置の製造過程を段階的に示す模式図である。
【図２】本実施形態に係る半導体装置の概略を示す平面図である。
【図３】（ａ）及び（ｂ）は、それぞれ本発明の他の実施形態に係る半導体装置の概略を示す平面図及び断面図である。
【図４】（ａ）及び（ｂ）は、それぞれ本発明のさらに他の実施形態に係る半導体装置の概略を示す平面図及び断面図である。
【図５】従来のＭＯＳトランジスタ型アンチヒューズの一例の概略を示す平面図である。
【符号の説明】
１０ シリコン基板
１１ａ Ｎウエル
１１ｂ Ｐウエル
１２ａ Ｐ^＋ 拡散
１２ｂ Ｎ^＋ 拡散
１３ ゲート電極
１４、１６ 電極
１８、２０、５８、６０ コンタクトホール
１９ 素子分離領域
１６、４０ 層間絶縁膜
２１、２８ フォトレジストパターン
２０ （第２の）コンタクトホール
２０ａ （第２の）コンタクトホールの表面
２２ （第２のコンタクトホール底部の）反応抑制層
２４、４１、４３ バリアメタル膜
２５、４５、４７ プラグ
２６、４２、４４ タングステン膜
３０ ヒューズ用コンタクトホール（第１のコンタクトホール）
３０ａ （第１の）コンタクトホールの表面
３２ （第１のコンタクトホール底部の）反応抑制層
３４ ＡｌＣｕ膜
４８、５０ 層間接続孔
５１、５２ 多結晶シリコン膜
５４、５６ 第２層の配線
６２ 反応抑制層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and an electrode forming method thereof, and more particularly to a semiconductor device having an electrically programmable so-called antifuse and an electrode forming method thereof.
[0002]
[Prior art]
2. Description of the Related Art In recent years, in order to reduce the number of components in electronic devices, semiconductor devices such as LSIs whose characteristics can be adjusted after assembly have been required. As a means for responding to this demand, there is known a technology that enables adjustment of an LSI by using a programmable element such as an antifuse integrated in the LSI. An antifuse is a switch element that generally exhibits an electrically non-conductive state in an initial state, and can be irreversibly changed from a non-conductive state to a conductive state using an electrical method.
[0003]
FIG. 5 is a plan view showing an example of such a MOS transistor type antifuse as a kind of antifuse.
On a surface of the semiconductor substrate 100, an active region 110 surrounded by the element isolation region 102 is formed. A gate electrode 130 extending in the vertical direction in the figure is provided on the active region via a gate insulating film (not shown). A portion of the surface of the active region covered with the gate electrode 130 is formed as a channel region 140. Become. On the other hand, impurities are added at a high concentration on both sides of the channel region 140 on the left and right sides of the figure, and diffusion regions forming the source region 112 and the drain region 114 are formed. An interlayer insulating film (not shown) covering the entire active region 110 and gate electrode 130 is formed, and contact holes 120 and 122 reaching source region 112 and drain region 114 are formed in the interlayer insulating film. Then, through the contact holes 120 and 122, a source electrode and a drain electrode (not shown) which are connected to the source region 112 and the drain region 114, for example, mainly containing aluminum are formed. Similarly, an electrode (not shown) is formed for the gate electrode.
[0004]
When the resistance between the drain and the source is measured in a state where the gate electrode is connected to the source electrode, the MOS transistor type anti-fuse element shows a resistance value of GΩ level in an initial state and is in a non-conductive state. However, when a high voltage is applied between the drain and the source while an appropriate voltage is applied to the gate, aluminum invades the active region from the negative electrode, penetrates the channel region, and forms a gap between the drain and the source. A conductive filament that short-circuits is formed. As a result, the resistance between the drain and the source is reduced to 100Ω or less, and the device is brought into a conductive state. Thus, it is possible to write data into the antifuse and perform programming.
[0005]
Conventionally, many methods for manufacturing such a programmable semiconductor device have been proposed (for example, see Patent Documents 1 to 3).
Patent Document 1 discloses a method in which a tungsten plug is formed in a contact hole of a normal element and an anode electrode made of aluminum or an aluminum alloy is formed in a contact hole of a programmable element. .
Further, in Patent Document 2, a programming voltage having a voltage value equal to or higher than a drain-source breakdown voltage of a field-effect transistor is applied between a drain region and a source region of a MOSFET to form an electrode material (titanium silicide). The method of forming a conductive filament according to (1) is disclosed.
[0006]
Further, Patent Document 3 discloses that a very thin insulating film is formed on a surface of an exposed silicon substrate by a CVD method with respect to a contact hole for a normal element, whereby a short circuit between a wiring layer and a semiconductor substrate due to aluminum diffusion, A device that prevents an increase in contact resistance due to a natural oxide film is disclosed.
[0007]
[Patent Document 1]
JP 2000-340750 A
[Patent Document 2]
Japanese Patent No. 3204454
[Patent Document 3]
JP-A-61-285762
[0008]
[Problems to be solved by the invention]
Conventionally, AlSi containing about 1 wt% (wt%) of Si has been used as an electrode material for such an antifuse. In this material, an amount of Si exceeding a solid solubility that is the maximum amount that can be dissolved in Al at a temperature (maximum 400 ° C.) of a thermal process performed after electrode formation in a semiconductor device manufacturing process. Has been added. For this reason, at the interface connected to the diffusion region on the surface of the semiconductor substrate that constitutes the source region and the drain region, Si is not absorbed from the diffusion region. Therefore, there is no Al spike generated due to the intrusion of Al from the electrode into the hole generated by the absorption of Si. This material has been used as a wiring material when the design rule of the LSI is 1.0 μm or more.
On the other hand, when the design rule is 0.8 μm or less, it is necessary to use an aluminum alloy (AlCu) containing, for example, 0.5 wt% of Cu in order to secure the reliability of the metal wiring (electromigration resistance and the like). .
[0009]
However, when an aluminum alloy (AlCu) is used, when AlCu comes into direct contact with the silicon substrate, the aluminum is moved from the contact surface to the depth of the silicon substrate from the contact surface before writing due to the solid solubility of aluminum and silicon. Aluminum spikes penetrating in the direction are likely to occur. For this reason, there is a problem that the initial yield (before writing) of the antifuse is reduced.
Here, the initial yield means that the resistance value between the drain and source before destruction is 1 GΩ or more and the breakdown voltage between drain and source B _vds Is defined as a non-defective product having a voltage of 6 V or more, as a percentage of the number of non-defective products with respect to the number of measurements.
[0010]
The present invention has been made in view of the above-mentioned conventional problems, and a semiconductor capable of suppressing the occurrence of aluminum spikes before writing a fuse and stabilizing an initial yield while maintaining a write voltage within an allowable range. An object is to provide an apparatus and a method for forming an electrode thereof.
[0011]
[Means for Solving the Problems]
In order to solve the above problem, a first aspect of the present invention is a method for forming an electrode of a semiconductor device, the method comprising forming an electrode connected to a programmable first element by intrusion of a fluid metal into a joint. Forming an insulating film on a semiconductor substrate having a first semiconductor region constituting the first element, selectively removing a part of the insulating film, and forming the first semiconductor region on a bottom thereof. A first contact hole that exposes the first semiconductor region is exposed to a first plasma, and then exposed to an oxidizing atmosphere, thereby forming a first reaction including an oxide layer. Forming a film containing the fluid metal as a main component in the first contact hole without removing the first reaction suppressing layer; and forming the first reaction suppressing layer in the first contact hole without removing the first reaction suppressing layer. Through the first semiconductor Providing an electrode forming method of a semiconductor device, characterized in that it comprises a step of forming a first electrode made of a film composed mainly of the flowable metal which is connected to the band, the.
[0012]
Similarly, in order to solve the above-mentioned problem, a second aspect of the present invention relates to a first element which can be programmed by intrusion of a flowable metal into a joint and a second element which is programmable by the other elements. A method of forming an electrode of a semiconductor device for forming an electrode connected to a semiconductor device, comprising: a first semiconductor region forming the first element; and a second semiconductor region forming the second element. Forming an insulating film thereon, selectively removing a first region of the insulating film, opening a first contact hole exposing the first semiconductor region at the bottom thereof, and exposing the exposed first contact region. Forming a first reaction suppression layer including an oxide layer by irradiating the surface of the first semiconductor region with a first plasma and then exposing the first reaction suppression layer to an oxidizing atmosphere; Without removing the first component A film mainly composed of the fluid metal is deposited in the via hole, and the film composed mainly of the fluid metal is connected to the first semiconductor region via the first reaction suppression layer. Forming a first electrode, selectively removing a second region of the insulating film, opening a second contact hole exposing the second semiconductor region at the bottom thereof, and Irradiating the surface of the second semiconductor region with the second plasma and then exposing the surface to an oxidizing atmosphere to form a second reaction suppression layer including an oxide layer; and at least the second reaction suppression layer Removing the oxide layer, and subsequently forming a plug made of a high melting point metal in the second contact hole.
[0013]
Further, the formation of the plug in the second contact hole is performed before the opening of the first contact hole, and the entire surface of the insulating film in which the first and second contact holes are opened. Depositing a film containing the fluid metal as a main component, and simultaneously forming the first electrode, forming a second electrode connected to the second semiconductor region via the plug. Is preferred.
[0014]
Further, it is preferable that the irradiation of the first plasma be performed at the time of over-etching of the plasma etching for opening the first contact hole.
[0015]
In the method for forming an electrode of a semiconductor device, the film containing the fluid metal as a main component is preferably an aluminum or aluminum alloy film containing substantially no silicon.
[0016]
Similarly, in order to solve the above-described problem, a third aspect of the present invention provides a method in which a first element which is programmable by intrusion of a fluid metal into a joint and a second element other than the programmable element are the same. A first contact hole formed on the semiconductor substrate and exposing a first semiconductor region constituting the first element at a bottom thereof; and a bottom portion thereof. An insulating film having a second contact hole exposing a second semiconductor region constituting the second element; and a film containing a fluid metal as a main component formed in the first contact hole. And a plug made of a refractory metal embedded in the second contact hole. The surface of the first semiconductor region exposed at the bottom of the first contact hole is provided on the surface of the first semiconductor region. , At least the oxide layer A second semiconductor exposed at a bottom of the second contact hole, wherein the first electrode is non-ohmically connected to the first semiconductor region via the reaction suppression layer. There is provided a semiconductor device, wherein the reaction suppressing layer is not substantially present on the surface of the region, and the plug is ohmically connected to the second semiconductor region.
[0017]
Similarly, in order to solve the above problem, a fourth aspect of the present invention includes a first element which is programmable by intrusion of a flowable metal into a joint, and a second element other than the first element. A semiconductor device in which a plurality of other elements are formed on the same semiconductor substrate, the first device being formed on the semiconductor substrate and exposing a first semiconductor region forming the first element at a bottom thereof. Forming an insulating film having a contact hole, a second contact hole exposing a second semiconductor region forming the second element at a bottom thereof, and the inside of the first contact hole and over the insulating film. A first electrode made of a film containing a flowable metal as a main component, a plug made of a high melting point metal embedded in the second contact hole, and an interlayer insulating film on the first electrode. Upper layer arrangement formed A reaction suppression layer including at least an oxide layer is formed on the surface of the first semiconductor region exposed at the bottom of the first contact hole, and the first electrode forms the reaction suppression layer. And a reaction suppression layer is not substantially present on the surface of the second semiconductor region exposed at the bottom of the second contact hole, and the plug is connected to the first semiconductor region. The first electrode is connected directly to the upper wiring via a diffusion prevention film for preventing diffusion of silicon in the vicinity of the first contact hole. A semiconductor device is provided which is connected to any of the other elements only via the diffusion barrier film and the upper wiring.
[0018]
Similarly, in order to solve the above problem, a fifth aspect of the present invention provides a first element which can be programmed by invasion of a flowable metal into a junction formed in a semiconductor substrate, A second element formed on the semiconductor substrate, the second element being formed on the semiconductor substrate, and exposing a first semiconductor region constituting the first element at a bottom thereof; A contact hole, a second contact hole at the bottom exposing a second semiconductor region constituting the second element, and a polycrystalline silicon film formed at the bottom on the element isolation region on the surface of the semiconductor substrate An insulating film having a third contact hole exposing the first contact hole; and a first electrode formed from the inside of the first contact hole to the inside of the third contact hole, the film being composed mainly of a fluid metal. And a plug made of a refractory metal embedded in the second contact hole, wherein at least an oxide is formed on the surface of the first semiconductor region exposed at the bottom of the first contact hole. A first electrode connected to the first semiconductor region via the reaction suppression layer, and the second electrode exposed at the bottom of the second contact hole. There is provided a semiconductor device, wherein a reaction suppression layer is not substantially present on a surface of a semiconductor region, and the plug is directly connected to the second semiconductor region.
[0019]
In the semiconductor device, it is preferable that the film containing the fluid metal as a main component is an aluminum or aluminum alloy film containing substantially no silicon.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a semiconductor device and a method of forming an electrode thereof according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.
[0021]
FIG. 1 shows a step-by-step process of manufacturing a semiconductor device according to the method for forming an electrode of a semiconductor device of the present invention.
Here, a case will be described in which an antifuse is added to a laminated metal process with a design rule of 0.5 μm or less. The process up to the formation of the normal contact portion other than the antifuse is the same as the conventional process.
[0022]
In FIG. 1A, a plurality of active regions are formed on a surface of a silicon substrate 10 and are separated from each other by an isolation region 19 in which a field oxide film for element isolation is formed. The left part of the drawing is formed in the N well 11a, and the right part is formed in the P well 11b. The active region on the surface of the N well 11a has P ⁺ A diffusion region 12a is formed in the active region on the surface of the P well 11b. ⁺ A diffusion region 12b is formed. Here, N in the P well 11b ⁺ The diffusion region 12b is representative of a semiconductor region constituting an anti-fuse element (programmable element). Specifically, for example, a MOS transistor type anti-fuse element corresponds to a source region or a drain region. On the other hand, P in the N well 11a ⁺ The diffusion region 12a is representative of a semiconductor region constituting a normal (not programmable) element. For example, these are the source and drain regions of a normal MOS transistor. ⁺ N with type ⁺ A mold diffusion region is formed. Then, an interlayer insulating film 16 is formed thereon. Thereafter, the surface of the interlayer insulating film 16 is flattened by, for example, a CMP (Chemical Mechanical Polish) method or the like, and a photoresist pattern 21 for forming a contact hole is formed thereon.
[0023]
Next, FIG. 1B shows a state in which a contact hole (second contact hole) 20 is formed in the silicon oxide film 16 by plasma etching (second plasma) using the photoresist pattern 21 as a mask. Show. This plasma etching is performed using, for example, a parallel plate type RIE (Reactive Ion Etching) ₃ And C ₄ F ₈ And the like, using a fluorocarbon-based gas. This etching is performed under anisotropic conditions. The contact hole 20 is a contact hole for an ordinary (not corresponding to a programmable element) transistor in which a film mainly composed of a fluid metal (for example, aluminum Al) is not deposited. That is, a plug made of a high melting point metal (tungsten W) is formed later in the contact hole 20.
[0024]
At this time, the P on the surface of the semiconductor substrate 10 exposed by opening the contact hole 20 by plasma etching. ⁺ On the surface 20a of the diffusion region 12a (second semiconductor region), a damaged layer made of, for example, an SiC layer (carbon-containing layer) having a thickness of 3 to 5 nm is formed by receiving plasma irradiation during over-etching. Then, an oxide layer made of a natural oxide film having a thickness of, for example, about 3 nm is formed by being further exposed to an oxidizing atmosphere, and the reaction suppression layer (the second reaction suppression layer including the oxide layer) 22 is formed by these. It is formed.
The exposure to the oxidizing atmosphere is usually performed when the substrate is taken out into the air after the plasma etching for opening the contact hole. Further, it is also performed when performing oxygen plasma treatment or cleaning for removing the resist as described below.
[0025]
Next, as shown in FIG. ₄ / O ₂ Light etching is performed by plasma using a system gas to remove the damaged layer 22 existing at the bottom of the contact hole 20. The reason why the damaged layer 22 is removed in this way is to ensure ohmic contact of the contact. Next, the resist pattern 21 is removed using oxygen plasma, and further, cleaning is performed using a mixed solution of sulfuric acid and hydrogen peroxide. By properly setting the conditions of the light etching, the damaged layer is etched and almost completely removed. On the other hand, the oxide layer has a CF ₄ Etching is performed by the action of CF-based ions generated from the gas. ₂ It is oxidized again by oxygen radicals generated from the gas. Furthermore, the oxide layer is oxidized when it is taken out into the air after light etching or when the resist pattern is removed, so that the oxide layer remains after light etching. Therefore, the remaining oxide layer is further removed using, for example, buffered hydrofluoric acid (BHF) or the like, and the exposed P layer at the bottom of the contact hole 20 is removed. ⁺ A state is obtained in which the reaction suppression layer does not substantially exist on the surface of the diffusion region 12a.
Next, as shown in FIG. 1D, first, for example, a titanium nitride (TiN) -based barrier metal film 24 is formed by sputtering, and then a tungsten film 26, which is a refractory metal, is formed by chemical vapor deposition (CVD). It is formed by a method.
[0026]
Next, as shown in FIG. 1E, the tungsten film 26 and the barrier metal film 24 deposited on the silicon oxide film 16 are removed by the CMP method.
As a result, a plug 25 composed of a tungsten film 26, which is a high melting point metal, and a barrier metal film (diffusion preventing film) 24, which is buried in the second contact hole 20, is formed.
[0027]
Next, a fuse contact hole (first contact hole) is opened. This contact hole is for depositing a film mainly composed of a fluid metal such as Al and forming an electrode connected to the semiconductor region of the first programmable element.
As shown in FIG. 1F, a photoresist pattern 28 for forming a fuse contact hole is formed on the exposed interlayer insulating film 16.
[0028]
As shown in FIG. 1G, a fuse contact hole 30 is opened using the photoresist pattern 28 as a mask.
In this opening (contact hole 30), an AlCu film mainly composed of Al which is a flowable metal is directly deposited. Therefore, although not shown, round etching is performed by isotropic etching. Finish by anisotropic etching by RIE. Here, the isotropic etching means may be either radical etching or wet etching.
The same etching apparatus and conditions for anisotropic etching as those used for opening the second contact hole 20 can be used. After the anisotropic etching, when the semiconductor device is taken out to the atmosphere, the first semiconductor region N which is exposed at the bottom of the contact hole 30 and constitutes a programmable element is formed. ⁺ On the surface of the diffusion region 12b, a reaction suppression layer (first reaction suppression layer) 32 composed of a damaged layer and an oxide layer is formed as in the case of the second contact hole 20. Furthermore, an additional oxide layer is formed during the subsequent oxygen plasma treatment or cleaning.
[0029]
Subsequently, as in the case of forming the second contact hole 20, the resist pattern 28 is removed by oxygen plasma. However, in this case, light etching for removing the damaged layer is not performed. The cleaning after the removal of the resist pattern 28 is also performed using, for example, an amine-based organic solvent so as not to erode the plug 25 made of the tungsten film embedded in the second contact hole 20. Therefore, the reaction suppression layer 32 at the bottom of the first contact hole 30 remains without being removed.
[0030]
Next, as shown in FIG. 1H, an AlCu film 34 in which Al, which is a fluid metal, contains about 0.5 wt% of Cu is deposited by a sputtering method. Subsequently, a resist pattern (not shown) is formed, and the AlCu film is patterned by performing etching using the resist pattern as a mask, so that the first electrode 34b connected to the first semiconductor region 12b and the second semiconductor region 12a are formed. A second electrode 34a connected via a plug 25 composed of the tungsten film 26 and the barrier metal film 24 is formed.
As described above, in the case of the (second) contact hole 20, the plug 25 is formed after removing the reaction suppression layer 22 at the bottom of the contact hole 20 in order to ensure ohmic contact of the contact. In the case of the (first) contact hole 30, an electrode 34b made of an AlCu film was formed with the reaction suppression layer 32 remaining. Therefore, the electrode 34b is a semiconductor region that constitutes a programmable element through the reaction suppression layer 32, and is formed of N. ⁺ Connected to diffusion region 12b.
[0031]
That is, the present embodiment positively utilizes the reaction suppression layer formed at the time of opening the contact, which has been conventionally removed to secure ohmic contact.
As described later, even when the electrode 34b is formed by using the AlCu alloy film containing no Si by connecting to the semiconductor region via the reaction suppressing layer 32, the generation of Al spikes in the manufacturing process is prevented. It is possible to increase the initial yield of suppressed and programmable elements.
Thereafter, although not shown, a second interlayer insulating film is formed on the entire surface of the semiconductor substrate on which the wirings 34a and 34b are formed, and an interlayer connection hole is opened in the second interlayer insulating film. Form layer wiring. Further, if necessary, an interlayer insulating film, an interlayer connection hole, and a wiring for the third layer and thereafter are formed, and finally, a surface protection film is formed, and a pad hole is opened, thereby completing the semiconductor device manufacturing process.
[0032]
The manufacturing process according to the electrode forming method of the present embodiment is basically performed according to the above flow. In addition, about the part which abbreviate | omitted description, it is the same as that of the conventional method usually performed.
As described above, since the reaction suppression layer 22 was removed on the second contact hole 20 side, ohmic contact was made, whereas the reaction suppression layer 32 was left on the first contact hole 30 side. , Non-ohmic contact.
[0033]
Note that the reaction suppression layer 22 on the second contact hole 20 side is not necessarily completely removed, but at least a treatment for removing the oxide layer is performed, and the reaction existing on the first contact hole 30 side. The state may be such that it is thinner than the suppression layer 32 and an ohmic contact is obtained, and it can be regarded as substantially removed. Actually, it is not always easy to obtain perfect ohmic characteristics in the second contact hole when the size of the contact hole becomes fine. However, even if there is a slight non-ohmic property, it can be considered that the element is effectively ohmic as long as the element (transistor) used is within an allowable range for the operation. On the other hand, the first contact hole does not require ohmic properties because it is used for writing by applying a high voltage exceeding, for example, 10 V to the fuse element. Therefore, there is no problem because the reaction suppression layer is not removed at all and a state having clear non-ohmic characteristics is obtained. At the time of writing, since the non-ohmicity is eliminated by forming a conductive filament as described later, the conduction state after writing can be detected without any problem.
The reaction suppression layer 32 on the first contact hole 30 side is a reaction suppression layer formed by exposing the surface irradiated with plasma at the time of plasma etching for opening the contact hole to the atmosphere, oxygen plasma, or the like. In the case where the reaction suppression effect is too high and the program voltage (writing voltage) is too high, light etching is performed, and the surface exposed to the plasma of the light etching is exposed to air and washed to form an appropriate reaction suppression layer. It may be formed.
When the damaged layer is completely removed by light etching, a reaction suppression layer is formed substantially only by the oxide layer formed by exposing the substrate to an oxidizing atmosphere after plasma irradiation. By adjusting the amount of light etching, a state in which a thin damaged layer remains can be obtained.
[0034]
FIG. 2 shows a plan view of the N-channel MOS transistor type anti-fuse element thus formed. In this figure, illustration of ordinary elements formed on the same semiconductor substrate is omitted.
As shown in FIG. 2, a gate electrode 13 is formed on an active region 10 in a P well (not shown), and N, which is a source region and a drain region on the left and right sides of the gate electrode 13, respectively. ⁺ Diffusion regions 15 and 17 are formed, and contact holes 18 and 20 are formed therein, respectively.
The source electrode 14 and the drain electrode 16 made of, for example, an AlCu film are connected through the contact holes 18 and 20.
[0035]
By applying a predetermined write voltage between the source and drain electrodes 14 and 16, a short circuit occurs between the source region and the drain region. For example, when a negative voltage is applied to the source electrode 14 side, the drain side N ⁺ When a voltage exceeding the reverse breakdown voltage is applied to the PN junction between the diffusion region 17 and the P-type channel region, breakdown of the PN junction occurs, and current flows from the drain electrode 16 to the source electrode 14 toward the source electrode 14. Begins to flow. Under the force of the electron flow generated by this, a fluid metal, in this case, aluminum contained in the electrode flows from the electrode 14 on the source side, and penetrates the reaction suppression layer to form a bottom portion of the contact hole 14. N ⁺ It penetrates into the diffusion region 15 and further reaches the PN junction between the drain and the channel through the channel region below the gate electrode 13. As a result, the PN junction between the drain and the channel is permanently destroyed, and data is written. That is, the program is executed.
Actually, the application of the write voltage is further continued to allow the fluid metal to reach the drain electrode 16 from the bottom of the drain-side contact hole 16 through the reaction suppression layer. As a result, a conductive filament that short-circuits between the source electrode 14 and the drain electrode 16 is formed, and a state having a low resistance of 100Ω or less is obtained.
[0036]
In FIG. 2, the size of each part of the anti-fuse element is, typically, a gate width W = 6 to 10 μm, a gate length L = 1 μm, a contact hole diameter S = 1 to 2 μm, and a contact hole from an end of the gate electrode 12 to the contact hole. The distance X = 1 to 2 μm to 18 (20), and the area of the electrode 14 (16) is 18 μm ² It is.
[0037]
Table 1 shows the dependence of the initial yield and the write voltage on the type of the electrode film. Table 1 shows that the fuse transistor size is W / L = 3.4 μm / 1 μm, Cx / Cy = 1.4 μm / 1.4 μm, and the electrode area is 6400 μm. ² It is an example in the case of. Here, an electrode having an extremely large area was used to increase the probability of Al spike generation.
[Table 1]

[0038]
In Table 1, "No Ar etch" means that an AlSi film containing 1 wt% of Si or an AlCu film containing 0.5 wt% of Cu is deposited while leaving the reaction suppression layer at the bottom of the contact hole. This is the case where electrodes are formed. The case where “Ar etch” is indicated is a case where an electrode is formed after etching with Ar ions to remove the reaction suppression layer on the bottom surface of the contact hole for comparison. In this case, in order to remove the entire reaction suppression layer including both the oxide layer and the damaged layer, the SiO 2 is removed. ₂ Etching of 5 nm or more was performed in conversion.
When the electrode is formed of an AlSi film, a 100% initial yield can be obtained regardless of whether or not Ar etching is performed. This is because the AlSi film contains Si exceeding the solid solubility in the heat treatment during the manufacturing process (up to about 400 ° C.), and Al spikes were generated even when the reaction suppression layer was not present. I understand that there is. On the other hand, when the electrode is formed of an AlCu film, the initial yield becomes 0% when Ar etching is performed. It can be understood that this is because Al spikes having a high density occurred during the manufacturing process because the AlCu film containing no Si was directly in contact with the surface of the semiconductor region from which the reaction suppression layer was removed by the Ar etching. On the other hand, when Ar etching was not performed, an initial yield of 96%, which was close to 100%, was obtained, and it can be seen that the occurrence of Al spikes was effectively suppressed by the presence of the reaction suppression layer.
[0039]
The writing voltage required for writing is 11.5 V on average when an electrode made of an AlSi film is formed by performing Ar etching, whereas the writing voltage required for writing is not dependent on the electrode material when Ar etching is not performed. It will be as high as 16V. This is interpreted to be because the presence of the reaction suppression layer suppressed the penetration of the fluid metal into the semiconductor region. However, the degree of increase in the write voltage is not large and is within a range that can be practically handled.
As described above, by intentionally leaving the reaction suppression layer, even when the electrode is formed using an Al film containing no Si such as AlCu, the electrode is formed within a practical write voltage range. It was found that the initial yield could be greatly increased. In the example shown in Table 1, the processing yield does not reach 100%, but this is because the electrode area is as large as 6400 μm 2. As described below, the electrode area and the layout are further optimized by optimizing the layout. It was found that a high initial yield could be obtained.
[0040]
Table 2 shows the initial yield in the case where electrodes made of AlCu films having various areas are formed for contact holes of Cx = Cy = 1.4 μm. Here, in order to clarify the influence of the electrode area, a result when Ar etching of 1 to 2 nm is performed is shown. With this etching amount, the reaction suppression layer becomes thin but is not completely removed.
[Table 2]

[0041]
From Table 2, it can be seen that the smaller the electrode area, the higher the initial yield, ² That is, when the electrode area is about 9 times as large as the contact hole area of Cx = Cy = 1.4 μm, it reaches 100%. This is because the ratio of the electrode area to the area of the contacting semiconductor region at the bottom of the contact hole is reduced by reducing the electrode area while keeping the dimensions of the contact hole constant, and the amount of Si absorbed from the semiconductor region is reduced. However, as a result, it can be understood that the generation of Al spikes was suppressed. From these results, it is possible to obtain a high initial yield if the ratio of the electrode area to the area of the contact hole connected to the semiconductor region forming the antifuse is kept at a predetermined value or less, and in the example of Table 2, is about 9 times or less. It is considered possible.
[0042]
However, in an actual semiconductor integrated circuit, it is not easy to keep the area of the electrode connected to the anti-fuse element below a predetermined value. Since the electrode connected to the contact hole of the anti-fuse element is usually used also as a wiring for connecting the anti-fuse element to another element on the semiconductor integrated circuit, the electrode area varies depending on the position of the element to be connected. It is because.
In order to keep the electrode area below a predetermined value, the electrodes 14 and 16 are used only as electrodes for connecting to the semiconductor region of the anti-fuse element, and another wiring is used for connection with other elements. It is effective to do. For this purpose, specifically, as shown in the plan view of FIG. 3A and the sectional view of FIG. 3B, the source and the source are formed at the bottoms of the contact holes 18 and 20 formed in the first wiring layer. A second interlayer insulating film 40 is formed on the electrodes 14 and 16 connected to the drain regions 15 and 17, and a first layer wiring and a first layer wiring are formed on the interlayer insulating film 40 near the contact holes 18 and 20. Interlayer connection holes 48 and 50 for connecting to the second layer wiring are provided, and the first layer wirings 14 and 16 are connected to the second layer wirings 54 and 56 by plugs 45 and 47 filling the interlayer connection holes 48 and 50. And the connection with other elements is made only through the second layer wirings 54 and 56. That is, the electrodes 14 and 16 are used only for connection between the contact holes 18 and 20 and the plugs 45 and 47, and are not used for connection to other elements. By forming the plugs 45 and 47 with barrier metal films (diffusion prevention films) 41 and 43 and tungsten films 42 and 44 in the same manner as the plug 25, the source and drain regions connected at the bottoms of the contact holes 18 and 20 are formed. The diffusion of Si absorbed from 15 and 17 is blocked by the barrier metal films 41 and 43. As a result, the area of the AlCu electrode which reacts with the source / drain regions 15 and 17 to cause aluminum spikes can be limited to only the portions 14 and 16 formed in the first wiring layer. As a result, the ratio of the area of the electrode and the area of the contact hole, which affect the occurrence of aluminum spikes, is reliably reduced to a predetermined value or less even if the length of the wiring portion used for connection with other elements changes. Can be maintained.
[0043]
More specifically, the anti-fuse element having the contact holes 18 and 20 shown in FIG. 3, the first layer wirings 14 and 16 having a predetermined area with respect to the area of the contact holes 18 and 20, The plugs 45 and 47 arranged near the holes 18 and 20 are prepared as one unit (cell), and are used as a unit when designing a semiconductor device using an anti-fuse element. This makes it possible to maintain a constant ratio between the area of the electrode connected to the anti-fuse element and the area of the contact hole irrespective of the configuration of the semiconductor device to be designed. There is no particular limitation on the distance between each of the contact holes 18 and 20 and the corresponding plug 45 or 47. However, as long as the manufacturing process to be used permits, it is preferable to provide an unnecessarily large margin, It is preferable to reduce the distance to reduce the dimensions of the electrodes 14 and 16 of the first wiring layer.
[0044]
Depending on the dimensions of the interlayer connection holes 48 and 50, it may not be necessary to form a plug using the tungsten films 42 and 44. In this case, only barrier metal films 41 and 43 for preventing diffusion of silicon are formed, and for example, an AlCu film is deposited from inside the interlayer connection holes 48 and 50 onto the second interlayer insulating film 40, and is patterned. By doing so, the wirings 54 and 56 of the second layer may be formed. In this case as well, the range in which the silicon absorbed from the source / drain regions 15 and 17 is diffused by the barrier metal films (diffusion prevention films) 41 and 43 is limited to the range of the electrodes 14 and 16 of the first wiring layer. Is suppressed.
When the ratio of the area of the electrode to the area of the contact hole is increased for some reason, the area of the electrode is substantially reduced to prevent the occurrence of aluminum spikes. There is a method in which a silicon film is arranged and connected to an electrode connected to a semiconductor region of an anti-fuse element. Even when the wiring is formed of a film containing no Si such as AlCu, silicon is supplied from the connected dummy polycrystalline silicon film, so that the amount of silicon absorbed from the diffusion regions 12a and 12b is suppressed, and aluminum spikes are generated. Is suppressed.
[0045]
In this case, as shown in the plan view of FIG. 4A and the cross-sectional view of FIG. 4B, for example, simultaneously with the formation of the gate electrode 13, the polycrystalline silicon films 51 and 52 are formed on the element isolation region 19. At the same time as the opening of the contact holes 18 and 20 for the anti-fuse element, the contact holes 58 and 60 for connecting to these polycrystalline silicon films are opened. At the same time as the deposition of the AlCu film in the contact holes 18 and 20, an AlCu film is also deposited in the contact holes 58 and 60, and patterning is performed so that the electrodes 14 and 16 are connected to the contact holes 18 for the anti-fuse element. 20 are formed to extend from each of the contact holes 20 to the corresponding contact holes 58 and 60 for the polycrystalline silicon film, and are formed so as to connect between them. In this case, a reaction suppression layer 62 similar to the reaction suppression layer 32 at the bottom of the contact holes 18 and 20 for the anti-fuse element remains at the bottom of the contact holes 58 and 60 for the polycrystalline silicon film.
[0046]
At this time, in order to effectively utilize the effect of effectively reducing the electrode area by connecting the polycrystalline silicon films 51 and 52, as shown in the plan view of FIG. It is preferable to increase the number of contact holes 58 and 60 connected to the polycrystalline silicon film as compared with the number of contact holes 18 and 20 connected to the polysilicon film. Specifically, when the dimensions of the contact holes 18 and 20 and the dimensions of the contact holes 58 and 60 are the same, the number ratio is at least three times or more, or more preferably about ten times or more. To When the dimensions of the contact holes 18 and 20 are different from the dimensions of the contact holes 58 and 60, the ratio of the total area of the contact holes may be set to the above value.
[0047]
The distance between each of the contact holes 18 and 20 for the anti-fuse element and the corresponding contact holes 58 and 60 for the polycrystalline silicon film is not particularly limited. However, by making the distance between them as short as possible without providing an unnecessarily large margin within the range allowed by the manufacturing process to be used, the effect of supplying Si from the polycrystalline silicon film can be effectively utilized, and The electrode area with respect to the contact hole area of the fuse element can be effectively reduced.
The polycrystalline silicon film used as a dummy may be formed simultaneously with the gate electrode by using the first polycrystalline silicon layer, or may be formed by using the second polycrystalline silicon layer to form a capacitor element. It may be formed simultaneously with the upper electrode and the high resistance element.
Furthermore, a semiconductor (Si) substrate surface region separated from other elements can be used as a dummy. For example, when an N-channel MOS transistor whose source is fixed to the GND potential is used as an anti-fuse element, the source region is formed by a P-type region formed in a P-well region on the surface of the Si substrate. ⁺ The P well is connected to the diffusion region and a GND potential is supplied to the P well. In the drain region, N formed in the N-well region ⁺ Connect to the diffusion area. At the time of writing, a high voltage for writing is also applied to the N well. On the other hand, at the time of reading, no voltage is applied to the N well, and the N well is set to the same potential as the drain.
[0048]
As described in detail above, according to the present embodiment, the reaction suppression layer is left between the AlCu wiring and the Si substrate in the contact connection portion, and further, the electrode (dimension / layout) for the fuse element is formed. By optimizing, it was possible to suppress the occurrence of aluminum spikes before writing and to stabilize the initial yield while keeping the writing voltage within an allowable range.
[0049]
As described above, the semiconductor device and the electrode forming method of the present invention have been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications can be made without departing from the gist of the present invention. Of course, changes may be made.
For example, as the programmable element, not only the illustrated N-channel MOS transistor type anti-fuse element but also various elements such as a P-channel MOS transistor type and a PN junction diode (Zener zap diode) type can be used. As described above, in the case of the N-channel MOS transistor type, the fluid metal of the source electrode, which becomes negative at the time of writing, passes through the channel region from the source diffusion region, which is the semiconductor region to which the source electrode is connected, and -Writing is performed by breaking into the PN junction between the channels and breaking the junction. In a PN junction diode, for example, when writing is performed by applying a reverse voltage, the fluid metal of the anode electrode to which a negative voltage is applied to the cathode electrode is the semiconductor region to which the anode electrode is connected. ⁺ From the diffusion region, this P ⁺ Between the diffusion region and the N diffusion region provided adjacent thereto, or ⁺ A P diffusion region provided adjacent to the diffusion region, and an N diffusion region further provided adjacent thereto. ⁺ Writing is performed by invading a PN junction formed between the diffusion region and the junction and destroying the junction.
[0050]
The junction to be destroyed is formed in the semiconductor substrate in the exemplified MOS transistor type anti-fuse element. That is, the junction exists in the surface region of the semiconductor substrate itself. Similarly, in a PN junction type, it is possible to provide a junction in a semiconductor substrate. However, for example, a MOS transistor or a PN junction diode used as an anti-fuse element may be formed in a polycrystalline silicon film formed on a semiconductor substrate via an element isolation field insulating film formed on the surface thereof. It is possible. However, in order to form a stable reaction suppression layer of stable film quality by exposing it to an oxidizing atmosphere after plasma irradiation, and to stabilize the initial yield while maintaining the write voltage within an allowable range, at least an electrode which is on the negative side during writing is required. Is preferably formed in the surface region of the semiconductor substrate itself.
[0051]
The electrode connected to the anti-fuse element is not limited to the case where the fluid metal is aluminum, in addition to the exemplified AlCu, uses pure Al, and various other Al alloy films mainly containing Al. Can be formed. However, the effect of suppressing the generation of aluminum spikes by the reaction suppression layer and stabilizing the initial yield is that an aluminum alloy film containing no pure Al or Si is highly likely to generate aluminum spikes without the reaction suppression layer. It is remarkably exhibited when using. Alternatively, even if Si is included, the content is smaller than the solid solubility at the heat treatment temperature performed in the manufacturing process after the electrode is formed, and the aluminum spike is more likely to occur without the reaction suppression layer. In that sense, even when an Al alloy film substantially containing no Si is used, the effect of the reaction suppression layer is remarkably exhibited.
As a fluid metal that writes into the junction of the anti-fuse element to write data, in addition to aluminum, for example, as described in Patent Document 2, a metal forming silicide such as titanium, gold, copper, or silver Etc. can be used.
[0052]
【The invention's effect】
As described above, according to the present invention, it is possible to suppress the occurrence of aluminum spikes before writing and to stabilize the initial yield while keeping the writing voltage of the anti-fuse element within an allowable range.
[Brief description of the drawings]
FIGS. 1A to 1H are schematic views showing step by step the steps of manufacturing a semiconductor device by the method for forming an electrode of a semiconductor device according to the present invention.
FIG. 2 is a plan view schematically showing the semiconductor device according to the embodiment.
FIGS. 3A and 3B are a plan view and a cross-sectional view, respectively, schematically illustrating a semiconductor device according to another embodiment of the present invention.
FIGS. 4A and 4B are a plan view and a cross-sectional view, respectively, schematically showing a semiconductor device according to still another embodiment of the present invention.
FIG. 5 is a plan view schematically showing an example of a conventional MOS transistor type antifuse.
[Explanation of symbols]
10. Silicon substrate
11a N well
11b P well
12a P ⁺ diffusion
12b N ⁺ diffusion
13 Gate electrode
14, 16 electrodes
18, 20, 58, 60 Contact holes
19 Device isolation area
16, 40 interlayer insulating film
21, 28 Photoresist pattern
20 (second) contact hole
20a Surface of (second) contact hole
22 Reaction suppression layer (at bottom of second contact hole)
24, 41, 43 Barrier metal film
25, 45, 47 plug
26, 42, 44 Tungsten film
30 Contact hole for fuse (first contact hole)
30a Surface of (first) contact hole
32 Reaction suppression layer (at bottom of first contact hole)
34 AlCu film
48, 50 interlayer connection hole
51, 52 Polycrystalline silicon film
54, 56 Second layer wiring
62 Reaction suppression layer

Claims (9)

An electrode forming method for a semiconductor device, comprising: forming an electrode connected to a first element that is programmable by invasion of a fluid metal into a junction,
Forming an insulating film on a semiconductor substrate having a first semiconductor region constituting the first element;
A portion of the insulating film is selectively removed, a first contact hole exposing the first semiconductor region is opened at a bottom thereof, and a first plasma is formed on a surface of the exposed first semiconductor region. Forming a first reaction-suppressing layer including an oxide layer by exposing the film to an oxidizing atmosphere;
Depositing a film containing the fluid metal as a main component in the first contact hole without removing the first reaction suppression layer, and removing the first semiconductor through the first reaction suppression layer; Forming a first electrode made of a film containing the fluid metal as a main component connected to a region;
A method for forming an electrode of a semiconductor device, comprising: An electrode forming method for a semiconductor device, comprising: forming an electrode connected to each of a first element which can be programmed by invasion of a fluid metal into a junction and a second element other than the first element,
Forming an insulating film on a semiconductor substrate having a first semiconductor region forming the first element and a second semiconductor region forming the second element;
A first region of the insulating film is selectively removed, a first contact hole for exposing the first semiconductor region is opened in a bottom portion thereof, and a first contact hole is formed on a surface of the exposed first semiconductor region. Forming a first reaction suppression layer including an oxide layer by exposing the substrate to an oxidizing atmosphere after irradiating the plasma;
Depositing a film containing the fluid metal as a main component in the first contact hole without removing the first reaction suppression layer, and removing the first semiconductor through the first reaction suppression layer; Forming a first electrode made of a film containing the fluid metal as a main component connected to a region;
A second region of the insulating film is selectively removed, a second contact hole exposing the second semiconductor region is opened at the bottom thereof, and a second contact hole is formed on the surface of the exposed second semiconductor region. Forming a second reaction-suppressing layer including an oxide layer by exposing the substrate to an oxidizing atmosphere after the plasma irradiation;
At least removing the oxide layer of the second reaction suppression layer, and subsequently forming a plug made of a high melting point metal in the second contact hole;
A method of forming an electrode of a semiconductor device, comprising: The plug is formed in the second contact hole before the opening of the first contact hole, and the plug is formed on the entire surface of the insulating film where the first and second contact holes are opened. Depositing a film containing a fluid metal as a main component, and simultaneously forming the first electrode, forming a second electrode connected to the second semiconductor region through the plug. The method for forming an electrode of a semiconductor device according to claim 2. 4. The method according to claim 1, wherein the irradiation of the first plasma is performed during over-etching of the plasma etching for opening the first contact hole. 5. The method according to claim 1, wherein the film containing a fluid metal as a main component is an aluminum or aluminum alloy film containing substantially no silicon. A semiconductor device in which a first element programmable by invasion of a fluid metal into a junction and a second element other than the first element are formed on the same semiconductor substrate,
A first contact hole formed on the semiconductor substrate and exposing a first semiconductor region forming the first element at a bottom thereof, and a second semiconductor region forming the second element at a bottom thereof An insulating film having a second contact hole exposing
A first electrode formed of a film containing a fluid metal as a main component and formed in the first contact hole, and a plug made of a high-melting metal embedded in the second contact hole. ,
A reaction suppression layer including at least an oxide layer is formed on the surface of the first semiconductor region exposed at the bottom of the first contact hole, and the first electrode is connected to the first electrode via the reaction suppression layer. Non-ohmic connection to the semiconductor region of
A reaction suppression layer is not substantially present on the surface of the second semiconductor region exposed at the bottom of the second contact hole, and the plug is ohmically connected to the second semiconductor region. Semiconductor device. A semiconductor device in which a plurality of other elements are formed on the same semiconductor substrate, including a first element that can be programmed by invasion of a fluid metal into a junction and another second element,
A first contact hole formed on the semiconductor substrate and exposing a first semiconductor region forming the first element at a bottom thereof, and a second semiconductor region forming the second element at a bottom thereof An insulating film having a second contact hole exposing
A first electrode made of a film containing a fluid metal as a main component and formed from the inside of the first contact hole onto the insulating film; and a plug made of a high melting point metal embedded in the second contact hole. When,
An upper wiring formed on the first electrode via an interlayer insulating film;
A reaction suppression layer including at least an oxide layer is formed on the surface of the first semiconductor region exposed at the bottom of the first contact hole, and the first electrode is connected to the first semiconductor region via the reaction suppression layer. Connected to the semiconductor region of
A reaction suppression layer is not substantially present on the surface of the second semiconductor region exposed at the bottom of the second contact hole, and the plug is directly connected to the second semiconductor region;
The first electrode is connected to the upper wiring via a diffusion prevention film for preventing diffusion of silicon in the vicinity of the first contact hole, and the first electrode is connected to any of the other elements. A semiconductor device, which is connected only through a diffusion prevention film and an upper wiring. A semiconductor device in which a first element programmable by invasion of a fluid metal into a junction formed in a semiconductor substrate and another second element are formed on the semiconductor substrate,
A first contact hole formed on the semiconductor substrate and exposing a first semiconductor region forming the first element at a bottom thereof, and a second semiconductor region forming the second element at a bottom thereof An insulating film having a second contact hole exposing a second contact hole, and a third contact hole exposing a polycrystalline silicon film formed on the element isolation region on the surface of the semiconductor substrate at the bottom thereof;
A first electrode formed from a film containing a fluid metal as a main component, formed from inside the first contact hole to inside the third contact hole;
A plug made of a refractory metal embedded in the second contact hole;
Has,
A reaction suppression layer including at least an oxide layer is formed on a surface of the first semiconductor region exposed at a bottom of the first contact hole, and the first electrode is connected to the second electrode via the reaction suppression layer. 1 semiconductor region,
A reaction suppression layer is not substantially present on the surface of the second semiconductor region exposed at the bottom of the second contact hole, and the plug is directly connected to the second semiconductor region. Semiconductor device. 9. The semiconductor device according to claim 6, wherein the film containing a fluid metal as a main component is an aluminum or aluminum alloy film containing substantially no silicon.

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