TWI740531B - High-voltage semiconductor device - Google Patents

Abstract

A high-voltage semiconductor device includes a substrate, a buried layer, a drain region, a source region, a gate and at least one concentration modulated regions. The substrate includes a first conductive type, and the buried layer is disposed in the substrate and includes a second conductive type. The drain region and the source region are respectively disposed in the substrate and over the buried layer, and the gate is disposed on the substrate and between the source region and the drain region. The at least one concentration modulated regions are disposed in a portion of the buried layer, under the drain region, wherein the at least one concentration modulated regions include the second conductive type, and the doped concentration of the at least one concentration modulated regions is lower than that of the buried layer.

Description

High-voltage semiconductor device

The present invention relates to a semiconductor device, and more particularly to a high-voltage semiconductor device.

With the improvement of semiconductor technology, the industry has been able to integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and related components on a single chip at the same time to reduce costs and improve operating efficiency. Transistor elements, which are commonly used to amplify current or voltage signals in circuits, as circuit oscillators, or as switching elements that control circuit switching operations, have been applied as high-power elements or high-voltage with the advancement of semiconductor process technology. element. For example, a transistor component as a high-voltage component is placed between the internal circuit of the chip and the input/output (I/O) pins to prevent a large amount of charge from passing through the I/O pins in a very short time. Enter the internal circuit and cause damage.

In the current transistor components as high-voltage components, the effect of increasing the breakdown voltage is mainly achieved by reducing the lateral electric field, and the structure roughly includes double diffused drain metal oxide semiconductor (double diffused drain metal oxide semiconductor). MOS, DDDMOS), laterally diffused MOS (LDMOS) and other components. However, how to further increase the breakdown voltage of high-voltage semiconductor devices? Complying with practical requirements is a topic facing the industry at present.

An object of the present invention is to provide a high-voltage semiconductor device, which is locally added at least one concentration-modulated region in the buried insulating layer below the drain region, the at least one concentration-modulated region having the same thickness as the buried insulating layer The conductivity type, the same dopant, and a lower doping concentration can reduce the electric field intensity under the drain region, thereby increasing the breakdown voltage of the high-voltage semiconductor device.

To achieve the above objective, a preferred embodiment of the present invention provides a high-voltage semiconductor device, which includes a substrate, a buried layer, a drain region, a source region, a gate, and at least one concentration modulation region. The substrate has a first conductivity type, and the buried layer is disposed in the substrate and has a second conductivity type that is complementary to the first conductivity type. The drain region is disposed in the substrate and above the buried layer, and the drain region has the first conductivity type. The source region is disposed in the substrate and above the buried layer, and the source region has the first conductivity type. The gate is arranged on the substrate and is located between the source region and the drain region. The at least one concentration modulation area is arranged in a local buried layer. The at least one concentration-modulated region is located under the drain region and has the second conductivity type, and the doping concentration of the concentration-modulated regions is less than the doping concentration of the buried layer.

100, 300, 400, 500, 600: high-voltage semiconductor devices

110: Base

120, 320, 420, 520, 620: buried layer

121: Concentration modulation area

130: The first well area

140: The second well area

150: Drain area

160: source region

170: matrix area

190, 191, 193, 195: insulation structure

210: Gate

211: gate dielectric layer

213: gate electrode layer

321: Concentration Modulation Area

323: Square doped area

421: Concentration Modulation Area

521, 523: Concentration modulation area

621, 623: Concentration modulation area

D1: First direction

D2: second direction

E1, E2: Curve

FIG. 1 is a schematic top view of the high-voltage semiconductor device in the first embodiment of the present invention.

Figure 2 is a schematic cross-sectional view taken along the line A-A' in Figure 1.

FIG. 3 is a schematic diagram of a simulation of the high-voltage semiconductor device in the first embodiment of the present invention.

FIG. 4 shows a schematic diagram of a high-voltage semiconductor device in the second embodiment of the present invention.

FIG. 5 shows a schematic diagram of a high-voltage semiconductor device in the third embodiment of the present invention.

FIG. 6 shows a schematic diagram of a high-voltage semiconductor device in the fourth embodiment of the present invention.

FIG. 7 shows a schematic diagram of a high-voltage semiconductor device in the fifth embodiment of the present invention.

In order to enable those who are familiar with the technical field of the present invention to have a better understanding of the present invention, a few preferred embodiments of the present invention are listed below, together with the accompanying drawings, to explain in detail the content of the present invention and what it intends to achieve. The effect. Moreover, those who are familiar with the technical field of the present invention can also refer to the following embodiments without departing from the spirit of the present invention, and replace, reorganize, and mix the features in several different embodiments to complete other implementations. example.

In the present invention, the description of "the first part is formed on or above the second part" can mean "the first part is in direct contact with the second part", or it can mean "between the first part and the second part" There are other parts", so that the first part and the second part are not in direct contact. In addition, various embodiments of the present invention may use repeated component symbols and/or text annotations. The use of these repeated component symbols and text notes is to make the description more concise and clear, rather than to indicate the association between different embodiments and/or configurations. In addition, for the space-related narrative vocabulary mentioned in the present invention, for example: "below", "above", "low", "high", "below", "above" "", "below", "above", "bottom", "top" and similar words, for ease of description, their usage is to describe one component or feature and another (or more) component or The relative relationship of features. Except in the scheme The displayed swing outwards, and these space-related words are also used to describe the possible swing directions of the semiconductor device during the manufacturing process, in use, and operation. For example, when the semiconductor device is rotated by 180 degrees, a component that was originally placed "above" other components will become "below" other components. Therefore, as the swing direction of the semiconductor device is changed (rotated by 90 degrees or other angles), the space-related narrative used to describe its swing direction should also be interpreted in a corresponding manner.

Although the present invention uses terms such as first, second, and third to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and / Or the block should not be restricted by these words. These terms are only used to distinguish an element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and they do not mean or represent the element. Any preceding ordinal number does not represent the order of arrangement of a component and another component, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or block discussed below may also be termed as the second element, component, region, layer, or block Of.

The term "about" or "substantially" mentioned in the present invention usually means within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, the meaning of "approximate" or "substantial" can still be implied when there is no specific description of "approximate" or "substantial".

Please refer to Figures 1 and 2, which illustrate the high voltage in the first embodiment of the present invention A schematic diagram of the semiconductor device 100, wherein FIG. 1 is a schematic top view of the high-voltage semiconductor device 100, and FIG. 2 is a schematic cross-sectional view of the high-voltage semiconductor device 100. The high-voltage semiconductor device of the present invention refers to a semiconductor device whose operating voltage is approximately higher than 90 volts (V), which is, for example, a laterally diffused metal oxide semiconductor transistor (LDMOS transistor), which may be a laterally diffused metal oxide semiconductor transistor (LDMOS transistor). Type metal oxide semiconductor transistor or laterally diffused P-type metal oxide semiconductor transistor. In this embodiment, the high-voltage semiconductor device 100 is described with a laterally diffused P-type metal oxide semiconductor transistor as an implementation mode, but it is not described in terms of This is limited.

First, as shown in FIGS. 1 and 2, the high-voltage semiconductor device 100 includes a substrate 110, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (silicon-on-insulator, SOI) substrate, etc., and at least one insulating structure 190 disposed on the substrate 110. In this embodiment, the insulating structure 190 is, for example, a field oxide (FOX) layer formed by a local oxidation of silicon (LOCOS) method, as shown in FIG. 2, but it is not limited to this. . In another embodiment, the insulating structure may also be a shallow trench isolation (STI) formed through a deposition process or an insulating unit manufactured through other suitable processes. It should be noted that, in order to clearly show the relative relationship of certain specific doped regions in the high-voltage semiconductor device 100, the insulating structure 190 is omitted in the first figure, but those familiar with the art should be able to easily understand the insulating structure according to the second figure. The location of the structure 190. In addition, the specific location and quantity of the insulating structure 190 of the present invention will be described in subsequent paragraphs.

The substrate 110 has a first conductivity type (for example, P-type), and a first well area 130 and a second well area 140 are respectively disposed therein. Specifically, the first well area 130 has the The first conductivity type (such as P-type), and a drain region 150 is also formed in the first well region 130. The drain region 150 also has the first conductivity type (such as P-type), and its doping concentration is preferably greater than the doping concentration of the first well region 130. The second well region 140 is arranged around the outside of the first well region 130 and has a second conductivity type (such as N-type). The second conductivity type (such as N-type) is the same as the first conductivity type (such as P-type). ) Complementary. In this embodiment, the depth of the second well region 140 in the base 110 is, for example, greater than that of the first well region 130, as shown in FIG. 2, but it is not limited thereto. A source region 160 is formed in the second well region 140, and the source region 160 has the first conductivity type (such as P-type).

In addition, a body region 170 is formed in the second well region 140. The body region 170 has the second conductivity type (such as N-type) and its doping concentration is preferably greater than that of the second well region 140 . In an embodiment, the base region 170 preferably does not directly contact the drain region 150 provided in the first well region 130. For example, two opposite sides of the base region 170 can be provided with an insulating structure 191 and an insulating structure 193, and two opposite sides of the drain region 150 can be provided with an insulating structure 193 and an insulating structure 195, so that the insulating structure 193 can be sandwiched It is arranged between the drain region 150 and the base region 170 so that the drain region 150 and the base region 170 are electrically isolated from each other, as shown in FIG. 2. In addition, in an embodiment, the base region 170 may have a ring shape, for example, a rectangular frame shape as shown in FIG. 1, and may surround the drain region 150 and the source region 160. However, those skilled in the art should understand that in another embodiment, the base region may also have other shapes, such as square, circular, racetrack-shaped or other suitable shapes, etc. 1 is limited to those shown in the figure. In addition, a gate 210 is further provided on the substrate 110. The gate 210 may include a gate dielectric layer 211 and a gate electrode layer 213 sequentially stacked on the substrate 110. The gate electrode layer 213 is, for example, a Polysilicon gate layer or metal gate layer, but not limited to this. Gate 210 is located at Between the source region 160 and the drain region 150. In this embodiment, one side of the gate 210 partially covers the second well region 140 in the substrate 110 and is adjacent to the source region 160, while the other side of the gate 210 partially covers the first well region 130 and On the insulating structure 195, it does not directly contact the drain region 150.

On the other hand, a buried layer 120 is also provided in the base 110, which is located under the first well area 130 and the second well area 140. The buried layer 120 may have the second conductivity type (such as N-type) and its doping concentration is higher than the doping concentration of the first well region 130 and the second well region 140. In this embodiment, the buried layer 120 and the second well region 140 in the substrate 110 are used together as an isolation layer of the high-voltage semiconductor device 100 to prevent current from punching through the substrate directly from the first well region 130 The bottom or inner portion of 110 affects the device performance of the high-voltage semiconductor device 100. It should be noted that the high-voltage semiconductor device 100 of this embodiment further includes at least one concentration modulated region 121 partially opened in the buried layer 120. Wherein, the number of the concentration modulation regions 121 may be single or plural. In the high-voltage semiconductor device 100 of this embodiment, two concentration modulation regions 121 separated from each other are arranged in a local buried layer 120 for implementation. The state is explained, but not limited to this. Those skilled in the art should easily understand that the number of the concentration modulation regions can be further adjusted according to actual device requirements, for example, only one concentration modulation region is provided in the local buried layer 120 or more than two concentration modulation regions are provided. The concentration modulation area.

It should be noted that the concentration-modulating region 121 is preferably arranged in a part of the high-voltage semiconductor device 100 where the electric field is strong, such as arranged at a PN junction adjacent to the first well region 130 and the second well region 140 or At the PN junction between the first well area 130 and the buried layer 120, but not limited to this. For example, the concentration modulation region 121 can be disposed in the drain region 150 and The buried layer 120 below the first well area 130 extends between the top surface and the bottom surface of the buried layer 120 and directly contacts the first well area 130, as shown in FIG. 2. Wherein, each concentration modulation region 121 is, for example, a strip-shaped doped region in a top view as shown in FIG. 1, and the entire coverage area of the concentration modulation region 121 is preferably smaller than the coverage area of the first well region 130 , As shown in Figure 1 and Figure 2. In a preferred embodiment, the projection range of the concentration modulation region 121 in a direction (not shown) perpendicular to the substrate 110 does not exceed the projection range of the first well region 130 in the vertical direction. In one embodiment, the concentration modulation region 121 is fabricated by, for example, providing a mask (not shown) during the ion implantation process of the buried layer 120, and blocking a local area of the substrate 110 through the mask, so that The local area cannot be implanted with dopants in the ion implantation process, but only a small amount of dopants diffused from the buried layer 120 can be obtained in the subsequent drive-in process. Therefore, the concentration-modulated region 121 may have the same conductivity type (such as N-type), the same dopant, and a relatively low doping concentration as the buried layer 120. For example, the doping concentration of the concentration-modulating region 121 is about 10% to 20% less than the doping concentration of the buried layer 120, preferably about 15%, but not limited to this. In another embodiment, the production of the concentration-adjustable region 121 can also be performed before or after the formation of the buried layer 120. For example, another ion implantation process can be used to directly form a relatively high doping concentration in the local substrate 110. A low doped region is used as the concentration modulation region, and then the buried layer 120 is formed, or, when the buried layer 120 is formed in the substrate 110, a space is reserved locally, and then another ion implantation process is performed in the reserved area. A doped region with a relatively low doping concentration is directly formed in the space as the concentration modulation region, but it is not limited to this.

In other words, the concentration modulation region 121 is at least one slot in the buried layer 120 that is locally provided (the drain region 150 and the part below the first well region 130), and then the self-buried layer 120 is obtained through a thermal drive process. A small amount of dopants diffused out, but can have a relatively low Doping concentration. Therefore, the concentration modulation region 121 can reduce the electric field intensity of the part, thereby improving the problem of low breakdown voltage of the high-voltage semiconductor device 100 in the part with strong electric field intensity (ie, the part near the PN junction or the drain region 150). Under this setting, the breakdown voltage of the high-voltage semiconductor device 100 can be increased by about 5 volts, but is not limited to this. Please refer to FIG. 3, the high-voltage semiconductor device 100 of this embodiment (as shown by the curve E1) can indeed reduce the local electric field strength under the simulation test, and it can be compared with the conventional high-voltage semiconductor device (as shown by the curve E2). Show) to obtain a higher breakdown voltage, but not limited to this. Therefore, the high-voltage semiconductor device 100 of this embodiment can obtain better device performance.

Those with ordinary knowledge in the art should easily understand that the high-voltage semiconductor device of the present invention may also have other aspects, which are not limited to the foregoing, on the premise of meeting actual product requirements. For example, in the foregoing embodiment, although the laterally diffused P-type metal oxide semiconductor transistor is used as an implementation mode for description, the first conductivity type is P-type and the second conductivity type is N-type. Not limited to this. In another embodiment, the first conductivity type may be N-type and the second conductivity type may be P-type to form different types of high-voltage semiconductor devices. The following will further describe other embodiments or variations of the high-voltage semiconductor device. In order to simplify the description, the following description mainly focuses on the differences between the embodiments, and the similarities are not repeated. In addition, the same elements in the embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.

According to another embodiment of the present invention, a high-voltage semiconductor device is provided, which can locally adjust the doping concentration of the buried layer to reduce the local electric field strength while avoiding the excessively low doping concentration of the part that affects the buried layer. The effect of the layer as an insulating layer. Please refer to FIG. 4, which shows a schematic plan view of the high-voltage semiconductor device 300 in the second embodiment of the present invention picture. The structure of the high-voltage semiconductor device 300 in this embodiment is substantially the same as that of the high-voltage semiconductor device 100 described in the first embodiment, and also includes a substrate 110, a first well region 130, a second well region 140, a drain region 150, and a source region. The pole region 160, the base region 170, and the insulating structure 190, etc., the similarities will not be repeated here. The main difference between this embodiment and the previous embodiment lies in the specific setting conditions of the concentration modulation area 321 in the buried layer 320, such as the setting area, pattern design, number, and size.

In detail, in the buried layer 320 of the present embodiment, a plurality of concentration modulation regions 321 are locally provided, and the concentration modulation regions 321 are located below the drain region 150 and the first well region 130. In addition, the concentration-modulated region 321 may have the same conductivity type (such as N-type), the same dopant, and a lower doping concentration as the buried layer 320. It should be noted that the concentration modulation region 321 of this embodiment is, for example, a square doped region, and each of the square doped regions is spaced apart and arranged in a staggered arrangement on a top view as shown in FIG. The whole presents a checkerboard arrangement, but it is not limited to this. In other words, the local buried layer 320 (that is, the part of the buried layer 320 located below the first well region 130) of this embodiment can also form a plurality of square doped regions 323, and the various doped regions 323 have a different concentration. The modulation regions 321 are spaced apart and arranged in a staggered arrangement, as shown in FIG. 4.

Therefore, the concentration modulation region 321 of the present embodiment can be more evenly distributed in the part of the high-voltage semiconductor device 300 where the electric field is strong, so that the doping concentration of the buried layer 320 under the part can be more uniformly reduced, for example Compared with other parts, the doping concentration of the buried layer 320 is reduced by about 10% to 20%, preferably by about 15%, but not limited to this. With this configuration, the high-voltage semiconductor device 300 of the present embodiment can also improve the problem of the low breakdown voltage of the device at the location where the electric field strength is strong (that is, the portion near the PN junction or the drain region 150). Problem, and effectively increase the breakdown voltage of the part, for example, it can increase about 5 volts, so as to obtain better device performance.

In addition, those with ordinary knowledge in the art should easily understand that the number, pattern (such as square or strip), and size of the concentration adjustment regions 321 and 121 in the foregoing embodiment are only examples, and not limited thereto. . In other embodiments, the concentration modulation region can also have other configurations according to actual device requirements, so that the doping concentration of the buried layer can be locally reduced more uniformly to achieve the effect of reducing the electric field intensity. In addition, the overall area occupied by the concentration modulation region in the buried layer can also be adjusted according to actual device requirements. It is better to increase the breakdown voltage of the device as much as possible without affecting the effect of the buried layer as an insulating layer. .

Please refer to FIG. 5 to FIG. 7, which illustrate the top view schematic diagrams of the high-voltage semiconductor devices 400/500/600 in the third, fourth, and fifth embodiments of the present invention, respectively, in which the high-voltage semiconductor device The structure of 400/500/600 is substantially the same as that of the high-voltage semiconductor device 300 described in the aforementioned second embodiment, and will not be repeated here. The main difference between these embodiments and the foregoing second embodiment is that the concentration modulation regions can have a variety of different configurations.

In detail, in the third embodiment, the high-voltage semiconductor device 400 includes a plurality of concentration adjustment regions 421, and each concentration adjustment region 421 is also a square-type doped region (with a lower doping concentration), and each The square doped regions are arranged in the buried layer 420 under the first well region 130 or the drain region 150 in an in-line arrangement in a top view as shown in FIG. 5. In the fourth embodiment, the high-voltage semiconductor device 500 may include both the concentration-modulating region 521 and the concentration-modulating region 523. Density adjustment zone 521 and density adjustment The area 523 can be a rectangular frame-shaped doped area (lower doping concentration) in a top view as shown in FIG. In the buried layer 520 under a well region 130 or the drain region 150, and the concentration modulation region 523 surrounds the concentration modulation region 521. In addition, the geometric centers of the density adjustment region 523 and the density adjustment region 521 may overlap each other, but are not limited thereto. In the fifth embodiment, the high-voltage semiconductor device 600 may include a plurality of concentration-modulating regions 621 and a plurality of concentration-modulating regions 623 at the same time. The concentration-modulated regions 621 are, for example, strip-shaped doped regions (with lower doping concentration) that are parallel to each other and extend along a first direction D1, and the concentration-modulated regions 623 are, for example, parallel to each other and along a second direction D2. In the extended strip-shaped doped region (with lower doping concentration), the second direction D2 is different from the first direction D1. As a result, each concentration modulation region 623 can span the concentration modulation region 621 in a top view as shown in FIG. 7, and a mesh is present in the buried layer 620 under the first well region 130 or the drain region 150 Grid-shaped structure, but not limited to this. In the fifth embodiment, the first direction D1 is, for example, perpendicular to the second direction D2, as shown in Figure 7, but not limited to this. In another embodiment, the first direction and the second direction D2 The directions can also be selected to intersect each other but not perpendicular to each other, so as to still form a density modulation area that presents a grid-like structure as a whole.

In the aforementioned various settings, the density adjustment areas (including the density adjustment area 421 shown in Fig. 5; the density adjustment areas 521 and 523 shown in Fig. 6; and the density adjustment areas shown in Fig. 7 The concentration modulation regions 621, 623) can also be more evenly distributed in the high-voltage semiconductor device 400/500/600 in the area where the electric field is strong, so that the buried layer (including the buried layer 420 shown in Figure 5) The buried layer 520 shown in FIG. 6; and the buried layer 620 shown in FIG. 7). The doping concentration of the buried layer can be reduced more uniformly, for example, the doping concentration of the buried layer is reduced by about 10 compared to other parts % To about 20%, preferably about 15% reduction, but not limited to this. in front Under the various configurations described above, the high-voltage semiconductor device 400/500/600 can also improve the problem of the low breakdown voltage of the device in the part with strong electric field strength (ie the part near the PN junction or the drain region 150), and improve The breakdown voltage of this part can be increased by about 5 volts, for example, to obtain better device performance.

In addition, it should also be noted that in the foregoing embodiments of the present invention, although the concentration modulation regions in various forms are provided in a buried layer for description, those with ordinary knowledge in the field should be able to easily It is understood that the aforementioned concentration modulation regions of the present invention can also be optionally provided in other electrical insulating layers of a high-voltage semiconductor device, for example, formed in a deep well region or a high-voltage well region (HV well). Wait. Thereby, it is also possible to achieve the effect of locally reducing the doping concentration of the electrically insulating layer through the arrangement of the concentration-modulating regions, thereby locally reducing the electric field intensity of the high-voltage semiconductor device.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: High-voltage semiconductor device

120: Buried layer

121: Concentration modulation area

130: The first well area

140: The second well area

150: Drain area

160: source region

170: matrix area

210: Gate

Claims (17)

A high-voltage semiconductor device includes: a substrate having a first conductivity type; a buried layer disposed in the substrate, the buried layer having a second conductivity type, and the second conductivity type is complementary to the first conductivity type A first well region is provided in the substrate; a drain region is provided in the substrate and located above the buried layer, the drain region has the first conductivity type, and the drain region is provided in the In the first well region; a source region is disposed in the substrate and located above the buried layer, the source region has the first conductivity type; a gate is disposed on the substrate and is located in the source Between a region and the drain region; and at least one concentration-modulated region is disposed in a part of the buried layer, the at least one concentration-modulated region is located below the drain region and has the second conductivity type, and the The doping concentration of the at least one concentration adjustment region is less than the doping concentration of the buried layer, and the projection range of the at least one concentration adjustment region does not exceed the projection range of the first well region. The high-voltage semiconductor device according to claim 1, wherein the doping concentration of the at least one concentration adjustment region is reduced by 10% to 20% compared with the doping concentration of the buried layer. The high-voltage semiconductor device according to claim 1, wherein the at least one concentration modulation region includes at least a strip-shaped doped region. The high-voltage semiconductor device according to claim 1, wherein the at least one concentration-modulated region includes a plurality of square doped regions, and the square doped regions are spaced apart and arranged in a staggered arrangement. According to the high-voltage semiconductor device described in claim 1, wherein the at least one concentration-modulated region includes a plurality of square doped regions, and the square doped regions are arranged at intervals. The high-voltage semiconductor device according to claim 1, wherein the at least one concentration modulation region includes at least one rectangular frame-shaped doped region. The high-voltage semiconductor device according to claim 1, wherein the at least one concentration-modulated region is plural, and the concentration-modulated regions include a first concentration-modulated region extending along a first direction, and A second density adjustment zone extending along a second direction, the second density adjustment zone straddles the first density adjustment zone, and the first direction is different from the second direction. According to the high-voltage semiconductor device described in claim 1, wherein the first well region has the first conductivity type. The high-voltage semiconductor device according to item 8 of the scope of patent application, wherein the coverage area of the at least one concentration modulation region is smaller than the coverage area of the first well region. The high-voltage semiconductor device described in item 8 of the scope of the patent application, wherein the At least one concentration adjustment zone directly contacts the first well zone. The high-voltage semiconductor device according to item 8 of the scope of patent application, wherein there is a PN junction between the buried layer and the first well region. The high-voltage semiconductor device described in item 8 of the scope of the patent application further includes: a second well region disposed in the substrate, the second well region having the second conductivity type, wherein the second well region surrounds The first well region and the source region are arranged in the second well region. According to the high-voltage semiconductor device described in item 12 of the scope of the patent application, the doping concentration of the buried layer is greater than the doping concentration of the second well region. The high-voltage semiconductor device according to claim 12, wherein one side of the gate partially covers the second well region, and the side of the gate is adjacent to the source region. The high-voltage semiconductor device described in item 12 of the scope of the patent application further includes a base region located in the second well region, and the base region has the second conductivity type. According to the high-voltage semiconductor device described in item 15 of the scope of patent application, the base region surrounds the drain region and the source region. The high-voltage semiconductor device according to item 15 of the scope of the patent application further includes: a first insulating structure disposed on the substrate and located between the base region and the drain region; and a second insulating structure disposed on the substrate On the substrate, it is located between the drain region and the gate, and the gate does not directly contact the drain region.

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