TWI747379B - High-voltage semiconductor device and method of forming the same - Google Patents

Abstract

High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first isolation structure and a drain diffusion region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first isolation structure is disposed on the substrate, under the gate structure to partially overlapping with the gate structure. The drain diffusion region is disposed in the substrate, under the drain and the first isolation structure, and the drain diffusion region includes a discontinuous junction.

Description

High-voltage semiconductor device and its forming method

The present invention relates to a semiconductor device and its forming method, and more particularly to a high-voltage semiconductor device and its forming method.

With the improvement of semiconductor technology, the industry has been able to integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and related components on a single chip at the same time to reduce costs and improve operating efficiency. Transistor elements, which are commonly used to amplify current or voltage signals in circuits, as circuit oscillators, or as switching elements that control circuit switching operations, have been used as high-power elements or high-voltage components with the advancement of semiconductor process technology. element. For example, a transistor element, which is a high-voltage element, is placed between the internal circuit of the chip and the input/output (I/O) pins to prevent a large amount of charge from passing through the I/O pins in a very short time. Enter the internal circuit and cause damage.

In the current transistor components as high-voltage components, the effect of increasing the breakdown voltage is mainly achieved by reducing the lateral electric field, and the structure roughly includes the introduction of a double diffusion drain into the drift region (drift region). Double diffused drain MOS (DDDMOS), laterally diffused drain MOS (laterally diffused drain MOS, LDMOS) and other components. However, how to further increase the breakdown voltage of high-voltage semiconductor devices to meet practical requirements is a subject currently faced by the industry.

An object of the present invention is to provide a high-voltage semiconductor device and a method for forming the same. The high-voltage semiconductor device is provided with a doped region at the high-voltage end. Carrier injection) problems and the effects of avoiding the collapse of the voltage drop are beneficial to improve the reliability of the components of the high-voltage semiconductor device.

To achieve the above objective, a preferred embodiment of the present invention provides a high-voltage semiconductor device, which includes a substrate, a gate structure, a drain, a first insulating structure, and a drain doped region. The gate structure is arranged on the substrate, and the drain is arranged in the substrate and located on one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure and partially overlaps the gate structure. The drain doped region is disposed in the substrate and is located under the drain and the first insulating structure, and the drain doped region has a discontinuous bottom surface, and the drain doped region further includes a first A drain doped region and a second drain doped region, a part of the area of the first drain doped region projected vertically on the substrate overlaps the area of the drain and the first insulating structure projected vertically on the substrate, The area of the second drain doped region projected vertically on the substrate does not overlap with the area of the first insulating structure projected vertically on the substrate, and the second drain doped region surrounds the drain.

To achieve the above objective, a preferred embodiment of the present invention provides a high-voltage semiconductor The method of forming the device includes the following steps. First, a substrate is provided, and an insulating structure is formed on the substrate. Next, a drain doped region is formed in the substrate, the drain doped region has a discontinuous bottom surface under the insulating structure, and the drain doped region further includes a first drain doped region and a A second drain doped region, a part of the area of the first drain doped region projected vertically on the substrate overlaps the area of the insulating structure that is projected vertically on the substrate, and the second drain doped region projects vertically on the substrate The area of does not overlap with the area of the insulating structure perpendicularly projected to the substrate. Then, a gate structure is formed on the substrate.

100, 200, 300: High-voltage semiconductor devices

110: Base

130: Gate structure

150: Dip pole

170: Source

160: Drain doped region

161: first drain doped region

162: second drain doped region

163: third drain doped region

180: source doped area

181: first source doped region

182: second source doped region

183: third source doped region

190, 191, 192: insulation structure

230: gate structure

260: Drain doped region

260a: bottom surface

261: first drain doped region

262: second drain doped region

263: The third drain doped region

290: Insulation structure

380: source doped region

380a: bottom surface

381: first source doped region

382: second source doped region

383: third source doped region

390: Insulation structure

400: Mask

410: Dielectric layer

431, 432, 433: plug

a2, a2’: vertical doping range

C: Base current curve of comparative example

C’: Gate current curve of comparative example

d1, d2, d3, d1’, d2’: depth

E1: The base current curve of the first embodiment

E1’: Gate current curve of the first embodiment

g: spacing

w1, w2, w3: width

FIG. 1 is a schematic cross-sectional view of a high-voltage semiconductor device in a comparative embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the high-voltage semiconductor device in the first embodiment of the present invention.

FIG. 3 is a schematic diagram showing the curves of simulated substrate current (Isub) or gate current (Ig) versus gate voltage (Vg) of the high-voltage semiconductor device in the comparative embodiment of the present invention and the first embodiment.

FIGS. 4 to 5 are schematic diagrams showing the stage cross-sectional views of the method of forming the high-voltage semiconductor device in the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of the high-voltage semiconductor device in the second embodiment of the present invention.

In order to enable those who are familiar with the technical field of the present invention to have a better understanding of the present invention, a few preferred embodiments of the present invention are listed below, together with the accompanying drawings, to explain in detail the content of the present invention and what it intends to achieve. The effect.

In the present invention, the description of "the first part is formed on or above the second part" can mean "the first part is in direct contact with the second part", or it can mean "between the first part and the second part" There are other parts", so that the first part and the second part are not in direct contact. In addition, various embodiments of the present invention may use repeated component symbols and/or text annotations. The use of these repeated component symbols and text notes is to make the description more concise and clear, rather than to indicate the association between different embodiments and/or configurations. In addition, for the space-related narrative words mentioned in the present invention, for example: "below", "above", "low", "high", "below", "above" "", "below", "above", "bottom", "top" and similar words, for ease of description, their usage is to describe one component or feature in the diagram with another (or more) component or The relative relationship of features. In addition to the swing outward shown in the diagram, these spatially related words are also used to describe the possible swing directions of the semiconductor device during the manufacturing process, in use, and operation. For example, when the semiconductor device is rotated by 180 degrees, a component that was originally placed "above" other components will become "below" other components. Therefore, as the swing direction of the semiconductor device changes (rotated by 90 degrees or other angles), the space-related narrative used to describe its swing direction should also be interpreted in a corresponding manner.

Although the present invention uses terms such as first, second, and third to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and / Or the block should not be restricted by these words. These terms are only used to distinguish a certain element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and they do not mean or represent the element. Any previous ordinal number does not represent the order of arrangement of a component and another component, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element discussed below, A component, region, layer, or block can also be referred to as a second element, component, region, layer, or block.

The term "about" or "substantially" mentioned in the present invention usually means within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is approximate, that is, the meaning of "approximate" or "substantial" can still be implied when there is no specific description of "approximate" or "substantial".

Please refer to FIG. 1, which shows a schematic cross-sectional view of a high-voltage semiconductor device 100 in a comparative embodiment of the present invention. In the present invention, the high-voltage semiconductor device 100 means that the operating voltage can be higher than 20 volts (V) (for example, 30 volts) semiconductor device. The high-voltage semiconductor device 100 includes a substrate 110, a gate structure 130, a drain electrode 150, a source electrode 170 and at least one insulating structure 190. In one embodiment, the substrate 110 may include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The substrate 110 has, for example, a first conductivity type (for example, P-type), the gate structure 130 is disposed on the substrate 110, and the drain 150 and the source 170 are disposed in the substrate 110 in a horizontal direction (not shown) , For example, in the X direction) are respectively located on two opposite sides of the gate structure 130. In one embodiment, the gate structure 130 may include a polysilicon gate, a metal gate, or a gate structure formed of other suitable materials, and the drain 150 and the source 170 may each have a second conductivity type (For example, N-type) doped region, the second conductivity type (such as N-type) is complementary to the first conductivity type (such as P-type). In another embodiment, the first conductivity type may be N-type, the second conductivity type is P-type, and P-type doped regions are formed as the drain and source to obtain different types of conductivity. High voltage semiconductor device Set.

At least one insulating structure 190 is also disposed on the substrate 110, where the insulating structure 190 is, for example, a field oxide (FOX) layer formed by a local oxidation of silicon (LOCOS) method, as shown in Figure 1. As shown, or, it can also be an insulating unit (such as shallow trench isolation, etc.) manufactured through a deposition process or other suitable processes, but it is not limited to this. In this embodiment, two insulating structures 191 and 192 can be formed on two opposite sides of the gate structure 130, so that the source 170 can be located between the insulating structure 192 and the gate structure 130, and the drain 150 is located between the insulating structure 192 and the gate structure 130. Between the insulating structure 191 and the gate structure 130, but not directly in contact with the insulating structure 191 and/or the gate structure 130, as shown in FIG. However, those with ordinary knowledge in the art should easily understand that the number and positions of the aforementioned insulating structures 190 are only examples, and the specific number and positions of the insulating structures 190 can be further adjusted according to actual component requirements.

The high-voltage semiconductor device 100 further includes a drain doped region 160 and a source doped region 180 disposed in the substrate 100, respectively located below the drain 150 and the source 170. The drain doped region 160 and the source doped region 180 can also be doped regions with the second conductivity type (for example, N-type), and their doping concentration is less than that of the drain 150 and the source 170 . In this embodiment, the drain doped region 160 and the source doped region 180, for example, have a mutually asymmetric structure. For example, along the horizontal direction, the width w1 of the drain doped region 160 is It is larger than the width w2 of the source doped region 180, as shown in Fig. 1. In the configuration of this embodiment, the source doped region 180 is also disposed between the gate structure 130 and the insulating structure 192, so that the sidewalls of the source doped region 180 and the sidewalls of the source 170 can be just cut. The sidewall of the same side of the gate structure 130; and the drain doped region 160 is further from the side of the insulating structure 191 Extending to the bottom of the gate structure 130, the sidewall of the drain 150 or the sidewall of the gate structure 130 will not be aligned with the sidewall. That is, in this embodiment, the drain 150 is located in the drain doped region 160 in the horizontal direction and is surrounded by the drain doped region 160, so that the drain doped region 160 can be used as the high-voltage semiconductor device 100 The drift region (drift region). However, the configuration of the drain doped region 150 and the source doped region 170 is not limited to the foregoing. In another embodiment, the structure of the source doped region and the drain doped region may be mutually Symmetrical, for example, the source doped region and the drain doped region can have the same width in the horizontal direction.

Specifically, the drain doped region 160 may also include a first drain doped region 161, a second drain doped region 162, and a third drain doped region 163 arranged in order from bottom to top. . Among them, the first drain doped region 161, the second drain doped region 162, and the third drain doped region 163 may be doped regions containing the same or different dopants, and the dopants are, for example, phosphorus (P ), arsenic (As) or tellurium (Ti) and other five-valent atoms, but not limited to this. Wherein, the first drain doped region 161 may have a relatively deep depth d1 and a relatively small doping concentration in the substrate 110. The doping concentration is, for example, the number of ions per cubic centimeter is about 5×10 ¹³ to 2.0×10 ¹⁴ (5×10 ¹³ -2.0×10 ¹⁴ ions/cm ³ ), the third drain doped region 163 in the substrate 110 may have a relatively shallow depth d3 and a relatively large doping concentration, for example The number of ions per cubic centimeter is about 3.0×10 ¹⁴ to 9.0×10 ¹⁴ (3.0-9.0×10 ¹⁴ ions/cm ³ ), and the depth d2 and doping concentration of the second drain doped region 162 are respectively Between the depths d1 and d3 of the first drain doped region 161 and the third drain doped region 163 and the doping concentration, the doping concentration is, for example, about 1.0×10 ^{14 ions per cubic centimeter.} To 5.0×10 ¹⁴ (1.0-5.0×10 ¹⁴ ions/cm ³ ), but not limited to this. In one embodiment, the depth d1 of the first drain doped region 161 is, for example, 0.8 micrometer (micrometer, μm) to 1.2 micrometers, and the depth d2 of the second drain doped region 162 is, for example, 0.4 to 0.8 micrometers, and The depth d3 of the third drain doped region 163 is, for example, 0.1 μm to 0.3 μm, but it is not limited thereto. In other words, the overall doping concentration in the drain doped region 160 gradually decreases as the depth in the substrate 110 increases.

On the other hand, the source doped region 180 may also include a first source doped region 181, a second source doped region 182, and a third source doped region 183 arranged in sequence from bottom to top. . Among them, the first source doped region 181, the second source doped region 182, and the third source doped region 183 can also contain doped regions with the same or different dopants, and the dopants can also contain phosphorous. , Arsenic or tellurium and other five-valent atoms. In addition, the depths d1, d2, d3 and doping concentration of the first source doped region 181, the second source doped region 182, and the third source doped region 183 are the same as those of the first drain doped region 161, The depth d1, d2, d3 and doping concentration of the second drain doped region 162 and the third drain doped region 163 are the same, so that in the process of forming the high-voltage semiconductor device 100, the same mask and doping The process forms the source doped region 180 and the drain doped region 160 together, but it is not limited to this.

Therefore, the high-voltage semiconductor device 100 in the comparative embodiment of the present invention uses the doping concentration of the drain doped region 160 to gradually decrease from top to bottom, so that the high-voltage semiconductor device 100 can have sufficient voltage resistance. However, in some cases, the high-voltage semiconductor device 100 is still prone to hot carrier injection problems, so that the substrate current (Isub) passing through the substrate 110 or the gate current (gate current, passing through the gate structure 130) Ig) is too high and has poor component reliability. Generally speaking, although the hot carrier injection problem can be improved by further reducing the overall doping concentration of the drain doped region 160, it may additionally cause the Kirk effect and decrease the breakdown voltage (Vth). It is still not conducive to improving the reliability of the components of the high-voltage semiconductor device 100.

Therefore, a person with ordinary knowledge in the art should easily understand that the high-voltage semiconductor device of the present invention may also have other aspects, which are not limited to the foregoing, on the premise of meeting actual product requirements. The following will further describe other embodiments or variations of the high-voltage semiconductor device. In order to simplify the description, the following description mainly focuses on the differences between the embodiments, and the similarities are not repeated. In addition, the same elements in the various embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the various embodiments.

Please refer to FIG. 2, which shows a schematic cross-sectional view of the high-voltage semiconductor device 200 in the first embodiment of the present invention. The structure of the high-voltage semiconductor device 200 in this embodiment is substantially the same as the embodiment shown in FIG. The content will not be repeated here. The main difference between this embodiment and the aforementioned comparative embodiment is that an insulating structure 290 is additionally provided below the gate structure 230 near the drain 150, so that the drain doped region 260 extends to the insulating structure 290 and the gate structure. The portion under 230 may have a discontinuous bottom surface 260a.

In detail, the insulating structure 290 is also disposed on the substrate 110, which is preferably formed together with the insulating structure 190 and is the same field oxide layer (as shown in FIG. 2) or other suitable insulating units, but not This is limited. In this embodiment, the drain doped region 260 also extends from one side of the insulating structure 191 to below the gate structure 230, so that the drain 150 can be located in the drain doped region 260 in the horizontal direction. And it is surrounded by the drain doped region 260. Among them, the drain 150 of this embodiment does not directly contact the gate structure 230 or the insulating structure 290 under the gate structure 230, and the drain 150 and the insulating structure 290 are part of the drain doped region 260 (that is, part of the The third drain doped region 263) is spaced apart, so that the gap g between the drain 150 and the insulating structure 290 is, for example, about 1 μm to 2.5 μm, preferably It is 1.5 micrometers to 2 micrometers, but not limited to this.

In an embodiment, the drain doped region 260 may further include a first drain doped region 261, a second drain doped region 262, and a third drain doped region 263 arranged in order from bottom to top. In addition, the first drain doped region 261, the second drain doped region 262, and the third drain doped region 263 may also be doped regions containing the same or different dopants, and the dopants may also include phosphorus, Five-valent atoms such as arsenic or tellurium, but not limited to this. The doping concentrations of the first drain doped region 261, the second drain doped region 262, and the third drain doped region 263 are substantially the same as those of the first drain doped region 161 and the second drain doped region 161 in the aforementioned comparative embodiment. The doping concentration of the drain doped region 162 and the third drain doped region 163 are the same, and will not be repeated here. Therefore, the overall doping concentration in the drain doped region 260 of this embodiment also gradually decreases as the depth in the substrate 110 increases. However, in another embodiment, the drain doped region may also include other numbers of doped regions, or be composed of a single doped region whose doping concentration gradually increases from bottom to top.

It should be noted that, in this embodiment, part of the first drain doped region 261 (for example, the part located below the drain 150), and part of the second drain doped region 262 (for example, the bit The portion under the drain 150) and the third drain doped region 263 may substantially have the same as the first drain doped region 161, the second drain doped region 162, and the third drain doped region in the aforementioned comparative embodiment. The depths d1, d2, and d3 of the impurity regions 163 are the same. For example, the depth d1 of the first drain doped region 161 of this part is 0.8 to 1.2 μm, and the depth d2 of the second drain doped region 162 of this part For example, it is 0.4 micrometers to 0.8 micrometers, and the depth d3 of the third drain doped region 163 of this part is, for example, 0.1 micrometers to 0.3 micrometers, but it is not limited thereto. The other part of the first drain doped region 261 (for example, the part under the insulating structure 290) and the other part of the second drain doped region 262 (for example, the part under the insulating structure 290) are respectively With shallower The depth d1’, d2’. At the same time, because of being shielded by the insulating structure 290, the vertical doping range a2' of the second drain doping region 262 located below the insulating structure 290 is significantly smaller than that of the second drain doping region 262 located below the drain 150 The vertical doping range a2 is shown in Figure 2. On the other hand, due to the same shielding by the insulating structure 290, the third drain doped region 263 is only formed under the drain 150 and part of the gate structure 230, but not under the insulating structure 290. Due to the difference in depth or vertical doping range between the portion of the first drain doped region 261 and the second drain doped region 262 under the insulating structure 290 and other portions, the drain doped region 260 The portion under the insulating structure 290 has a relatively shallow depth d1 ′, so that the drain doped region 260 has a discontinuous bottom surface 260 a as a whole, as shown in FIG. 2. In addition, a part of the drain doped region 260 can be disposed under the gate structure 230 (only under the gate structure 230 but not under the insulating structure 290 at the same time), and generally has the aforementioned drain doped region. The same depth d1, d2, d3 and doping range of the impurity region 160 (that is, the bottom surface of the drain doped region 260 located below the gate structure 230 is deeper than the bottom surface of the drain doped region 260 below the insulating structure 290) . In other words, the bottom surface of the drain doped region 260 is not located on the same horizontal plane everywhere, and the bottom surface of the portion adjacent to the insulating structure 290 will have a discontinuous steep rise or fall, so that the drain doped region 260 as a whole It has a discontinuous bottom surface 260a, where the second icon indicates an arrow indicating that the drain-doped region 260 may present a significantly misaligned junction between the portion adjacent to the insulating structure 290 and other portions.

Therefore, the high-voltage semiconductor device 200 in the first embodiment of the present invention can have sufficient withstand voltage due to the gradually decreasing doping concentration of the drain doped region 260 and a discontinuous bottom surface 260a. At the same time, a discontinuous bottom surface 260a at the bottom of the drain doped region 260 can effectively improve the problem of hot carrier injection. Please refer to Figure 3, where the solid curves C and E1 plot the relationship between the gate voltage (Vg, X axis) and the base current (Isub, Y axis). The dashed curves C'and E1' plot the relationship between the gate voltage (X axis) and the gate current (Ig, Y axis). For the high-voltage semiconductor device 200 where the substrate current current value is maximum (about 10 volts), the current indicated by the substrate current curve E1 of the first embodiment is lower than the current indicated by the substrate current curve C of the comparative embodiment. In addition, for the high voltage semiconductor device 200 at the maximum gate current value (at about 30 volts), the current indicated by the gate current curve E1' of the first embodiment is lower than the gate current curve C of the comparative embodiment '. In this way, the high-voltage semiconductor device 200 can indeed have better component reliability.

Please refer to FIG. 4 to FIG. 5, which illustrate a schematic cross-sectional view of stages of a method for forming a high-voltage semiconductor device 200 in an embodiment of the present invention. First, as shown in FIG. 4, a substrate 110 is provided first, and insulating structures 190 and 290 are formed on the substrate 110 at the same time. Next, a mask 400 is formed on the substrate 110 to expose part of the substrate 110 and the insulating structure 290, and at least one doping process is performed through the mask 400 to form a drain doped region 260 and a source in the substrate 110 Doped region 180.

It should be noted that the formation position of the drain doped region 260 is partially overlapped with the insulating structure 290, so that the thickness of the insulating structure 290 will affect the degree of energy penetration during the doping process, thereby affecting the position below the insulating structure 290 The depth and/or vertical doping range of the drain doped region 260. For example, if ion implantation is performed at a higher doping voltage (e.g., 700 to 800 kiloelectron volts, 700-800 KeV), the shielding of the insulating structure 290 will affect the depth of the ion deployment value, so the insulating structure 290 A shallow doped region (for example, the first drain doped region 261 shown in FIG. 2) is formed below. If ion implantation is performed at a relatively low doping voltage (for example, 450 to 550 kiloelectron volts), the shielding of the insulating structure 290 may prevent at least part of the ions from being implanted smoothly, and thus a relatively deep depth is formed under the insulating structure 290. A shallow doped region with a small vertical range (for example, the second drain doped region 262 shown in FIG. 2). As a result, the drain-doped region 260 formed under the insulating structure 290 and the drain-doped region 260 in other parts can present a significantly dislocated junction, and can have a discontinuous bottom surface 260a as a whole. , As shown in Figure 4. In addition, if ion implantation is performed at a lower doping voltage (for example, 100 to 200 kiloelectron volts), the shielding of the insulating structure 290 will even affect the progress of the ion implantation value, and a doped region cannot be formed under the insulating structure 290. (For example, the third drain doped region 263 shown in FIG. 2).

In this embodiment, for example, a first doping process is performed first, for example, ion implantation is performed at an energy of about 700 to 800 kiloelectron volts (keV) (preferably 750 kiloelectron volts) to form a first doping process. The drain doped region 261 and the first source doped region 181, and then a second doping process is performed, for example, for ion implantation at an energy of about 450 to 550 kiloelectron volts (preferably 500 kiloelectron volts). In the process, a second drain doped region 262 and a second source doped region 182 are formed, and finally a third doping process is performed, for example, about 100 to 200 kiloelectron volts (preferably 120 kiloelectron volts) The ion implantation process is performed under energy to form a third drain doped region 263 and a third source doped region 183. Thus, the first drain doped region 261, the second drain doped region 262, and the third drain doped region 263 are sequentially formed to form the drain doped region 260, and at the same time, the first source doped region is formed in sequence. The impurity region 181, the second source doped region 182 and the third source doped region 183 constitute the source doped region 180. However, a person with ordinary knowledge in the art should easily understand that in the actual manufacturing process, the number and sequence of the doping process are not limited to the foregoing, and can be further adjusted according to product requirements. For example, although the foregoing embodiment chooses to operate a doping process with a larger doping energy first to form a deeper doped region, in other embodiments, it is also possible to choose to operate a doping process with a smaller doping energy first. To form a shallow doped region, or perform a single or other number of doping processes to form the drain doped region or The source doped region.

Then, as shown in FIG. 5, a gate structure 230, a drain electrode 150 and a source electrode 170 are sequentially formed. The gate structure 230 is formed on a part of the insulating structure 290 and partially overlaps the drain doped region 260 below. The drain 150 and the source 170 are respectively formed in the drain doped region 260 and the source doped region 180 on both sides of the gate structure 230. As a result, the high-voltage semiconductor device 200 in the aforementioned first embodiment can be formed, and the same component parts in this manufacturing process have been shown and described in the aforementioned Fig. 2 and will not be repeated here. The high-voltage semiconductor device 200 can effectively improve the hot carrier injection problem through a discontinuous bottom surface 260a at the bottom of the drain doped region 260, and avoid a drop in breakdown voltage. Therefore, the forming method of this embodiment is beneficial to obtain a high-voltage semiconductor device with better component reliability. Then, as shown in FIG. 5, at least one dielectric layer 410 and a plurality of plugs 431, 432, and 433 can be formed on the substrate 110 to connect the gate structure 230, the drain 150 and the source 170, respectively. To electrically connect the high-voltage semiconductor device 200 to an external circuit.

It should be noted that although the method for forming the high-voltage semiconductor device in this embodiment is based on the process sequence of forming the drain doped region 260 and the source doped region 180, and then forming the gate structure 230 as an example, the actual process is The above is not limited to this. In another embodiment, after the insulating structure 290 is formed, a gate structure (not shown) that partially covers the insulating structure 290 is formed on the substrate 110 first, and then a mask (not shown) is passed through A drain doped region (not shown) and a source doped region (not shown) are formed. Therefore, the formation of the drain doped region can be double-shielded by the insulating structure 290 and the gate structure, so that the drain doped region can have a more complex discontinuous bottom surface (not shown). In this way, the formed high-voltage semiconductor device should also have the advantages of improving the hot carrier injection problem and avoiding the breakdown voltage drop. Effect. In addition, although the doping range of the aforementioned doped regions (such as the drain doped region 260, the source doped region 180, etc.) is selected to be aligned with the sidewalls of the mask 400 or the components on both sides (such as the insulating structure 190, etc.) It will be described as an implementation mode, but in the actual process, the doping range of each doped region may further diffuse below the components on both sides during the subsequent drive-in process (not shown) ). Therefore, the aforementioned other process aspects should still fall within the scope of the present invention.

Please refer to FIG. 6, which is a schematic cross-sectional view of the high-voltage semiconductor device 300 in the second embodiment of the present invention. The structure of the high-voltage semiconductor device 300 in this embodiment is substantially the same as that of the first embodiment shown in FIG. 2, and the similarities will not be repeated here. The main difference between this embodiment and the aforementioned first embodiment is that the drain doped region 260 and the source doped region 380 of this embodiment may have a mutually symmetrical structure, for example, have the same width.

Specifically, the source doped region 380 is also disposed between the gate structure 230 and the insulating structure 192, and the width w3 of the source doped region 380 is, for example, equal to the width w1 of the drain doped region 260. The source doped region 380 of this embodiment further extends from one side of the insulating structure 192 to below the gate structure 230, so that the source 170 can be located in the source doped region 380 in the horizontal direction and is surrounded by sources. Surrounded by the doped region 380, the source 170 and the insulating structure 390 can be separated by a part of the doped source region 380 (that is, a part of the third doped region 383), so that the source 170 is insulated from the The spacing g between the structures 390 is, for example, about 1 micrometer to 2.5 micrometers, preferably 1.5 micrometers to 2 micrometers, but it is not limited thereto. With this configuration, the source electrode 170 of this embodiment can be used as the drift region of the high-voltage semiconductor device 300 together.

In addition, it should be noted that the gate structure 230 near the source 170 is also An insulating structure 390 is additionally provided, so that the portion of the source doped region 380 extending below the insulating structure 390 and the gate structure 230 may have a discontinuous bottom surface 380a. The manufacturing process and structure of the insulating structure 390 are substantially the same as the insulating structure 290, and will not be repeated here. The source doped region 380 can also include a first source doped region 381, a second source doped region 382, and a third source doped region 383 arranged in sequence from bottom to top, and similar In the drain doped region 260 on the left, part of the source doped region 380 is also shielded by the insulating structure 390 when it is formed, thereby affecting the first source doped region 381 and the second source doped region 382 The depth or doping range of the portion below the insulating structure 390. In this way, the bottom surface of the source doped region 380 is not located on the same horizontal plane everywhere, but a discontinuous steep rise or fall occurs on the part of the bottom surface adjacent to the insulating structure 390, so that the source doped region 380 has A discontinuous bottom surface 360a, as shown in Figure 6. The depths of the first source doped region 381, the second source doped region 382, and the third source doped region 383 below the source 170 are substantially the same as those of the aforementioned first drain doped region 261, second The depths d1, d2, and d3 of the drain doped region 262 and the third drain doped region 263 under the drain 150 are the same, and the first source doped region 381 and the second source doped region 382 are located at The depth of the lower portion of the insulating structure 390 is substantially the same as the depth d1', d2' of the aforementioned first drain doped region 261 and the second drain doped region 262 located below the insulating structure 290, and will not be repeated here.

Therefore, the source 170 and the drain 150 of the high-voltage semiconductor device 300 in this embodiment can be adjusted by the gradually decreasing doping concentration of the source doped region 380 and the drain doped region 260 and its discontinuous The bottom surfaces 380a, 260a have sufficient withstand voltage capability, which can effectively improve the problem of hot carrier injection and avoid the drop in breakdown voltage, thereby obtaining better device reliability.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

110: Base

150: Dip pole

170: Source

180: source doped area

181: first source doped region

182: second source doped region

183: third source doped region

190, 191, 192: insulation structure

200: High-voltage semiconductor device

230: gate structure

260: Drain doped region

260a: bottom surface

261: first drain doped region

262: second drain doped region

263: The third drain doped region

290: Insulation structure

a2, a2’: doping range

d1, d2, d3, d1’, d2’: depth

g: spacing

w1, w2: width

Claims (19)

A high-voltage semiconductor device includes: a substrate; a gate structure disposed on the substrate; a drain disposed in the substrate and located on one side of the gate structure; and a first insulating structure disposed on the substrate On the substrate, the first insulating structure is located under the gate structure and partially overlaps the gate structure; and a drain doped region is disposed in the substrate and is located under the drain and the first insulating structure, And the drain doped region has a discontinuous bottom surface, the drain doped region further includes a first drain doped region and a second drain doped region, the first drain doped region is vertically projected A part of the area of the substrate overlaps the area of the drain and the area of the first insulating structure projected vertically on the substrate, and the area of the second drain doped region projected vertically on the substrate does not overlap with the area of the first insulating structure vertical projection In the area of the substrate, and the second drain doped region surrounds the drain. A high-voltage semiconductor device as described in claim 1, wherein the depth of the drain doped region under the first insulating structure is smaller than the depth of other parts of the drain doped region. A high-voltage semiconductor device according to claim 3, wherein the depth of the first drain doped region in the substrate is greater than the depth of the second drain doped region in the substrate. A high-voltage semiconductor device as described in item 1 of the scope of patent application, which Wherein, the doping concentration of the first drain doping region is less than the doping concentration of the second drain doping region. The high-voltage semiconductor device described in claim 1, wherein a part of the second drain doped region is between the drain and the first insulating structure. A high-voltage semiconductor device as described in item 1 of the scope of patent application, further comprising: a third drain doped region disposed in the substrate, between the first drain doped region and the second drain doped region Between districts. A high-voltage semiconductor device according to item 6 of the scope of patent application, wherein the doping concentration of the third drain doping region is between the doping concentration of the first drain doping region and the second drain doping Between the doping concentration of the miscellaneous region. A high-voltage semiconductor device according to item 6 of the scope of patent application, wherein the third drain doped region is disposed under the drain and the first insulating structure, and the third drain is located under the first insulating structure. The vertical doping range of the drain doping region is smaller than the vertical doping range of the third drain doping region located below the drain. A high-voltage semiconductor device as described in item 1 of the scope of patent application, further comprising: a source electrode disposed in the substrate and located on the other side of the gate structure; and A source doped region is arranged in the substrate and located below the source. A high-voltage semiconductor device as described in item 9 of the scope of patent application, wherein the source doped region is symmetrical to the drain doped region. A high-voltage semiconductor device as described in item 9 of the scope of patent application, wherein the source doped region is asymmetrical to the drain doped region. A high-voltage semiconductor device as described in item 9 of the scope of patent application, further comprising: a second insulating structure disposed on the substrate, and the first insulating structure and the second insulating structure are respectively located on opposite sides of the source. side. A high-voltage semiconductor device as described in item 1 of the scope of patent application, further comprising: a third insulating structure disposed on the substrate, and the first insulating structure and the third insulating structure are respectively located on opposite sides of the drain side. A method for forming a high-voltage semiconductor device includes: providing a substrate; forming an insulating structure on the substrate; forming a drain doped region in the substrate, the drain doped region having a discontinuity under the insulating structure On a bottom surface, the drain doped region further includes a first drain doped region and a second drain doped region, and the first drain doped region is vertically projected on the substrate Part of the area overlaps with the area of the insulating structure projected vertically on the substrate, the area of the second drain doped region projected vertically on the substrate does not overlap with the area of the insulating structure projected on the substrate; and formed on the substrate A gate structure. The method for forming a high-voltage semiconductor device as described in item 14 of the scope of the patent application, wherein the gate structure is formed on a part of the insulating structure. According to the method for forming a high-voltage semiconductor device described in claim 14, wherein the depth of the drain doped region formed under the insulating structure is smaller than the depth of other parts of the drain doped region. The method for forming a high-voltage semiconductor device as described in the scope of patent application, wherein the step of forming the drain doped region includes: performing a doping process, and the doping voltage of the doping process is 700 to 800 kilograms. Electron volt. The method for forming a high-voltage semiconductor device as described in item 14 of the scope of patent application, wherein the vertical doping range of the drain doping region formed under the insulating structure is smaller than the vertical doping range of other parts of the drain doping region Miscellaneous range. The method for forming a high-voltage semiconductor device as described in claim 14 further includes: forming a drain in the drain doped region, and a part of the drain doped region is disposed between the drain and the drain Between insulating structures.

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