TWI632541B - Gate driving module and gate-in-panel - Google Patents

Abstract

A gate driving module and a gate embedded panel include: a first pull-up thin film transistor, one terminal of which is connected to a gate driving signal generator and the other terminal is connected to an end of the first gate line ; The first pull-down thin film transistor, one terminal is connected to the end of the first gate line and the other terminal is connected to a low level voltage terminal; and the second pull-up thin film transistor, one terminal is connected to the The gate drive signal generator and the other terminal are connected to the other end relative to the end of the first gate line, wherein, when the first pull-up thin film transistor and the second pull-up thin film transistor are turned on At this time, the first pull-down thin film transistor is turned off, and when the first pull-up thin film transistor and the second pull-up thin film transistor are turned off, the first pull-down thin film transistor is turned on.

Description

Gate drive module and gate embedded panel

The present invention relates to a gate drive module and a gate embedded panel, in particular to a gate drive that can reduce the number of TFTs by sharing a thin film transistor (TFT), thereby reducing the thickness of the frame A module and a gate embedded panel.

In today's information technology era, technologies related to flat display devices (for example, information contained in electronic signals in the form of visual images) are rapidly developing. In particular, research for developing thinner and lighter flat display devices with lower power consumption is continuing.

Flat display devices include liquid crystal display devices (LCD), plasma display panel devices (PDP), field emission display devices (FED), electroluminescent display devices (ELD), electrowetting display devices (EWD), and organic light-emitting display devices ( OLED).

Among these devices, organic light-emitting display devices generate images by using self-luminous organic light-emitting diodes. Such an organic light-emitting display device includes two or more organic light-emitting diodes that emit light in different colors, so that a colored image can be displayed without using an additional color filter layer like other devices (eg, liquid crystal display devices) . In addition, since the organic light emitting display device does not require an additional light source, the organic light emitting display device can be lighter, thinner, and have a wider viewing angle compared to the liquid crystal display device. In addition, the reaction speed of the organic light-emitting display device is at least a thousand times faster than that of the liquid crystal display device, so that it hardly leaves an afterimage.

Such an organic light-emitting display device turns on the scanning transistor to display an image by applying a voltage to the gate line. When the scanning transistor is turned on, the voltage is applied through the data line to turn on the driving transistor. When the driving transistor is turned on, current flows through the driving transistor to turn on the organic light emitting diode. In order to perform these functions, a gate for applying voltage to the gate line is required Pole drive module.

The conventional gate drive module has a defect that includes a large number of TFTs for driving the gate lines. Therefore, the frame of the gate drive module is thick. In addition, since the traditional gate driver module has a thicker frame, it is difficult for the user to integrate the content displayed on the screen, and the overall volume of the panel is increased. In addition, the current gate drive module has the problem of driving a large number of Q _b nodes and inverters for the gate line.

An object of the present invention is to provide a gate driving module and a gate embedded panel that reduces the number of thin film transistors by sharing the pull-down thin film transistors.

Another object of the present invention is to provide a gate driving module and a gate embedded panel, which reduces the thickness of the frame by reducing the number of thin film transistors.

Another object of the present invention is to provide a gate driving module and a gate embedded panel, which allows the user to have a more integrated visual experience by reducing the thickness of the frame.

Another object of the present invention is to provide a gate driving module and a gate embedded panel, which reduces the overall volume of the panel by reducing the thickness of the frame.

Another object of the present invention is to provide a gate driving module, and one gate embedded panel by a shared node Q _b Q _b to reduce the number of nodes.

Another object of the present invention is to provide a gate driving module and a gate embedded panel that reduces the number of inverters by sharing a Q _b node.

Another object of the present invention is to provide a gate drive module and a gate embedded panel that controls the opening and closing operations of a scanning transistor.

Another object of the present invention is to provide a gate drive module and a gate embedded panel that controls the opening and closing timing of an organic light emitting diode by controlling the opening and closing operations of a scanning transistor.

Another object of the present invention is to provide a gate driving module and a gate embedded panel, which can simultaneously apply a gate driving signal to a first pull-up thin film transistor and a second pull-up thin film transistor Crystal.

Another object of the present invention is to provide a gate driving module and a gate embedded panel that simultaneously apply a gate driving signal to a first pull-up thin film transistor and a second pull-up thin film transistor To reduce the voltage between the voltage signals applied to an active area delay.

According to one aspect of the invention, there is provided a gate driving module which can reduce the number of thin film transistors by sharing the pull-down thin film transistors, and thereby reduce the thickness of the frame.

More specifically, when a first pull-up thin film transistor and a second pull-up thin film transistor are turned on, a first pull-down thin film transistor is turned off. When the first pull-up thin film transistor and the second pull-up thin film transistor are turned off, the first pull-down thin film transistor is turned on. When the first pull-up thin film transistor and the second pull-up thin film transistor are turned on, a gate drive signal is applied to the gate through the first pull-up thin film transistor and the second pull-up thin film transistor Polar line. Then, when the first pull-down thin film transistor is turned on, a low level voltage signal is applied to the gate line through the first pull-down thin film transistor. As described above, only by using the first pull-up thin film transistor, the second pull-up thin film transistor, and the first pull-down thin film transistor, the gate drive signal and the low level voltage signal are applied to This reduces the number of thin film transistors and reduces the thickness of the frame.

The gate driving module may further include: a first inverter whose one terminal is connected to the gate terminal of the first pull-up thin film transistor and the other terminal is connected to the gate terminal of the first pull-down thin film transistor .

A Q _b 3 node connected to the gate terminal of a third pull-up thin film transistor through a third inverter can be connected to a Q _b 2 node. The Q _b 2 node can be connected to the gate terminal of the second pull-up thin film transistor by a second inverter. As described above, the Q _b 3 node is connected to the Q _b 2 node, so that the number of Q _b nodes can be reduced and the number of inverters can be reduced.

Accordingly, the gate driving module can share the pull-down thin film transistor and the Q _b node, thereby reducing the number of thin film transistors, the number of Q _b nodes, and the number of inverters.

According to another aspect of the present description, there is provided a gate embedded panel that can reduce the number of thin film transistors by sharing the pull-down thin film transistors and thereby reduce the thickness of the frame.

More specifically, when the first pull-up thin film transistor and the second pull-up thin film transistor are turned on, the first pull-down thin film transistor is turned off. When the first pull-up thin film transistor and the second pull-up thin film transistor are turned off, the first pull-down thin film transistor is turned on. When the first pull-up thin film transistor and the second pull-up thin film transistor are turned on, a gate drive signal is applied to the gate through the first pull-up thin film transistor and the second pull-up thin film transistor Polar line. Then, when the first pull-down thin film transistor is turned on, a low level voltage signal A crystal is applied to this gate line. As described above, only by using the first pull-up thin film transistor, the second pull-up thin film transistor, and the first pull-down thin film transistor, the gate drive signal and the low level voltage signal are applied to This reduces the number of thin film transistors and reduces the thickness of the frame.

The gate embedded panel may further include: an active area, and a scanning operation is performed in the active area by a gate drive signal applied by the first gate line.

The gate embedded panel may further include: a first inverter, one terminal of which is connected to the gate terminal of the first pull-up thin film transistor and the other terminal is connected to the gate terminal of the first pull-down thin film transistor .

A Q _b 3 node connected to the gate terminal of a third pull-up thin film transistor through a third inverter can be connected to a Q _b 2 node. The Q _b 2 node can be connected to the gate terminal of the second pull-up thin film transistor by a second inverter. As described above, the Q _b 3 node is connected to the Q _b 2 node, so that the number of Q _b nodes can be reduced and the number of inverters can be reduced.

Accordingly, the gate embedded panel can share the pull-down thin film transistor and the Q _b node, thereby reducing the number of thin film transistors, the number of Q _b nodes and the number of inverters.

According to an exemplary embodiment of the present invention, by sharing the pull-down thin film transistors, the number of thin film transistors can be reduced. For example, by reducing the thickness of the bezel to allow the user to have a more integrated visual experience, the gate driving module and the gate embedded panel according to an exemplary embodiment of the present invention can be effectively used. That is, the display device with a thinner bezel provides more screen space, so that when a user watches a movie or a drama, the content displayed on the screen can be integrated.

In addition, according to an exemplary embodiment of the present invention, by reducing the thickness of the frame, the overall volume of the panel can be reduced relative to the screen size. For example, by reducing the overall volume of the panel to reduce excess space, the gate driving module and the gate embedded panel according to an exemplary embodiment of the present invention can be effectively used.

In addition, according to an exemplary embodiment of the present invention, by sharing a Q _b node, the number of Q _b nodes can be reduced. For example, by connecting one Q _b node to another Q _b node to reduce the number of Q _b nodes, the gate driving module and the gate embedded panel according to an exemplary embodiment of the present invention can be effectively used. By sharing a Q _b node, the inverter connected to the Q _b node can also be shared to reduce the thickness of the frame.

In addition, according to an exemplary embodiment of the present invention, the opening and closing operations of a scanning transistor can be controlled. For example, by controlling a pull-up thin film transistor and a pull-down thin film transistor The opening and closing operations of the body control a voltage signal applied to a gate line, and the gate driving module and the gate embedded panel according to an exemplary embodiment of the present invention can be effectively used.

In addition, by controlling the opening and closing operations of the scanning transistor, the opening and closing timing of the organic light emitting diode can be controlled. For example, by turning on or off the organic light emitting diodes in any order, the gate driving module and the gate embedded panel according to an exemplary embodiment of the present invention can be effectively used.

In addition, according to an exemplary embodiment of the present invention, the delay between the voltage signals applied to the active area can be reduced. For example, when the voltage signal applied to the active region is non-uniform to make the timing of turning on and off of the organic light emitting diodes unstable, the gate driving module and gate according to an exemplary embodiment of the present invention Built-in panels can be used effectively.

10‧‧‧ pixel structure

13‧‧‧Data cable

110‧‧‧First pull-up thin film transistor

120‧‧‧First pull-down thin film transistor

130‧‧‧Second pull-up thin film transistor

140‧‧‧First inverter

150‧‧‧ First gate line

160‧‧‧Gate drive signal generator

170‧‧‧Low level voltage terminal

180‧‧‧second inverter

210, 220, 330 ‧‧‧ signal

230‧‧‧Interval

510‧‧‧Third pull-up thin film transistor

520‧‧‧Second pull-down thin film transistor

530‧‧‧The third inverter

540‧‧‧ Fourth pull-up thin film transistor

550‧‧‧Second gate line

560‧‧‧Inverter

1100‧‧‧Active area

CLK1, CLK2, CLK3, CLK4 ‧‧‧ gate drive signals

Cst‧‧‧Capacitance

Dr_Tr‧‧‧Drive transistor

Scan_Tr‧‧‧scan transistor

Vdata‧‧‧Data voltage signal

FIG. 1 is a diagram illustrating a gate driving module according to an exemplary embodiment of the present invention; FIG. 2 (a) is a diagram showing a gate driving signal according to an exemplary embodiment of the present invention; FIG. 2 (b) A diagram showing a voltage signal applied to the gate terminal of the pull-up thin film transistor according to an exemplary embodiment of the present invention; FIG. 2 (c) shows a voltage signal applied to the gate terminal of the pull-down thin film transistor according to the exemplary embodiment of the present invention FIG. 2 (d) is a diagram showing the voltage signal applied to the gate line according to an exemplary embodiment of the present invention; FIG. 3 is an equivalent circuit diagram of a pixel structure according to an exemplary embodiment of the present invention; FIG. 4 A diagram for explaining a gate driving module according to another exemplary embodiment of the present invention; FIG. 5 is a diagram for explaining a gate embedded panel according to an exemplary embodiment of the present invention; and FIG. 6 is a diagram for explaining according to the present invention The pattern of the embedded panel of the gate according to another exemplary embodiment.

The above purpose, features and advantages are clearly explained from the detailed description with reference to the attached drawings. The present invention will explain these embodiments in detail so that those skilled in the art can easily implement the technical idea of the present invention. A description of well-known functions or configurations will be omitted to avoid Avoid unnecessarily obscuring the focus of the invention. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. In these drawings, the same element symbol refers to the same element.

FIG. 1 is a diagram illustrating a gate driving module according to an exemplary embodiment of the present invention. Referring to FIG. 1, a gate driving module according to an exemplary embodiment of the present invention may include: a first pull-up thin film transistor 110; a first pull-down thin film transistor 120; and a second pull-up thin film transistor 130. The gate drive module in FIG. 1 is only an exemplary embodiment of the present invention, and these components are not limited to those shown in FIG. 1. If necessary, other components can be added, or these components can be modified or deleted.

FIG. 2 (a) is a diagram showing a gate driving signal according to an exemplary embodiment of the present invention. FIG. 2 (b) is a diagram showing a voltage signal applied to the gate terminal of the pull-up thin film transistor according to an exemplary embodiment of the present invention.

FIG. 2 (c) is a diagram showing a voltage signal applied to the gate terminal of the pull-down thin film transistor according to an exemplary embodiment of the present invention. FIG. 2 (d) is a diagram showing the voltage signal applied to the gate line according to an exemplary embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of the pixel structure 10 according to an exemplary embodiment of the present invention. Hereinafter, referring to FIGS. 1 to 3, a gate driving module according to an exemplary embodiment of the present invention will be described in detail.

One terminal of the first pull-up thin film transistor 110 may be connected to the gate driving signal generator 160, and the other terminal of the first pull-up thin film transistor 110 may be connected to one end of the first gate line 150. The first pull-up thin film transistor 110 may be a metal oxide semiconductor field effect transistor, a bipolar transistor or an insulating gate bipolar transistor, but the type of the first pull-up thin film transistor 110 is not limited thereto. The gate drive signal generator 160 is an element that generates gate drive signals CLK1, CLK2, CLK3, and CLK4. The gate drive signals CLK1, CLK2, CLK3, CLK4 refer to voltage signals, which are applied to the gate lines to turn on the scan transistor Scan_Tr. For example, the gate driving signals CLK1, CLK2, CLK3, and CLK4 may be clock signals, but not limited thereto.

One terminal of the first pull-down thin film transistor 120 may be connected to the end of the first gate line 150, and the other terminal of the first pull-down thin film transistor 120 may be connected to the low level voltage terminal 170. The low level voltage terminal 170 is a component that provides a DC voltage signal to the source terminal of the first pull-down thin film transistor 120. The low level voltage terminal 170 may be a DC voltage source, but is not limited thereto. First A pull-down thin film transistor 120 may be a metal oxide semiconductor field effect transistor, a bipolar transistor or an insulated gate bipolar transistor, but the type of the first pull-down thin film transistor 120 is not limited thereto.

One terminal of the second pull-up thin film transistor 130 may be connected to the gate driving signal generator 160, and the other terminal of the second pull-up thin film transistor 130 may be connected to the other end of the first gate line 150. The second pull-up thin film transistor 130 may be a metal oxide semiconductor field effect transistor, a bipolar transistor or an insulating gate bipolar transistor, but the type of the second pull-up thin film transistor 130 is not limited thereto. The first pull-up thin film transistor 110, the first pull-down thin film transistor 120, and the second pull-up thin film transistor 130 may be of the same or different types. The positions of the first pull-up thin film transistor 110, the first pull-down thin film transistor 120, and the second pull-up thin film transistor 130 may be the same as or different from those shown in FIG.

For example, when the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned on, the first pull-down thin film transistor 120 is turned off. When the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned off, the first pull-down thin film transistor 120 may be turned on. Referring to FIG. 2 (b), the signal 210 may be applied to the gate terminal of the first pull-up thin film transistor 110. When the signal 210 is applied to the gate terminal of the first pull-up thin film transistor 110, the first pull-up thin film transistor 110 may be turned on at the interval 230.

On the other hand, referring to FIG. 2 (c), the signal 220 may be applied to the gate terminal of the first pull-down thin film transistor 120. The signal 220 may be the reverse signal of the signal 210. When the signal 220 is applied to the gate terminal of the first pull-down thin film transistor 120, the first pull-down thin film transistor 120 may be turned off during the interval 230. The anti-phase signals shown in FIGS. 2 (b) to 2 (c) can be applied to the gate terminals of the first pull-up thin film transistor 110 and the first pull-down thin film transistor 120, So that the thin film transistors are turned on and off simultaneously and separately in a repeating sequence, and vice versa.

For example, the gate driving module may further include a first inverter 140 having a terminal connected to the gate terminal of the first pull-up thin film transistor 110 and a gate terminal connected to the first pull-down thin film transistor 120 Another terminal. The first inverter 140 may reverse the phase of the signal provided to the Q1 node to output it to the Q _b 1 node. For example, the first inverter 140 may change the signal 210 shown in FIG. 2 (b) to the signal 220 shown in FIG. 2 (c) to output and apply it to the first pull-down thin film transistor 120 . When the first inverter 140 changes the signal 210 shown in FIG. 2 (b) to the signal 220 shown in FIG. 2 (c) to output it, the first pull-up thin film transistor 110 and the first lower The thin film transistor 120 can be turned on and off simultaneously and separately in a repeating sequence according to the reverse phase signals 210 and 220 shown in FIGS. 2 (b) to 2 (c).

According to an exemplary embodiment of the present invention, the signal 210 applied to the gate terminal of the first pull-up thin film transistor 110 can be applied to the Q1 node, and the signal 220 applied to the gate terminal of the first pull-down thin film transistor 120 can be applied to Q _b 1 node. The signal 210 applied to the Q1 node may be inverted by an inverter to apply to the gate terminal of the first pull-down thin film transistor 120. These signals may be applied to the gate terminal of the first pull-up thin film transistor 110 and the gate terminal of the first pull-down thin film transistor 120 in a different manner from the above.

However, the second pull-up thin film transistor 130 and the first pull-up thin film transistor 110 may be simultaneously turned on. In particular, the signal 210 shown in FIG. 2 (b) may also be applied to the gate terminal of the second pull-up thin film transistor 130. When the signal 210 is applied to the gate terminals of the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 and the signal 220 is applied to the gate terminals of the first pull-down thin film transistor 120, the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned on and the first pull-down thin film transistor 120 is turned off, and vice versa. By turning on the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 at the same time, a delay between time points can be prevented when the pixel is turned on.

For example, when the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned on and the first pull-down thin film transistor 120 is turned off, the gate driving signal generated by the gate driving signal generator 160 CLK1, CLK2, CLK3, CLK4 can be applied to the first gate line 150 through the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130. In addition, when the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned off and the first pull-down thin film transistor 120 is turned on, the low level voltage signal can pass through the first pull-down thin film transistor 120 It is applied to the first gate line 150. The low-level voltage signal may be a DC voltage signal.

More specifically, when the signal 210 is applied to the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130, the first pull-up thin-film transistor 110 and the second pull-up thin-film transistor 130 are blocked at the interval 230 Open. When the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned on, part of the gate driving signals CLK1, CLK2, CLK3, CLK4 can The pull-up thin film transistor 130 is applied to the first gate line 150. Referring to FIGS. 2 (a) to 2 (d), the gate drive signals CLK1, CLK2, CLK3, and CLK4 can be applied to the first pull-up thin film transistor 110 and the second At least one of the thin film transistors 130 is pulled. When the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned on, the first pull-down thin film transistor 120 may be turned off. After this, the signal 220 may be applied to the gate terminal of the first pull-down thin film transistor 120 to turn it on, and at the same time, the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned off. When the first pull-down thin film transistor 120 is turned on, a low-level voltage signal may be applied to the first gate line 150. When the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned off, the gate driving signals CLK1, CLK2, CLK3, and CLK4 cannot continue to be applied to the first gate line 150. Therefore, the signal 330 shown in FIG. 2 (d) may be applied to the first gate line 150, and the signal 330 may turn on the scan transistor Scan_Tr shown in FIG. 3.

Referring to FIG. 3, when the signal 330 is applied to the first gate line 150, the scan transistor Scan_Tr is turned on. When the scan transistor Scan_Tr is turned on, the data voltage signal Vdata is applied to the data line 13. The device that applies the data voltage signal to the data line 13 may be a data driver. The data voltage signal Vdata applied to the data line 13 is applied to the gate terminal of the capacitor Cst or the driving transistor Dr_Tr by the scan transistor Scan_Tr. When the data voltage signal is applied to the gate terminal of the driving transistor Dr_Tr, the driving transistor Dr_Tr is turned on. When the driving transistor Dr_Tr is turned on, current flows through the driving transistor Dr_Tr. The current flowing through the driving transistor Dr_Tr can turn on the organic light emitting diode.

In the above manner, the gate driving module according to the exemplary embodiment of the present invention can control the on and off operations of the scan transistor Scan_Tr. In addition, by controlling the on and off operations of the scanning transistor Scan_Tr, the on and off timing of the organic light emitting diode can be controlled.

FIG. 4 is a diagram illustrating a gate driving module according to another exemplary embodiment of the present invention. Referring to FIG. 4, the gate driving module according to another exemplary embodiment of the present invention further includes: a third pull-up thin film transistor 510; a second pull-down thin film transistor 520; a fourth pull-up thin film transistor 540; a Q3 node ; And Q _b 3 nodes.

One terminal of the third pull-up thin film transistor 510 may be connected to the gate driving signal generator 160 of the second gate line, and the other terminal of the third pull-up thin film transistor 510 may be connected to the second gate line 550 At the end. The gate driving signal generator of the first gate line may be of the same type or different type from the gate driving signal generator of the second gate line. The third pull-up thin film transistor 510 may be the same as or different from the first pull-up thin film transistor 110. In addition, the third pull-up thin film transistor 510 may be in contact with the above-mentioned first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 the same way to drive.

The Q _b 3 node can be connected to the gate terminal of the second pull-down thin film transistor 520 and can be connected to the gate terminal of the third pull-up thin film transistor 510 by a third inverter 530. The third thin film transistor 510 a pull-up, pull-down structure of the second thin film transistor 520, Q3 node, Q _b 3 nodes, and a third inverter 530, functions, and operations may be similar to those in FIG. 1 similar elements. In addition, the Q _b 3 node can be connected to the Q _b 2 node, and the Q _b 2 node is connected to the gate terminal of the second pull-up thin film transistor 130 through the second inverter 180. The Q _b 3 node may have the same structure and function as the Q _b 1 node described above.

The Q _b 3 node is connected to the Q _b 2 node according to the exemplary embodiment of the present invention, so that the Q _b 3 node can also perform the function of the Q _b 2 node. When the Q _b 3 node performs the function of the Q _b 2 node, the Q _b 2 node may be omitted. In addition, the inverter 530 performs the function of the inverter 180, and therefore, the inverter 180 may be omitted. According to yet another exemplary embodiment of the present invention, by omitting the Q _b 2 node and the inverter 180, the gate driving module can reduce the thickness of the frame.

In FIG. 4, the gate driving module according to another exemplary embodiment of the present invention may further include a fourth pull-up thin film transistor 540 and Q _b 4 node.

One terminal of the fourth pull-up thin film transistor 540 may be connected to the gate driving signal generator 160, and the other terminal of the fourth pull-up thin film transistor 540 may be connected to the other end of the second gate line. The fourth pull-up thin film transistor 540 may be a metal oxide semiconductor field effect transistor, a bipolar transistor or an insulating gate bipolar transistor, but the type of the fourth pull-up thin film transistor 540 is not limited thereto. The positions of the third pull-up thin film transistor 510, the first pull-down thin film transistor 120, and the fourth pull-up thin film transistor 540 may be the same as or different from those shown in FIG. On the other hand, the fourth pull-up thin film transistor 540 and the third pull-up thin film transistor 510 can be turned on simultaneously. More specifically, the signal 210 shown in FIG. 2 (b) may also be applied to the gate terminal of the fourth pull-up thin film transistor 540. When the signal 210 is applied to the gate terminals of the third pull-up thin film transistor 510 and the fourth pull-up thin film transistor 540 and the signal 220 is applied to the gate terminals of the second pull-down thin film transistor 520, the third pull-up thin film transistor 510 And the fourth pull-up thin film transistor 540 is turned on and the second pull-down thin film transistor 520 is turned off, and vice versa. By turning on the third pull-up thin film transistor 510 and the fourth pull-up thin film transistor 540 at the same time, a delay between time points can be prevented when the pixel is turned on.

The gate driving module may further include an inverter 560 having one terminal connected to the gate terminal of the fourth pull-up thin film transistor 540 and the other terminal connected to the Q _b 4 node. The Q _b 4 node can be connected to the Q _b 1 node. The Q _b 4 node may have the same structure and function as the Q _b 3 node described above.

When the Q _b 4 node performs the function of the Q _b 1 node, the Q _b 1 node can be omitted. In addition, the inverter 560 performs the function of the inverter 140, and therefore, the inverter 140 may be omitted.

FIG. 5 is a diagram illustrating a gate embedded panel according to an exemplary embodiment of the present invention. Referring to FIG. 5, the gate embedded panel according to an exemplary embodiment of the present invention may include: a first pull-up thin film transistor 110; a first pull-down thin film transistor 120; a second pull-up thin film transistor 130; and an active region 1100. The gate embedded panel shown in FIG. 5 is only an exemplary embodiment of the present invention, and the components are not limited to the components shown in FIG. 5. If necessary, other components can be added, or these components can be modified or deleted.

One terminal of the first pull-up thin film transistor 110 may be connected to the gate driving signal generator 160 of the first gate line 150, and the other terminal of the first pull-up thin film transistor 110 may be connected to the first gate line One end of 150. The first pull-up thin film transistor 110 may be a metal oxide semiconductor field effect transistor, a bipolar transistor or an insulating gate bipolar transistor, but the type of the first pull-up thin film transistor 110 is not limited thereto. The gate drive signal generator 160 is an element that generates gate drive signals CLK1, CLK2, CLK3, and CLK4. The gate drive signals CLK1, CLK2, CLK3, CLK4 refer to voltage signals, which are applied to the gate lines to turn on the scan transistor Scan_Tr. For example, the gate driving signals CLK1, CLK2, CLK3, and CLK4 may be clock signals, but not limited thereto.

One terminal of the first pull-down thin film transistor 120 may be connected to the end of the first gate line 150, and the other terminal of the first pull-down thin film transistor 120 may be connected to the low level voltage terminal 170. The low level voltage terminal 170 is a component that provides a DC voltage signal to the source terminal of the first pull-down thin film transistor 120. The low level voltage terminal 170 may be a DC voltage source, but is not limited thereto. The first pull-down thin film transistor 120 may be a metal oxide semiconductor field effect transistor, a bipolar transistor, or an insulated gate bipolar transistor, but the type of the first pull-down thin film transistor 120 is not limited thereto.

One terminal of the second pull-up thin film transistor 130 may be connected to the gate driving signal generator 160, and the other terminal of the second pull-up thin film transistor 130 may be connected to the other end of the first gate line 150. The second pull-up thin film transistor 130 may be a metal oxide semiconductor field effect transistor, a bipolar transistor or an insulating gate bipolar transistor, but the second pull-up thin film transistor 130 is The type is not limited to this. The first pull-up thin film transistor 110, the first pull-down thin film transistor 120, and the second pull-up thin film transistor 130 may be of the same or different types. The positions of the first pull-up thin film transistor 110, the first pull-down thin film transistor 120, and the second pull-up thin film transistor 130 may be the same as or different from those shown in FIG.

For example, when the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned on, the first pull-down thin film transistor 120 may be turned off. When the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned off, the first pull-down thin film transistor 120 may be turned on. Referring to FIG. 2 (b), a signal 210 may be applied to the gate terminal of the first pull-up thin film transistor 110. When the signal 210 is applied to the gate terminal of the first pull-up thin film transistor 110, the first pull-up thin film transistor 110 may be turned on at the interval 230.

On the other hand, referring to FIG. 2 (c), the signal 220 may be applied to the gate terminal of the first pull-down thin film transistor 120. When the signal 220 is applied to the gate terminal of the first pull-down thin film transistor 120, the first pull-down thin film transistor 120 may be turned off during the interval 230. Based on the reverse phase signals 210 and 220 shown in Figure 2 (b) and Figure 2 (c), the reverse phase signals shown in Figure 2 (a) to Figure 2 (d) can be applied to the A gate electrode of the pull-up thin film transistor and the first pull-down thin film transistor, so that the thin film transistors are turned on and off simultaneously and separately in a repeating sequence.

For example, the gate driving module may further include a first inverter 140 having a terminal connected to the gate terminal of the first pull-up thin film transistor 110 and a gate terminal connected to the gate terminal of the first pull-down thin film transistor 120 Another terminal. The first inverter 140 may reverse the phase of the signal provided to the Q1 node to output it to the Q _b 1 node. For example, the first inverter 140 may change the signal 210 shown in FIG. 2 (b) to the signal 220 shown in FIG. 2 (c) to output it. When the first inverter 140 changes the signal 210 shown in FIG. 2 (b) to the signal 220 shown in FIG. 2 (c) to output it, the first pull-up thin film transistor 110 and the first lower The thin film transistor 120 is repeatedly turned on and off.

According to an exemplary embodiment of the present invention, the signal 210 applied to the gate terminal of the first pull-up thin film transistor 110 can be applied to the Q1 node, and the signal 220 applied to the gate terminal of the first pull-down thin film transistor 120 can be applied to Q _b 1 node. The signal 210 applied to the gate terminal of the first pull-up thin film transistor 110 can be applied to the Q1 node and inverted by the inverter into the signal 220 and applied to the gate terminal of the first pull-down thin film transistor 120, and vice versa . Therefore, the first pull-up thin film transistor 110 and the first pull-down thin film transistor 120 can be turned on and off simultaneously and separately, and vice versa. These signals may be applied to the gate terminal of the first pull-up thin film transistor 110 and the gate terminal of the first pull-down thin film transistor 120 in a different manner from the above.

On the other hand, the second pull-up thin film transistor 130 and the first pull-up thin film transistor 110 can be turned on simultaneously. In particular, the signal 210 shown in FIG. 2 (b) may also be applied to the gate terminal of the second pull-up thin film transistor 130. When the signal 210 is applied to the gate terminals of the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 and the signal 220 is applied to the gate terminals of the first pull-down thin film transistor 120, the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned on and the first pull-down thin film transistor 120 is turned off, and vice versa. By turning on the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 at the same time, a delay between time points can be prevented when the pixel is turned on.

For example, when the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned on and the first pull-down thin film transistor 120 is turned off, the gate driving signal generated by the gate driving signal generator 160 CLK1, CLK2, CLK3, CLK4 can be applied to the first gate line 150 through the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130. In addition, when the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned off and the first pull-down thin film transistor 120 is turned on, the low level voltage signal can pass through the first pull-down thin film transistor 120 It is applied to the first gate line 150. The low-level voltage signal may be a DC voltage signal.

More specifically, when the signal 210 is applied to the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130, the first pull-up thin-film transistor 110 and the second pull-up thin-film transistor 130 are blocked at the interval 230 Turning on, during this time, the first pull-down thin film transistor 120 may be turned off. When the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned on, part of the gate driving signals CLK1, CLK2, CLK3, CLK4 can The pull-up thin film transistor 130 is applied to the first gate line 150. Referring to FIGS. 2 (a) to 2 (d), the signal CLK1 among the gate drive signals CLK1, CLK2, CLK3, and CLK4 may be applied to the pull-up thin film transistor. After this, the signal 220 may be applied to the gate terminal of the first pull-down thin film transistor 120 to turn it on, and at the same time, the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned off. When the first pull-down thin film transistor 120 is turned on, a low-level voltage signal may be applied to the first gate line 150. When the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned off, the gate driving signals CLK1, CLK2, CLK3, and CLK4 cannot continue to be applied to the first gate line 150. Therefore, the signal 330 shown in FIG. 2 (d) can be Applied to the gate line, and the signal 330 can turn on the scanning transistor Scan_Tr shown in FIG. 3.

In the active area 1100, by applying the gate driving signals CLK1, CLK2, CLK3, and CLK4 through the first gate line 150, part of the operations can be realized. The active area 1100 may include one or more pixel structures 10. Each pixel structure 10 may have the same configuration as the equivalent circuit shown in FIG. 3. The white, red, green, and blue organic light emitting diodes may be arranged in order in the active area 1100. Organic light-emitting diodes with the same color can also be arranged in a row.

The method of driving the active area 1100 will be described with reference to FIGS. 3 to 5. When a signal is applied to the first gate line 150, the scan transistor Scan_Tr is turned on. When the scan transistor Scan_Tr is turned on, the data voltage signal is applied to the data line 13. The device that applies the data voltage signal to the data line 13 may be a data driver. The data voltage signal Vdata applied to the data line 13 is applied to the gate terminal of the capacitor Cst or the driving transistor Dr_Tr by the scan transistor Scan_Tr. When the data voltage signal is applied to the gate terminal of the driving transistor Dr_Tr, the driving transistor Dr_Tr is turned on. When the driving transistor Dr_Tr is turned on, current flows through the driving transistor Dr_Tr. The current flowing through the driving transistor Dr_Tr can turn on the organic light emitting diode.

In the above manner, according to the present description, the gate embedded panel of the exemplary embodiment can control the opening and closing operations of the scan transistor Scan_Tr. In addition, by controlling the opening and closing operations of the scanning transistor Scan_Tr, the opening and closing timing of the organic light emitting diode can be controlled.

FIG. 6 is a diagram illustrating a gate embedded panel according to another exemplary embodiment of the present invention. Referring to FIG. 6, the gate embedded panel according to another exemplary embodiment of the present invention further includes: a third pull-up thin film transistor 510; and a Q _b 3 node.

One terminal of the third pull-up thin film transistor 510 may be connected to the gate driving signal generator 160 of the second gate line, and the other terminal of the third pull-up thin film transistor 510 may be connected to the second gate line One end. The gate driving signal generator of the first gate line may be of the same type or different type from the gate driving signal generator of the second gate line. The third pull-up thin film transistor 510 may be the same as or different from the first pull-up thin film transistor 110. In addition, the third pull-up thin film transistor 510 may be driven in the same manner as the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 described above.

The Q _b 3 node can be connected to the gate terminal of the third pull-up thin film transistor 510 through the third inverter 530. In addition, the node Q _b 3 may be connected to Q _b 2 node, the node Q _b 2 by the second inverter 180 is connected to the second pull-film transistor gate terminal 130. The Q _b 3 node may have the same structure and function as the Q _b 1 node described above.

The Q _b 3 node can be connected to the Q _b 2 node according to the exemplary embodiment of the present invention, so that the Q _b 3 node can also perform the function of the Q _b 2 node. When the Q _b 3 node performs the function of the Q _b 2 node, the Q _b 2 node may be omitted. In addition, the inverter 530 performs the function of the inverter 180, and therefore, the inverter 180 may be omitted. According to another exemplary embodiment of the present invention, by omitting the Q _b 2 node and the inverter 180, the gate embedded panel can reduce the thickness of the frame.

In FIG. 6, the gate embedded panel according to another exemplary embodiment of the present invention may further include a fourth pull-up thin film transistor 540 and Q _b 4 node.

One terminal of the fourth pull-up thin film transistor 540 may be connected to the gate driving signal generator 160, and the other terminal of the fourth pull-up thin film transistor 540 may be connected to the other end of the second gate line. The fourth pull-up thin film transistor 540 may be a metal oxide semiconductor field effect transistor, a bipolar transistor or an insulating gate bipolar transistor, but the type of the fourth pull-up thin film transistor 540 is not limited thereto. The types of the third pull-up thin film transistor 510, the first pull-down thin film transistor 120, and the fourth pull-up thin film transistor 540 may be the same as or different from each other. The positions of the third pull-up thin film transistor 510, the first pull-down thin film transistor 120, and the fourth pull-up thin film transistor 540 may be the same as or different from those shown in FIG.

On the other hand, the fourth pull-up thin film transistor 540 and the third pull-up thin film transistor 510 can be turned on simultaneously. More specifically, the signal 210 shown in FIG. 2 (b) may also be applied to the gate terminal of the fourth pull-up thin film transistor 540. When the signal 210 is applied to the gate terminals of the third pull-up thin film transistor 510 and the fourth pull-up thin film transistor 540 and the signal 220 is applied to the gate terminals of the second pull-down thin film transistor 520, the third pull-up thin film transistor 510 And the fourth pull-up thin film transistor 540 is turned on and the second pull-down thin film transistor 520 is turned off, and vice versa. By turning on the third pull-up thin film transistor 510 and the fourth pull-up thin film transistor 540 at the same time, a delay between time points can be prevented when the pixel is turned on.

The gate driving module may further include an inverter 560 having one terminal connected to the gate terminal of the fourth pull-up thin film transistor 540 and the other terminal connected to the Q _b 4 node. The Q _b 4 node can be connected to the Q _b 1 node. The Q _b 4 node may have the same structure and function as the Q _b 3 node described above.

When the Q _b 4 node performs the function of the Q _b 1 node, the Q _b 1 node can be omitted. In addition, the inverter 560 performs the function of the inverter 140, and therefore, the inverter 140 may be omitted.

According to yet another exemplary embodiment of the present invention, a method of driving a gate includes: turning on a first pull-up thin film transistor and a second pull-up thin film transistor; by the first pull-up thin film transistor and the first Two pull-up thin-film transistors apply a gate drive signal to a first gate line; turn off the first pull-up thin-film transistor and the second pull-up thin-film transistor; turn on a first pull-down thin-film transistor; and A low level voltage signal is applied to the first gate line by the first pull-down thin film transistor.

Initially, the method of the present invention according to the exemplary embodiment starts by turning on the first pull-up thin film transistor and the second pull-up thin film transistor. In order to turn on the first pull-up thin-film transistor and the second pull-up thin-film transistor, the signal shown in FIG. 2 (b) may be applied to the first pull-up thin-film transistor and the second pull-up thin-film transistor The extreme of such gates.

Then, the gate driving signal may be applied to the first gate line through the first pull-up thin film transistor and the second pull-up thin film transistor. The gate drive signal may be the clock signal shown in FIG. 2 (a), but it is not limited thereto.

Then, the first pull-up thin film transistor and the second pull-up thin film transistor are turned off and the first pull-down thin film transistor is turned on. The opening of the first pull-up thin film transistor and the second pull-up thin film transistor and the closing of the first pull-down thin film transistor can be implemented simultaneously.

When the first pull-down thin film transistor is turned on, a low-level voltage signal is applied to the first gate line through the first pull-down thin film transistor. The low-level voltage signal may be a DC voltage signal, but it is not limited thereto. Applying the low level voltage signal to the first gate line through the first pull-down thin film transistor can be implemented on the first gate through the first pull-up thin film transistor and the second pull-up thin film transistor Before applying the gate drive signal to the pole line. In addition, applying the low-level voltage signal to the first gate line by the first pull-down thin film transistor can be implemented by the first pull-up thin film transistor and the second pull-up thin film transistor to the first After applying the gate drive signal to a gate line.

More specifically, when the signal 210 is applied to the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130, the first pull-up thin-film transistor 110 and the second pull-up thin-film transistor 130 are blocked at the interval 230 Open. When the first pull-up thin-film transistor 110 and the second pull-up thin-film transistor 130 are turned on, the gate driving signals CLK1, CLK2, CLK3, CLK4 can pass the first pull-up thin-film transistor 110 and the second pull-up thin film The transistor 130 is applied to the first gate line 150. Next, the signal 220 is applied to the gate terminal of the first pull-down thin film transistor 120 to turn it on At the same time, the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned off. When the first pull-down thin film transistor 120 is turned on, a low-level voltage signal is applied to the first gate line 150. When the first pull-up thin film transistor 110 and the second pull-up thin film transistor 130 are turned off, the gate driving signals CLK1, CLK2, CLK3, and CLK4 cannot continue to be applied to the first gate line 150. Therefore, the signal 330 shown in FIG. 2 (d) is applied to the first gate line 150, and the signal 330 turns on the scan transistor Scan_Tr shown in FIG. 3.

Referring to FIG. 3, when the signal 330 is applied to the first gate line 150, the scan transistor Scan_Tr is turned on. When the scan transistor Scan_Tr is turned on, the data voltage signal is applied to the data line 13. The device that applies the data voltage signal to the data line 13 may be a data driver. The data voltage signal applied to the data line 1 is applied to the gate terminal of the capacitor Cst or the driving transistor Dr_Tr by the scan transistor Scan_Tr. When the data voltage signal is applied to the gate terminal of the driving transistor Dr_Tr, the driving transistor Dr_Tr is turned on. When the driving transistor Dr_Tr is turned on, current flows through the driving transistor Dr_Tr. The current flowing through the driving transistor Dr_Tr can turn on the organic light emitting diode.

According to the above formula, the method according to the exemplary embodiment of the present invention can control the on and off operations of the scan transistor Scan_Tr. In addition, by controlling the on and off operations of the scanning transistor Scan_Tr, the on and off timing of the organic light emitting diode can be controlled.

According to an exemplary embodiment of the present invention, by sharing the pull-down thin film transistors, the number of thin film transistors can be reduced. For example, by reducing the thickness of the bezel to allow the user to have a more integrated visual experience, the gate driving module and the gate embedded panel according to an exemplary embodiment of the present invention can be effectively used. That is, a display device with a thinner bezel provides more screen space, so that when a user watches a movie or a drama, the content displayed on the screen can be integrated.

In addition, according to an exemplary embodiment of the present invention, by reducing the thickness of the frame, the overall volume of the panel can be reduced relative to the screen size. For example, by reducing the overall volume of the panel to reduce excess space, the gate driving module and the gate embedded panel according to an exemplary embodiment of the present invention can be effectively used.

In addition, according to an exemplary embodiment of the present invention, by sharing Q _b nodes, the number of Q _b nodes can be reduced. For example, by connecting one Q _b node to another Q _b node to reduce the number of Q _b nodes, the gate driving module and the gate embedded panel according to an exemplary embodiment of the present invention can be effectively used. By sharing the Q _b node, the inverter connected to the Q _b node can also be shared to reduce the thickness of the frame.

In addition, according to an exemplary embodiment of the present invention, the opening and closing operations of the scan transistor can be controlled. For example, by controlling the on and off operations of the pull-up thin-film transistor and the pull-down thin-film transistor to control the voltage signal applied to the gate line, the gate driving module and gate embedding according to an exemplary embodiment of the present invention The panel can be effectively used.

In addition, by controlling the opening and closing operations of the scanning transistor, the opening and closing timing of the organic light emitting diode can be controlled. For example, by turning on or off the organic light emitting diodes in any order, the gate driving module and the gate embedded panel according to an exemplary embodiment of the present invention can be effectively used.

In addition, according to an exemplary embodiment of the present invention, the delay between the voltage signals applied to the active area can be reduced. For example, when the voltage signal applied to the active area is non-uniform to make the timing of the opening and closing of the organic light emitting diode unstable, the gate driving module and the gate embedded panel according to an exemplary embodiment of the present invention Can be used effectively. Those skilled in the art can make various substitutions, changes, and modifications to the above-mentioned present invention without departing from the scope and spirit of the present invention. Therefore, the present invention is not limited to the above-described exemplary embodiments and the drawings.

Claims (14)

A gate drive module includes: a first pull-up thin film transistor, one terminal of which is connected to a gate drive signal generator and the other terminal of which is connected to an end of a first gate line; a first lower A thin-film transistor, one terminal of which is connected to the end of the first gate line and the other terminal to a low-level voltage terminal; a second pull-up thin-film transistor whose one terminal is connected to the gate drive signal The generator and the other terminal are connected to the other end relative to the end of the first gate line; a third pull-up thin film transistor, one terminal of which is connected to the gate drive signal generator and the other terminal To an end of a second gate line; and a Q _b 3 node, connected to a gate terminal of the third pull-up thin film transistor by a third inverter, wherein, when the first pull-up thin film When the transistor and the second pull-up thin film transistor are turned on, the first pull-down thin film transistor is turned off, and when the first pull-up thin film transistor and the second pull-up thin film transistor are turned off, the The first pull-down thin film transistor is turned on, and , The node Q _b 3 is connected to a Q _b 2 node, the Q _b 2 node is connected to the second pull-film transistor by a second inverter a gate terminal. The gate drive module according to item 1 of the patent application scope, wherein, when the first pull-up thin film transistor and the second pull-up thin film transistor are turned on and the first pull-down thin film transistor is turned off A gate drive signal generated by the gate drive signal generator is applied to the first gate line through the first pull-up thin film transistor and the second pull-up thin film transistor. The gate drive module according to item 2 of the patent application scope, wherein the first gate line is connected to a pixel structure including a data line, a scanning transistor, a capacitor, and a driving circuit Crystal, wherein, when the gate drive signal is applied to the first gate line, the scanning transistor is turned on, and a data voltage is sequentially applied to the data line and the driving transistor by the scanning transistor A gate terminal of the switch to turn on an organic light emitting diode connected to the driving transistor. The gate drive module according to item 1 of the patent application scope, wherein, when the first pull-up thin film transistor and the second pull-up thin film transistor are turned off and the first pull-down thin film transistor is turned on A low-level voltage signal is applied to the first gate line through the first pull-down thin film transistor. The gate drive module according to item 1 of the patent application scope further includes: a first inverter whose one terminal is connected to a gate terminal of the first pull-up thin film transistor and the other terminal is connected to the A gate terminal of the first pull-down thin film transistor. The gate drive module according to item 5 of the patent application scope, wherein the first inverter reverses the signals applied to the first pull-up thin film transistor and the second pull-up thin film transistor, and The inverted signal is output to the first pull-down thin film transistor. A gate embedded panel includes: a first pull-up thin film transistor, one terminal of which is connected to a gate driving signal generator and the other terminal of which is connected to an end of a first gate line; a first lower A thin-film transistor, one terminal of which is connected to the end of the first gate line and the other terminal to a low-level voltage terminal; a second pull-up thin-film transistor whose one terminal is connected to the gate drive signal The generator and the other terminal are connected to the other end relative to the end of the first gate line; an active area generated by the gate drive signal generator and applied by the first gate line A gate drive signal to perform a scanning operation in the active area; a third pull-up thin film transistor, one terminal of which is connected to the gate drive signal generator and the other terminal is connected to a second gate line A terminal; and a Q _b 3 node connected to a gate terminal of the third pull-up thin film transistor by a third inverter, wherein when the first pull-up thin film transistor and the second pull-up When the thin film transistor is turned on, the A pull-down thin film transistor is turned off, and when the first pull-up transistor and the second thin film on the film pull-up transistor is turned off, the first pull-down transistor is turned on, and wherein, the node Q _b 3 Q _b 2 is connected to a node, Q _b 2 node is connected to the second pull-film transistor by a second inverter a gate terminal. The gate embedded panel according to item 7 of the patent application scope, wherein, when the first pull-up thin film transistor and the second pull-up thin film transistor are turned on and the first pull-down thin film transistor is turned off The gate drive signal is applied to the first gate line through the first pull-up thin film transistor and the second pull-up thin film transistor. The gate embedded panel according to item 8 of the patent application scope, wherein the first gate line is connected to a pixel structure, the pixel structure includes a data line, a scanning transistor, a capacitor, and a driving circuit Crystal, wherein, when the gate drive signal is applied to the first gate line, the scanning transistor is turned on, and a data voltage is sequentially applied to the data line and the driving transistor by the scanning transistor A gate terminal of the switch to turn on an organic light emitting diode connected to the driving transistor. The gate embedded panel according to item 7 of the patent application scope, wherein, when the first pull-up thin film transistor and the second pull-up thin film transistor are turned off and the first pull-down thin film transistor is turned on A low-level voltage signal is applied to the first gate line through the first pull-down thin film transistor. The gate embedded panel according to item 7 of the patent application scope further includes: a first inverter, one terminal of which is connected to a gate terminal of the first pull-up thin film transistor and the other terminal is connected to the A gate terminal of the first pull-down thin film transistor. The gate embedded panel according to item 11 of the patent application scope, wherein the first inverter reverses the signals applied to the first pull-up thin film transistor and the second pull-up thin film transistor, and The inverted signal is output to the first pull-down thin film transistor. An organic light-emitting device includes a gate driving module according to item 1 of the patent application scope. An organic light-emitting device includes a gate embedded panel according to item 7 of the patent application scope.