JP2004361942A - Active matrix type display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the variation in the luminance between pixels due to a leak current. <P>SOLUTION: The device 100 comprises a driving control element Tr, a display element 111, a first capacitor C1, a second capacitor C2, a first transistor (TR) Sw 1, a plurality of second TRs Sw 2a and Sw 2b, and a third TR SW 3. The second TRs Sw 2a and Sw 2b are a plurality of field effect transistors of the conduction types equal to each other. The gate of the TR Sw 2a nearest the control electrode side of the driving control element Tr among these TRs is directly connected to a gate control line 140b. The gates of the mutually adjacent TRs Sw 2a and Sw 2b are connected to each other through a first resistor R 1 and the gate of the TR Sw 2b nearest the terminal side of the driving control element Tr is connected through a second resistor R2 to a third power source terminal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an active matrix display device and a driving method thereof.

  In a display device such as an organic EL (electroluminescence) display device in which optical characteristics of a display element are controlled by a drive current flowing through the display device, poor image quality such as uneven brightness due to variation in the drive current occurs. Therefore, when the active matrix driving method is employed in such a display device, it is required that the characteristics of the drive control elements for driving the display elements be substantially the same between the pixels. However, in a display device, since a transistor is usually formed over an insulator such as a glass substrate, variation in transistor characteristics is likely to occur.

  To solve this problem, a threshold cancellation type circuit and a current copy type circuit have been proposed (see Patent Documents 1 and 2). According to these circuits, the influence of the threshold of the drive control element on the drive current can be eliminated. Therefore, even if the threshold value of the drive control element varies between pixels, the influence of such variation on the drive current supplied to the organic EL element can be minimized.

  By the way, in these circuits, the drain and the gate of the drive control element are connected via a correction transistor. The correction transistor is in a conductive state during a writing period for writing a video signal to a pixel in a current copy type circuit, in a reset period or a threshold cancellation period as a preparation period in a threshold cancellation type circuit, and is in a non-conductive state in a light emission period. And

  However, in the circuits described in Patent Literatures 1 and 2, a leakage current easily flows through the correction transistor during the light emission period, and the variation is large. In other words, in these circuits, the gate potential of the drive control element varies greatly during the light emission period, and the variation varies greatly between pixels. Therefore, the organic EL display device using these circuits for the pixels has a problem that the luminance tends to vary among the pixels.

When the correction transistor is turned on and then turned off with respect to the drive control element, a field-through voltage is generated via the gate-source capacitance of the correction transistor. This field-through voltage has large variations among pixels because the threshold value of the correction transistor varies. As a result, there is a problem that the gate potential of the drive control element varies due to the field through voltage.
US Pat. No. 6,229,506 B1 U.S. Patent No. 6,373,454B1

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an active matrix display device in which variation in luminance between pixels due to a leak current is less likely to occur. Another object of the present invention is to provide an active matrix display device and a driving method that can reduce the influence of a field through voltage on a transistor in a pixel.

  The basic idea of the present invention is a configuration in which a plurality of switches are connected in series between a control electrode and an output electrode of a drive control element. Therefore, the potentials of the control terminals of the plurality of switches can be arbitrarily selected, and the operation timings of the plurality of switches can be arbitrarily set. As a result, it is possible to suppress the leakage current and reduce the field through voltage.

  According to a first aspect of the present invention, a drive control including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal for outputting a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal. An element, a display element connected between the second terminal and the second power supply terminal and having an optical characteristic that changes according to the magnitude of the flowing current; and a display element connected between the first terminal and the control terminal. A first capacitor, a second capacitor having one terminal connected to the control terminal, a first switch connected between the other terminal of the second capacitor and a video signal line, A plurality of second switches connected in series between the terminal and the control terminal and having a conduction state controlled by a control signal supplied from a control line, interposed between the second terminal and the display element; And conduction / non-conduction between them A third switch for switching, wherein the plurality of second switches are a plurality of field effect transistors having the same conductivity type, and among the plurality of field effect transistors, the one located closest to the control electrode side is a gate. Are directly connected to the control line, adjacent gates are connected via a first resistor having a gate made of a polysilicon layer, and gates closest to the second terminal are connected to a gate made of a polysilicon layer. An active matrix display device is provided, wherein the active matrix display device is connected to a third power supply terminal via two resistors.

  According to a second aspect of the present invention, a drive control including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal for outputting a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal. An element, a display element connected between the second terminal and the second power supply terminal and having an optical characteristic that changes according to the magnitude of the flowing current; and a display element connected between the first terminal and the control terminal. Connected, a first switch connected between the second terminal and the video signal line, and a control connected in series between the second terminal and the control terminal and supplied from the control line. A plurality of second switches whose conduction state is controlled by a signal, and a third switch that is interposed between the second terminal and the display element and switches conduction / non-conduction between them; Of the second switches have the same conductivity type A plurality of field-effect transistors, among the plurality of field-effect transistors, a gate located closest to the control electrode side has a gate directly connected to the control line, and an adjacent one has a gate formed of a polysilicon layer. An active matrix connected to the third power supply terminal via a second resistor made of a polysilicon layer, the gate being closest to the second terminal side. A type display device is provided.

  According to a third aspect of the present invention, a drive control including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal for outputting a drive current with a magnitude corresponding to a voltage between them. An element, a display element connected between the second terminal and the second power supply terminal and having an optical characteristic that changes according to the magnitude of the flowing current; and a display element connected between the first terminal and the control terminal. A first capacitor, a second capacitor having one terminal connected to the control terminal, a first switch connected between the other terminal of the second capacitor and a video signal line, A plurality of second switches that are connected in series between the terminal and the control terminal and whose conduction state is controlled by control signals supplied from a plurality of control lines independent of each other; Interposed between the display element Both active matrix display device is characterized in that comprising a third switch for switching conduction / non-conduction between them is provided.

  According to a fourth aspect of the present invention, a drive control including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal for outputting a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal. An element, a display element connected between the second terminal and the second power supply terminal and having an optical characteristic that changes according to the magnitude of the flowing current; and a display element connected between the first terminal and the control terminal. And a first switch connected between the second terminal and the video signal line, and a plurality of capacitors connected in series between the second terminal and the control terminal and independent of each other. A plurality of second switches, each of which is in a conductive state controlled by a control signal supplied from a control line, and a third switch that is interposed between the second terminal and the display element and that switches between conduction and non-conduction between them. The switch and Active matrix display device is provided to.

  According to a fifth aspect of the present invention, a drive control including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal for outputting a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal. An element, a display element connected between the second terminal and the second power supply terminal and having an optical characteristic that changes in accordance with the magnitude of the flowing current, and a series connected between the control terminal and the second terminal. A plurality of switches connected to the plurality of switches, the plurality of switches are a plurality of field effect transistors having the same conductivity type, and the gates of the plurality of field effect transistors are connected to the sources of the plurality of field effect transistors. And an active matrix display device which is connected via a semiconductor layer having the same lamination position as the semiconductor layer on which the drain is formed.

  According to a sixth aspect of the present invention, a drive control including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal for outputting a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal. An element, a display element connected between the second terminal and the second power supply terminal and having an optical characteristic that changes in accordance with the magnitude of the flowing current, and a series connected between the control terminal and the second terminal. A plurality of switches connected to the active matrix display device, wherein the plurality of switches are controlled in conduction by control signals supplied from a plurality of control lines independent of each other. Provided.

  According to a seventh aspect of the present invention, a drive control including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal. An element, a display element connected between the second terminal and the second power supply terminal and having an optical characteristic that changes in accordance with the magnitude of the flowing current, and a series connected between the control terminal and the second terminal. A plurality of switches connected to the plurality of switches, wherein the plurality of switches are a plurality of field-effect transistors having the same conductivity type, and the plurality of switches are connected to each other while the plurality of switches are in a non-conductive state. The potential of each connecting part is between the potential of the control terminal and the potential of the second terminal, and when the plurality of switches are three or more switches, the connecting parts are Closer to the control terminal The closer the potential is to the potential of the control terminal and the closer to the second terminal, the closer the potential is to the potential of the second terminal, and the gate potentials of the plurality of switches are the potentials of the control terminal and the second terminal. An active matrix display device is provided in which any one of the potentials is set so as to monotonously decrease from a higher side to a lower side.

  Here, for example, when saying "" A "and" B "have the same lamination position", the meaning is as follows. That is, when a laminate is observed, it means a structure in which “A” and “B” can be simultaneously formed, typically formed into a film, when the laminate is formed. In this case, a structure in which “A” and “B” overlap and a structure in which another component is interposed between “A” and “B” are excluded.

  In the first and second aspects, the third power terminal may be different or the same as the second power terminal.

  In the third and fourth aspects, the plurality of second switches may be a plurality of field effect transistors having the same conductivity type, and the gates of the plurality of field effect transistors may be connected to a plurality of control lines, respectively.

According to an eighth aspect, a drive control element includes a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal. A display element connected between the second terminal and the second power supply terminal and having an optical characteristic that changes according to the magnitude of a flowing current; and a display element connected between the first terminal and the control terminal. A pixel having at least a capacitor, a plurality of switches connected in series between the control terminal and the second terminal, and a plurality of control lines to which control terminals of the plurality of switches are independently connected. A method or apparatus for driving a circuit,
When on / off control of the plurality of switches is performed via the plurality of control lines, a switch closest to the control terminal shifts from an on state to an off state, and subsequently, a switch on the second terminal side turns on. From the off state to the off state, and thereafter, control is performed so that the operation of the switch closest to the control terminal from the off state to the on state is obtained within one horizontal period.

  As described above, according to the present invention, there is provided an active matrix display device in which variation in luminance between pixels is less likely to occur.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each of the drawings, the same or similar components are denoted by the same reference numerals, and redundant description will be omitted. FIG. 1 is a plan view schematically showing an active matrix display device according to a first embodiment of the present invention. FIG. 2 is a timing chart illustrating an example of a driving method of the active matrix display device illustrated in FIG. FIG. 1 illustrates an organic EL display device 100 as an example of the active matrix display device according to the first embodiment.

  The organic EL display device 100 shown in FIG. 1 includes a plurality of pixels 110 (here, M rows × N columns) arranged in a matrix on an insulating support substrate 101 made of glass or the like. On the substrate 101, a driving circuit 120 including a video signal line driving circuit 121 and a scanning signal line driving circuit 122 is provided. The video signal line driving circuit 121 is connected to the video signal lines 130 provided for each column of the pixels 110, and is supplied from various control signals and data signals supplied from a signal supply source (not shown) and a power supply (not shown). A video signal is generated based on the power supply voltage, and the video signal is supplied to each video signal line. On the other hand, the scanning signal line driving circuit 122 is connected to first to third scanning signal lines 140a to 140c provided for each row of the pixels 110, and controls various control signals supplied from a signal supply source (not shown) and The first to third scanning signals are generated based on a power supply voltage supplied from a power supply not to be used. Further, the scanning signal line driving circuit 122 sequentially supplies the first to third scanning signals to the scanning signal lines 140a to 140c, respectively.

  Each pixel 110 includes a display element 111 having a photoactive layer between a pair of electrodes facing each other, and a pixel circuit for driving the display element 111. Here, the display element 111 is an organic EL element including at least an organic light emitting layer as a photoactive layer. For example, organic EL elements that emit red, green, and blue light are arranged on the substrate 101 in a predetermined order. .

  The pixel circuit includes a pixel selection switch Sw1, capacitors C1 and C2, a drive control element Tr, field-effect transistors Sw2a and Sw2b as correction switches, an output control switch Sw3, and resistors R1 and R2. Here, as an example, it is assumed that the drive control element Tr, the correction switches Sw2a and Sw2b, and the output control switch Sw3 are p-channel thin film transistors (TFTs), and the pixel selection switch Sw1 is an n-channel TFT.

  The pixel selection switch Sw1 has an input terminal connected to the video signal line 130, an output terminal connected to one terminal of the capacitor C2, and a control terminal connected to the scanning signal line 140a. The other terminal of the capacitor C2 is connected to a control terminal (gate) of the drive control element Tr.

  A first terminal (source) of the drive control element Tr is connected to a first power supply terminal. The capacitor C1 has one terminal connected to the first terminal (source) of the drive control element Tr and the other terminal connected to the control terminal (gate) of the drive control element Tr. Here, the case where the capacitor C1 is connected between the gate and the source of the drive control element Tr is described as an example, but the point is that one terminal is connected to the control terminal of the drive control element Tr and corresponds to the input signal. The potential difference between the gate and the source is maintained, and the present invention is not limited to this embodiment.

  The input terminal (source) of the output control switch Sw3 is connected to the second terminal (drain) of the drive control element Tr, the output terminal (drain) is connected to one electrode of the display element 111, and the control terminal (gate) is It is connected to the third scanning signal line 140c. The other electrode of the display element 111 is connected to a second power supply terminal. That is, the drive control element Tr, the output control switch Sw3, and the display element 111 are connected in series between the first power supply terminal and the second power supply terminal in this order.

  The correction switches Sw2a and Sw2b are connected in series in this order between the control terminal and the output terminal of the drive control element Tr. Control terminals (gates) of the correction switches Sw2a and Sw2b are connected via a resistor R1. The control terminal of the correction switch Sw2a is connected to the second scanning signal line 140b, and the control terminal of the correction switch Sw2b is connected to the second power supply terminal via the resistor R2.

  The video signal line driving circuit 121 outputs the video signals Data1 to DataN to each video signal line 130.

  The scanning signal line driving circuit 122 generates a first scanning signal Scan (M-m) a from the start signal Starta and the clock signal Clka supplied from the outside shown in FIG. A pulse wave corresponding to the length Tw-Starta is generated and sequentially output to the first scanning signal line 140a. Further, the scanning signal line driving circuit 122 generates a second scanning signal Scan (Mm) b from the pulse wave on the first scanning signal line 140a and the clock signal Clkb supplied from the outside, and performs the second scanning. The signals are sequentially output to the signal line 140b. Further, the scanning signal line driving circuit 122 generates the third scanning signal Scan (Mm) c from the pulse wave of the first scanning signal line 140a and the clock signal Clkc supplied from the outside, and generates the third scanning signal. The data is sequentially output to the line 140c. The above-described scanning signals are sequentially supplied to each pixel circuit via a scanning signal line corresponding to each pixel row.

(Mm) indicates the vertical order of the pixels. M is the maximum pixel prime number in the vertical direction, m = (M−p), and p is 1 to M.

  Next, a driving method of the organic EL display device 100 will be described.

  The first scanning signal Scan (M-m) a supplied from the scanning signal line driving circuit 122 via the scanning signal line 140a has a first level for turning on the pixel selection switch Sw1, here a High level, and It periodically changes between a second level at which the pixel selection switch Sw1 is turned off, here a Low level. The period in which the first scanning signal Scan (M-m) a is at the first level corresponds to the sum of the reset period, the threshold cancellation period, and the signal writing period, and in the effective display period (light emitting period) following the signal writing period. , The first scanning signal Scan (Mm) a is at the second level.

  In the reset period, the scanning signal line driving circuit 122 outputs the second scanning signal Scan (M-m) b of the third level, here the Low level, which makes the correction switches Sw2a and Sw2b conductive, to the scanning signal line 140b. And the third scanning signal Scan (Mm) c of the fifth level, here the Low level, which makes the output control switch Sw3 conductive, is output to the scanning signal line 140c. In the reset period, a reset signal RST is supplied from the video signal line driving circuit 121 to the video signal line 130. Thereby, the gate-source voltage of the drive control element Tr is made higher than its threshold voltage.

  In the threshold cancellation period following the reset period, the signal level of the second scanning signal Scan (M-m) b output from the scanning signal line driving circuit 122 to the scanning signal line 140b is set to a third level, here a Low level, for correction. While the switches Sw2a and Sw2b are in the conductive state, the third scanning signal Scan (Mm) c output to the scanning signal line 140c is changed to the sixth level, in which the output control switch Sw3 is turned off, here the High level. , In the threshold cancellation period, similarly to the reset period, the reset signal RST is supplied from the video signal line driving circuit 121 to the video signal line 130. In this case, the gate-source voltage of the drive control element Tr becomes equal to the threshold voltage, and the capacitor C2 holds the voltage of the difference between the reset potential and the threshold potential.

  In the signal writing period following the threshold cancellation period, the third scanning signal Scan (M-m) c output from the scanning signal line driving circuit 122 to the scanning signal line 140c is set to the sixth level, here the High level, and the output control switch. With Sw3 kept in the non-conductive state, the second scanning signal Scan (M-m) b output to the scanning signal line 140b is set to the fourth level, here the High level, and the correction switches Sw2a and Sw2b are made non-conductive. . In the signal writing period, the video signal line driving circuit 121 supplies video signals Data1 to DataN to the video signal line 130, respectively. As a result, the gate potential of the drive control element Tr fluctuates according to the potential difference between the video signal Data (N−n) and the reset signal RST.

  In the effective display period (light emission period) following the signal writing period, the first scanning signal Scan (Mm) a output from the scanning signal line driving circuit 122 to the scanning signal line 140a is set to the second level, here, the Low level. , The pixel selection switch Sw1 is turned off. In the effective display period, the second scanning signal Scan (Mm) b output from the scanning signal line driving circuit 122 to the scanning signal line 140b is set to a fourth level, here, a High level, and the correction switches Sw2a and Sw2b are set. The third scanning signal Scan (Mm) c output to the scanning signal line 140c is set to the fifth level, here the Low level, and the output control switch Sw3 is set to the non-conductive state. As a result, a drive current corresponding to the video signal Data (N−n) flows through the display element 111, and the light emitting operation starts. Note that a period in which the third scanning signal Scan (Mm) c is at the fifth level corresponds to an effective display period (light emitting period).

  In this way, even if the threshold value of the drive control element Tr varies between the pixels 110, it is possible to eliminate the influence of such variation on the luminance. Therefore, excellent display quality can be realized.

  By the way, in the present embodiment, the correction switch is composed of a plurality of field effect transistors Sw2a and Sw2b. Therefore, it is possible to suppress the flow of the leak current at the time of off.

  Moreover, in the present embodiment, the gates of the transistors Sw2a and Sw2b are connected via the resistor R1. The gate of the transistor Sw2a is directly connected to the second scanning signal line 140b, and the gate of the transistor Sw2b is connected to the second power supply terminal via the resistor R2.

  According to such a configuration, the gate potential of the transistor Sw2a and the gate potential of the transistor Sw2b can be made different, and as a result, the following effects can be obtained.

  For example, when the gate-source voltage Vgs is higher than the threshold voltage Vth, the p-channel field-effect transistor ideally becomes almost completely non-conductive regardless of the level of the gate-source voltage Vgs. It is a target. However, in a general p-channel transistor, when the gate-source voltage Vgs is excessively higher than the threshold voltage Vth, there is a tendency that the non-conductive state approaches the conductive state.

  In the effective display period, the potential of the connection portion between the transistor Sw2a and the transistor Sw2b which is turned off is between the potential of the gate and the potential of the drain of the drive control element Tr. For example, in the effective display period, when the gate potential of the drive control element Tr is about 8 V and the drain potential of the drive control element Tr is about 3 V, the potential of the connection between the transistor Sw2a and the transistor Sw2b is about 5V. .

  Therefore, when the gate potential of the transistor Sw2a and the gate potential of the transistor Sw2b are equal, the gate-source voltage Vgs of the transistor Sw2a and the gate-source voltage Vgs of the transistor Sw2b are different. Therefore, in the effective display period, when the gate potential is set to realize the optimum non-conductive state in one of the transistors Sw2a and Sw2b, the other cannot realize the optimum non-conductive state. That is, the effect of suppressing the leakage current expected by adopting the structure in which the plurality of transistors Sw2a and Sw2b are connected in series to the correction switch cannot be sufficiently obtained.

  On the other hand, according to the present embodiment, the gate potential of the transistor Sw2a and the gate potential of the transistor Sw2b can be made different. For example, in the effective display period, when the potential of the second scanning signal supplied to the second scanning signal line 140b is 10 V and the potential of the second power supply terminal is 0 V, the resistance values of the resistors R1 and R2 are set to 1 GΩ, respectively. Assuming 9 GΩ, the gate potentials of the transistors Sw2a and Sw2b can be set to 10V and 9V, respectively. Therefore, during the effective display period, the gate-source voltage Vgs of the transistor Sw2a and the gate-source voltage Vgs of the transistor Sw2b can be made substantially equal, and an optimum non-conductive state is realized in both the transistors Sw2a and Sw2b. be able to. Therefore, according to the present embodiment, an extremely high leakage current suppressing effect can be obtained. That is, according to the present embodiment, even if the characteristics of the drive control element Tr vary among the pixels 110, the influence of such variation on the drive current supplied to the display element 111 can be minimized, In addition, it is possible to suppress a variation in luminance between the pixels 110 due to a leak current.

  Note that the resistor R2 is not necessarily provided, but if the resistor R2 is provided, the gate potentials of the transistors Sw2a and Sw2b can be easily set, and current consumption can be suppressed. For example, the current flowing between the second scanning signal line 140b and the second power supply terminal during the effective display period can be set to 5 nA or less. Also, typically, a resistor having a larger resistance value than the resistor R1 is used as the resistor R2.

  The above-described resistors R1 and R2 are provided in the fine pixel 110. Therefore, in the present embodiment, the following structure is adopted for the resistors R1 and R2.

  FIG. 3 is a plan view schematically showing an example of a structure that can be employed in the active matrix display device of FIG. In FIG. 3, reference numerals 14 and 15 indicate wirings made of metal, alloy, or the like, reference numerals 22a and 22b indicate gates of the transistors Sw2a and Sw2b extending from the wiring 14, and reference numeral 21 indicates a transistor Sw2a or Sw2b. 1 shows a semiconductor layer made of polysilicon or the like on which a source, a drain, and a channel region are formed. In FIG. 3, a gate insulating film and the like interposed between the gates 22a and 22b and the semiconductor layer 21 are omitted.

  In the structure shown in FIG. 3, a polysilicon layer doped with a small amount of impurities is used as the resistors R1 and R2. The resistance values of the resistors R1 and R2 can be freely set according to the concentration of the impurity added to the polysilicon layer, the dimensions of the polysilicon layer, and the like. The polysilicon layer and the semiconductor layers 21 of the transistors Sw2a and Sw2b can be simultaneously formed and patterned.

  Next, a second embodiment of the present invention will be described.

  The active matrix display device according to the first embodiment is of a type in which video signals Data1 to DataN are written as voltage signals. On the other hand, in the second embodiment, the video signals Data1 to DataN are written as current signals.

  FIG. 4 is an equivalent circuit diagram schematically illustrating an example of a structure that can be employed in the active matrix display device according to the second embodiment of the present invention.

  The operation of the pixel 110 shown in FIG. 4 will be described. First, with the output control switch Sw3 opened (OFF), the pixel selection switch Sw1 and the correction switches Sw2a and Sw2b are closed (ON), and the drive control element Tr is turned on. A current I of a magnitude corresponding to the video signal Data (N-n) is passed. At this time, since the drive control element Tr is diode-connected by the correction switches Sw2a and Sw2b, the potential difference between both ends of the capacitor C1 is the gate-source voltage of the drive control element Tr through which the current I flows. Thereafter, the pixel selection switch Sw1 and the correction switches Sw2a and Sw2b are opened (OFF), and the gate-source voltage determined by the input signal is held in the capacitor C1.

  Next, the output control switch Sw3 is closed (ON), and the display element 111 is connected to the drain of the drive control element Tr. As a result, a current having a magnitude substantially equal to the current I flows through the display element 111, and the light emitting operation starts.

  Also in the present embodiment, the correction switch is composed of a plurality of field effect transistors Sw2a and Sw2b, and the gates of the transistors Sw2a and Sw2b are connected via a resistor R1. Further, the gate of the transistor Sw2a is directly connected to the second scanning signal line 140b, and the gate of the transistor Sw2b is connected to the second power supply terminal via the resistor R2. Therefore, the same effect as that described in the first embodiment can be obtained.

  Although the first and second scanning signal lines 140a and 140b are provided in FIG. 4, if the gate of the transistor Sw2a is connected to the first scanning signal line 140a, the second scanning signal line 140b can be omitted. it can.

  In the above embodiment, the case where polysilicon is used for forming the semiconductor layer and the resistor of the transistor has been described, but amorphous silicon may be used.

  In the first and second embodiments, the resistor R2 is connected to the second power supply terminal. However, the connection destination of the resistor R2 may not be the second power supply terminal. That is, the resistor R2 may be connected to a third power supply terminal provided independently of the first and second power supply terminals.

Next, a third embodiment of the present invention will be described.
In the first and second embodiments, the leakage current is suppressed by making the gate potentials of the transistors Sw2a and Sw2b different using the resistor R1. On the other hand, in the third embodiment, the leakage current is suppressed by connecting the gates of the transistors Sw2a and Sw2b to different scanning signal lines.

  FIG. 5 is a plan view schematically showing an active matrix display device according to the third embodiment of the present invention. FIG. 6 is a timing chart illustrating an example of a method for driving the active matrix display device illustrated in FIG. FIG. 5 illustrates an organic EL display device 100 as an example of the active matrix display device according to the third embodiment.

  The organic EL display device 100 shown in FIG. 5 is different from the organic EL display device shown in FIG. 1 in that a scanning signal line for driving the gate of the correction switch is added and the pixel 110 and the scanning signal line driving circuit 122 adopt the following configuration. It has the same structure as the EL display device 100.

  That is, in the organic EL display device 100 shown in FIG. 5, the pixel 110 includes a display element 111 and a pixel circuit that drives the display element 111. The pixel circuit includes a pixel selection switch Sw1, capacitors C1 and C2, a drive control element Tr, field-effect transistors Sw2a and Sw2b serving as correction switches, and an output control switch Sw3. Here, as an example, it is assumed that the drive control element Tr, the correction switches Sw2a and Sw2b, and the output control switch Sw3 are p-channel thin film transistors (TFTs), and the pixel selection switch Sw1 is an n-channel TFT.

  The pixel selection switch Sw1 has an input terminal connected to the video signal line 130, an output terminal connected to one terminal of the capacitor C2, and a control terminal connected to the scanning signal line 140a. The other terminal of the capacitor C2 is connected to a control terminal (gate) of the drive control element Tr.

  A first terminal (source) of the drive control element Tr is connected to a first power supply terminal. The capacitor C1 has one terminal connected to the first terminal of the drive control element Tr and the other terminal connected to the control terminal of the drive control element Tr.

  The input terminal (source) of the output control switch Sw3 is connected to the second terminal (drain) of the drive control element Tr, the output terminal (drain) is connected to one electrode of the display element 111, and the control terminal (gate) is It is connected to the fourth scanning signal line 140d. The other electrode of the display element 111 is connected to a second power supply terminal. That is, the drive control element Tr, the output control switch Sw3, and the display element 111 are connected in series between the first power supply terminal and the second power supply terminal in this order.

  The correction switches Sw2a and Sw2b are connected in series in this order between the control terminal and the output terminal of the drive control element Tr. The control terminal (gate) of the correction switch Sw2a is connected to the second scanning signal line 140b, and the control terminal (gate) of the correction switch Sw2b is connected to the second scanning signal line 140c.

  From the start signal Starta and the clock signal Clka supplied from the outside, the scanning signal line driving circuit 122 generates a first scanning signal Scan (Mm) a having a pulse width Tw-Starta having a length of one horizontal scanning period. A corresponding pulse wave is generated and sequentially output to the first scanning signal line 140a. Further, the scanning signal line driving circuit 122 generates a second scanning signal Scan (Mm) b from the pulse wave on the first scanning signal line 140a and the clock signal Clkb supplied from the outside, and performs the second scanning. The signals are sequentially output to the signal line 140b. Further, the scanning signal line driving circuit 122 generates the third scanning signal Scan (Mm) c from the pulse wave on the first scanning signal line 140a and the clock signal Clkc supplied from the outside, and performs the third scanning. Output to the signal line 140c. In addition, the scanning signal line driving circuit 122 generates the fourth scanning signal Scan (M-m) d from the pulse wave on the first scanning signal line 140a and the clock signal Clkd supplied from the outside, and The signals are sequentially output to the scanning signal line 140d. The above scanning signals are sequentially supplied to each pixel circuit via a scanning line corresponding to each pixel row.

  Next, a driving method of the organic EL display device 100 will be described.

  The first scanning signal Scan (M-m) a supplied from the scanning signal line driving circuit 122 via the scanning signal line 140a has a first level for turning on the pixel selection switch Sw1, here a High level, and It periodically changes between a second level at which the pixel selection switch Sw1 is turned off, here a Low level. The period during which the first scanning signal Scan (Mm) a is at the first level is substantially equal to the sum of the reset period, the threshold cancellation period, and the signal writing period, and in the effective display period (light emission period) following the signal writing period. The first scanning signal Scan (Mm) a becomes the second level.

  In the reset period, the scanning signal line driving circuit 122 outputs a second scanning signal Scan (M-m) b of a third level, here a Low level, which makes the correction switch Sw2a conductive, to the scanning signal line 140b. At the same time, the third scanning signal Scan (M-m) c at the fifth level, here the Low level, which makes the correction switch Sw2b conductive, is output to the scanning signal line 140c. Further, during the reset period, the fourth scanning signal Scan (Mm) d at the seventh level, here the Low level, which makes the output control switch Sw3 conductive, is output to the scanning signal line 140d. Further, in the reset period, a reset signal RST is supplied from the video signal line driving circuit 121 to the video signal line 130. Thereby, the gate-source voltage of the drive control element Tr is made higher than its threshold voltage.

  In the threshold cancellation period following the reset period, the signal level of the second scanning signal Scan (M-m) b output from the scanning signal line driving circuit 122 to the scanning signal line 140b is set to a third level, here, a Low level. The correction switch Sw2a is turned on, and the signal level of the third scanning signal Scan (Mm) c output to the scanning signal line 140c is set to the fifth level, here, the Low level, and the correction switch Sw2b is turned on. And keep it. However, in the threshold cancellation period, the fourth scanning signal Scan (Mm) d output to the scanning signal line 140d is set to the eighth level and the High level at which the output control switch Sw3 is turned off. In the threshold cancel period, the reset signal RST is supplied from the video signal line driving circuit 121 to the video signal line 130, as in the reset period. In this case, the gate-source voltage of the drive control element Tr becomes equal to the threshold voltage, and the capacitor C2 holds the voltage of the difference between the reset potential and the threshold potential.

  In the signal writing period following the threshold canceling period, the fourth scanning signal Scan (Mm) d output from the scanning signal line driving circuit 122 to the scanning signal line 140d is controlled to the eighth level, here the High level. Switch Sw3 is turned off. However, in the signal writing period, the second scanning signal Scan (Mm) b output to the scanning signal line 140b is set to the fourth level, here the High level, so that the correction switch Sw2a is turned off and the scanning signal is turned off. The third scanning signal Scan (M-m) c output to the line 140c is set to the sixth level, here the High level, and the correction switch Sw2b is turned off. In the signal writing period, the video signal line driving circuit 121 supplies video signals Data1 to DataN to the video signal line 130, respectively. As a result, the gate potential of the drive control element Tr fluctuates according to the potential difference between the video signal Data (N−n) and the reset signal RST.

  In the effective display period (light emission period) following the signal writing period, the first scanning signal Scan (Mm) a output from the scanning signal line driving circuit 122 to the scanning signal line 140a is set to the second level, here, the Low level. , The pixel selection switch Sw1 is turned off. In the effective display period, the second scanning signal Scan (Mm) b output from the scanning signal line driving circuit 122 to the scanning signal line 140b is set to the fourth level, here, the High level, and the correction switch Sw2a is turned off. State, the third scanning signal Scan (M-m) c output to the scanning signal line 140c is set to the sixth level, here the High level, and the correction switch Sw2b is turned off, and the third scanning signal Scan (Mm) c is output to the scanning signal line 140d. The four-scanning signal Scan (Mm) d is set to the seventh level, here the Low level, and the output control switch Sw3 is turned on. As a result, a drive current corresponding to the video signal Data (N−n) flows through the display element 111, and the light emitting operation starts. A period in which the output control switch Sw3 is turned on by the fourth scanning signal Scan (Mm) d corresponds to an effective display period (light emission period).

  In this way, even if the threshold value of the drive control element Tr varies between the pixels 110, it is possible to eliminate the influence of such variation on the luminance. Therefore, excellent display quality can be realized.

  Also in the present embodiment, the correction switch is configured by a plurality of field effect transistors Sw2a and Sw2b. Therefore, leakage current can be suppressed.

  Moreover, in the present embodiment, since the gates of the transistors Sw2a and Sw2b are connected to the scanning signal lines 140b and 140c, which are separate wirings, the gate potentials of the transistors Sw2a and Sw2b can be controlled independently of each other. it can. Therefore, in the effective display period, the gate-source voltage Vgs of the transistor Sw2a and the gate-source voltage Vgs of the transistor Sw2b can be made substantially equal, and an optimal non-conductive state is realized in both the transistors Sw2a and Sw2b. can do.

  Therefore, according to the present embodiment, an extremely high leakage current suppressing effect can be obtained. That is, according to the present embodiment, even if the characteristics of the drive control element Tr vary among the pixels 110, the influence of such variation on the drive current supplied to the display element 111 can be minimized, In addition, it is possible to suppress a variation in luminance between the pixels 110 due to a leak current.

  In the present embodiment, since the gates of the transistors Sw2a and Sw2b are connected to the scanning signal lines 140b and 140c, respectively, the transistors Sw2a and Sw2b can be operated at different timings. Therefore, for example, as shown in FIG. 6, when shifting from the threshold cancellation period to the signal writing period, if the operation of turning off the transistor Sw2a precedes the operation of turning off the transistor Sw2b, the transistor Variations in the gate potential of the drive control element Tr due to switching noise generated when the switch Sw2b switches from the conductive state to the non-conductive state can be suppressed.

  Next, a fourth embodiment of the present invention will be described.

  FIG. 7 is an equivalent circuit diagram schematically illustrating an example of a structure that can be employed in the active matrix display device according to the fourth embodiment of the present invention. The active matrix display device according to the third embodiment is of a type in which video signals Data1 to DataN are written as voltage signals. On the other hand, in the fourth embodiment, as described in the second embodiment, the video signals Data1 to DataN are written as current signals.

  Also in the present embodiment, the correction switch is configured by a plurality of field effect transistors Sw2a and Sw2b, and the gates of the transistors Sw2a and Sw2b are connected to the scanning signal lines 140b and 140c, respectively. Therefore, the same effect as that described in the third embodiment can be obtained.

  Although the first and second scanning signal lines 140a to 140c are provided in FIG. 7, if the gate of the transistor Sw2a is connected to the first scanning signal line 140a, the second scanning signal line 140b can be omitted. it can. Alternatively, if the gate of the transistor Sw2b is connected to the first scanning signal line 140a, the third scanning signal line 140c can be omitted.

  In the first to fourth embodiments described above, the correction switch is composed of two transistors Sw2a and Sw2b connected in series. However, the correction switch is composed of three or more transistors connected in series. You may.

  Further, the case where polysilicon is used as a semiconductor layer included in the transistor is described; however, the present invention is not limited to this, and amorphous silicon may be used for the semiconductor layer. However, in the case where amorphous silicon is used, there is a possibility that the formation area of the pixel circuit is increased. Therefore, it is preferable to combine the top emission method with the display surface on the side opposite to the substrate on which the pixel circuit is formed. .

  Next, a fifth embodiment of the present invention will be described.

  FIG. 8 is a timing chart showing another embodiment of the driving method of the active matrix display device shown in FIG. The waveforms of the clock signal Clkb and the scanning signals Scan1b and Scan2b are different from the waveform shown in the timing chart of FIG. That is, when the plurality of correction switches Sw2a and SW2b are on / off controlled via the plurality of control lines (scanning lines), the correction switch Sw2a on the side closest to the control terminal (gate) of the drive control element Tr is turned on. After that, the correction switch Sw2b on the second terminal (drain) side is shifted from the on state to the off state, and thereafter, the control terminal (gate) within one horizontal period or several horizontal periods. Is changed from the off state to the on state.

It is now assumed that there is no correction switch Sw2a and only the correction switch Sw2b is connected between the gate and the drain of the drive control element Tr. Then, when the correction switch Sw2b changes from on to off after the threshold value cancel operation, a field-through voltage is generated via the gate-source capacitance of the correction switch Sw2b. The field through voltage (ΔVp) is
ΔVp = {Cgsall / (Cgsall + Cs)} × | Vgson−Vth |
+ {Cgsovl / (Cgsovl + Cs)} × ｜ Vth − Vgsoff ｜
… (1)
It becomes. Cgsall is the capacitance between the gate and source of Sw2b, Cgsovl is the parasitic capacitance between the gate and source, Cs is the storage capacitance, Vgson is the on-potential of the gate control signal, Vgsoff is the off-potential of the gate control signal, and Vth is the correction switch. This is the threshold value of Sw2b.

  This field-through voltage has large variations among pixels because the threshold value of the correction switch varies. As a result, there is a problem that the gate potential of the drive control element varies due to the field through voltage. Therefore, in the present invention, a series circuit of the correction switch Sw2a and the correction switch Sw2b is provided, and the control is performed at the timing shown in FIG. 8 (see the scan waveforms Scan1b and Scan1c). Then, before the correction switch Sw2b is turned off, the transistor Sw2a is turned off from the on state first, and subsequently, the correction switch Sw2b is turned off from the on state. Thus, the field through voltage (ΔVp) when the correction switch Sw2b is turned off does not affect the gate of the drive control element Tr. However, the field-through voltage resulting from the turning-off of the correction switch Sw2a first from the on-state remains at the gate of the drive control element Tr. Therefore, by turning on the correction switch Sw2a after the correction switch Sw2b is turned off as shown in FIG. 8, at least the field-through voltage generated by the operation of the transistor Sw2a is suppressed.

  As a result, the field through voltage (ΔVp) when the correction switch Sw2b is turned off can be suppressed.

Therefore, fluctuations in the gate potential of the drive control element Tr can be reduced.

  In the timing chart of FIG. 8, the transistor Sw2a shifts from the on state to the off state, the transistor Sw2b on the second terminal (drain) side shifts from the on state to the off state, and thereafter, within one horizontal period. 5 shows an operation in which the transistor Sw2a closest to the control terminal (gate) shifts from the off state to the on state. However, the period from when the transistor Sw2a shifts from the on-state to the off-state until the transistor Sw2a turns on next may be within several horizontal cycles. Means for obtaining these operations are realized by the control circuit 200 and the drive circuit 120.

  The present invention can be similarly applied to an active matrix display device using the circuit shown in FIG. 7 for each pixel. In this case, prior to turning off the correction switch Sw2b at the end of the writing period, the switch Sw2b is turned off, and then the switch Sw2a is turned on. Variations in the gate potential of the drive control element due to the influence of the generated feedthrough voltage can be suppressed.

  FIG. 9 shows still another embodiment of the present invention. FIG. 7 illustrates the case where the gates of the pixel selection switch Sw1 and the correction switches Sw2a and Sw2b are connected to independent scanning signal lines, respectively. In the present embodiment, the pixel selection switch Sw1 and the correction switch Sw2b are connected. The case where the common switch is connected to the common scan signal line (140a) and the correction switch Sw2a and the correction switch Sw2b are connected to different scan signal lines will be described.

  FIG. 10 is a timing chart illustrating an example of a method for driving the active matrix display device illustrated in FIG. The scanning signal line drive circuit 122 generates a pulse wave corresponding to the length Tw-Starta of one horizontal period from a start signal Starta and a clock signal Clka supplied from the outside. Then, this pulse wave is sequentially output to the third scanning signal line 140c as the third scanning signal Scan (Mm) c. Further, the scanning signal line driving circuit 122 generates a second scanning signal Scan (Mm) b from the pulse wave and the clock signal Clkb supplied from the outside, and sequentially outputs the second scanning signal Scan (Mm) b to the second scanning signal line 140b. .

Further, the scanning signal line driving circuit 122 generates a first scanning signal Scan (M-m) a from the pulse wave and a clock signal Clkc supplied from the outside, and sequentially outputs the first scanning signal Scan (M-m) to the first scanning signal line 140a. .

  The first scanning signal Scan (M-m) a is supplied to the gates of the pixel selection switch Sw1 and the correction switch Sw2b via the first scanning signal line 140a, and the second scanning signal Scan (M-m) b is The third scanning signal Scan (Mm) c is supplied to the gate of the output control switch Sw3 via the third scanning signal line 140c, and is supplied to the gate of the correction switch Sw2a via the second scanning signal line 140b. Is done.

  Here, the operation of the pixel 110 of the present embodiment will be described. First, with the correction switch Sw2a closed (ON) and the output control switch Sw3 opened (OFF), the pixel selection switch Sw1 and the correction switch Sw2b are closed ( ON), a current I having a magnitude corresponding to the video signal Data (N-n) is supplied to the drive control element Tr. Thereafter, the correction switch Sw2a is opened (OFF), and the gate-source voltage of the drive control element Tr determined by the input signal is held in the capacitor C1 (signal writing period).

  Next, the pixel selection switch Sw1 and the correction switch Sw2b are opened (OFF), and then the correction switch Sw2a is closed (ON).

  Then, the output control switch Sw3 is closed (ON), and the display element 111 is connected to the drain of the drive control element Tr. As a result, a current having a magnitude substantially equal to the current I flows through the display element 111, and the light emitting operation starts (light emitting period).

  Also in the present embodiment, regarding the on / off control of the correction switches Sw2a and Sw2b, after the correction switch Sw2a on the side closest to the gate of the drive control element Tr is shifted from the on state to the off state, the second terminal (drain) side The correction switch Sw2b is shifted from the on state to the off state, and thereafter, the correction switch Sw2a closest to the control terminal (gate) is shifted from the off state to the on state. Therefore, the same effect as that described in the fifth embodiment can be obtained.

  It should be noted that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements in an implementation stage without departing from the scope of the invention. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Further, components of different embodiments may be appropriately combined.

FIG. 1 is a plan view schematically showing an active matrix display device according to a first embodiment of the present invention. 2 is a timing chart illustrating an example of a method for driving the active matrix display device illustrated in FIG. FIG. 2 is a plan view schematically showing an example of a structure that can be employed in the active matrix display device of FIG. 1. FIG. 9 is an equivalent circuit diagram schematically illustrating an example of a structure that can be employed in the active matrix display device according to the second embodiment of the present invention. FIG. 9 is a plan view schematically showing an active matrix display device according to a third embodiment of the present invention. 6 is a timing chart illustrating an example of a method for driving the active matrix display device illustrated in FIG. FIG. 13 is an equivalent circuit diagram schematically showing an example of a structure that can be employed in an active matrix display device according to a fourth embodiment of the present invention. 13 is a timing chart showing an example of a method for driving an active matrix display device according to a fifth embodiment of the present invention. FIG. 1 is an equivalent circuit diagram schematically showing an example of a structure that can be employed in an active matrix display device according to the present invention. 10 is a timing chart illustrating an example of a method for driving an active matrix display device using the equivalent circuit illustrated in FIG. 9.

Explanation of reference numerals

  Reference numeral 14: wiring, 15: wiring, 21: semiconductor layer, 22a, 22b: gate, 100: organic EL display device, 101: support substrate, 110: pixel, 111: display element, 120: drive circuit, 121: video signal line Drive circuit, 122: scan signal line drive circuit, 130: video signal line, 140a to 140d: scan signal line, Sw1: pixel selection switch, C1, C2: capacitor, Tr: drive control element, Sw2a, Sw2b: correction switch , Sw3: output control switch, R1, R2: resistor, Scan1a to ScanMa: scan signal, Scan1b to ScanMb: scan signal, Scan1c to ScanMc: scan signal, Scan1d to ScanMd: scan signal, Data1 to DataN: video signal, Starta ... Start signal, Clka to Clkd ... Clock signal

Claims (10)

A drive control element including a first terminal connected to the first power supply terminal, a control terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal;
A display element connected between the second terminal and the second power supply terminal, the optical property of which changes according to the magnitude of the flowing current;
A first capacitor connected to the control terminal;
A second capacitor having one terminal connected to the control terminal;
A first switch connected between the other terminal of the second capacitor and a video signal line;
A plurality of second switches that are connected in series between the second terminal and the control terminal and whose conduction state is controlled by a control signal supplied from a control line;
A third switch that is interposed between the second terminal and the display element and that switches conduction / non-conduction therebetween.
The plurality of second switches are a plurality of field-effect transistors having the same conductivity type, and among the plurality of field-effect transistors, the one located closest to the control electrode side has a gate directly connected to the control line, Adjacent components are connected via a first resistor having a gate made of a polysilicon layer, and those located closest to the second terminal side are connected to a third power supply terminal via a second resistor having a gate made of a polysilicon layer. An active matrix display device, characterized in that the display device is connected to a display. A drive control element including a first terminal connected to the first power supply terminal, a control terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal;
A display element connected between the second terminal and the second power supply terminal, the optical property of which changes according to the magnitude of the flowing current;
A capacitor connected to the control terminal;
A first switch connected between the second terminal and a video signal line;
A plurality of second switches that are connected in series between the second terminal and the control terminal and whose conduction state is controlled by a control signal supplied from a control line;
A third switch that is interposed between the second terminal and the display element and that switches conduction / non-conduction therebetween.
The plurality of second switches are a plurality of field-effect transistors having the same conductivity type, and among the plurality of field-effect transistors, the one located closest to the control electrode side has a gate directly connected to the control line, Adjacent components are connected via a first resistor having a gate made of a polysilicon layer, and those located closest to the second terminal side are connected to a third power supply terminal via a second resistor having a gate made of a polysilicon layer. An active matrix display device, characterized in that the display device is connected to a display.   3. The active matrix display device according to claim 1, wherein the third power supply terminal is the same as the second power supply terminal. A drive control element including a first terminal connected to the first power supply terminal, a control terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal;
A display element connected between the second terminal and the second power supply terminal, the optical property of which changes according to the magnitude of the flowing current;
A first capacitor connected to the control terminal;
A second capacitor having one terminal connected to the control terminal;
A first switch connected between the other terminal of the second capacitor and a video signal line;
A plurality of second switches that are connected in series between the second terminal and the control terminal and whose conduction state is controlled by control signals supplied from a plurality of control lines independent of each other,
An active matrix display device, comprising: a third switch that is interposed between the second terminal and the display element and that switches conduction / non-conduction between them. A drive control element including a first terminal connected to the first power supply terminal, a control terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal;
A display element connected between the second terminal and the second power supply terminal, the optical property of which changes according to the magnitude of the flowing current;
A capacitor connected to the control terminal;
A first switch connected between the second terminal and a video signal line;
A plurality of second switches that are connected in series between the second terminal and the control terminal and whose conduction state is controlled by control signals supplied from a plurality of control lines independent of each other,
An active matrix display device, comprising: a third switch that is interposed between the second terminal and the display element and that switches conduction / non-conduction between them.   5. The plurality of second switches are a plurality of field effect transistors having the same conductivity type, and gates of the plurality of field effect transistors are respectively connected to the plurality of control lines. Item 6. An active matrix display device according to item 5. A drive control element including a first terminal connected to the first power supply terminal, a control terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal;
A display element connected between the second terminal and the second power supply terminal, the optical property of which changes according to the magnitude of the flowing current;
A plurality of switches connected in series between the control terminal and the second terminal,
The plurality of switches are a plurality of field effect transistors having the same conductivity type,
An active matrix display device, wherein the gates of the plurality of field effect transistors are connected via a semiconductor layer having the same stacking position as the semiconductor layer on which the sources and drains of the plurality of field effect transistors are formed. . A drive control element including a first terminal connected to the first power supply terminal, a control terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal;
A display element connected between the second terminal and the second power supply terminal, the optical property of which changes according to the magnitude of the flowing current;
A plurality of switches connected in series between the control terminal and the second terminal,
An active matrix display device, wherein the plurality of switches are controlled in conduction state by control signals supplied from a plurality of independent control lines. A drive control element including a first terminal connected to the first power supply terminal, a control terminal, and a second terminal that outputs a drive current with a magnitude corresponding to a voltage between the first terminal and the control terminal;
A display element connected between the second terminal and the second power supply terminal, the optical property of which changes according to the magnitude of the flowing current;
A plurality of switches connected in series between the control terminal and the second terminal,
The plurality of switches are a plurality of field effect transistors having the same conductivity type,
While the plurality of switches are in a non-conductive state,
The potential of each connection unit connecting the plurality of switches is between the potential of the control terminal and the potential of the second terminal,
In a case where the plurality of switches are three or more switches, the connection portions of the plurality of switches have a potential closer to the control terminal, the closer the potential is to the potential of the control terminal, and the closer the closer to the second terminal, the higher the potential of the second terminal is. The relationship is closer to the potential of the two terminals,
An active matrix display device, wherein a gate potential of the plurality of switches is set so that a potential of one of the control terminal and the second terminal monotonically decreases from a higher side to a lower side. A drive control element comprising: a first terminal connected to a first power supply terminal; a control terminal; and a second terminal for outputting a drive current having a magnitude corresponding to a voltage between the first terminal and the control terminal; A display element connected between the power supply terminal and having a change in optical characteristics according to the magnitude of the flowing current; a capacitor connected to the control terminal; and a series connected between the control terminal and the second terminal. A method for driving an active matrix display device having a pixel circuit having at least a plurality of switches connected to a plurality of switches and a plurality of control lines to which control terminals of the plurality of switches are independently connected,
After shifting the switch closest to the control terminal from the on state to the off state, the switch on the second terminal side is shifted from the on state to the off state, and thereafter, the switch closest to the control terminal A method for driving an active matrix type display device, wherein the device is shifted from an off state to an on state.

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