TWI625991B - Circuit board structure and method for forming the same - Google Patents

Abstract

The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes: a substrate; a dielectric layer formed on the substrate; a first circuit layer formed in the dielectric layer, wherein the first circuit layer has a structure with a wide width and a narrow width; A conductive lining layer is formed on the first circuit layer; and a second circuit layer is formed on the conductive lining layer, wherein the second circuit layer is electrically connected to the first wiring layer through the conductive lining layer. Line layer.

Description

Circuit board structure and manufacturing method thereof

The present invention relates to a circuit board structure, and more particularly, to a circuit board structure having a conductive structure.

In the new generation of electronic products, the continuous pursuit of lightness, thinness and shortness has led to the development of integrated circuits (ICs) towards high density. Therefore, printed circuit boards (PCBs) have also been designed to be miniaturized accordingly. Make the configuration of electrical connection lines more dense.

At present, the technology of manufacturing printed circuit boards is mainly composed of a plurality of patterned conductive layers and a plurality of dielectric layers alternately stacked, and the internal circuit structure is used to achieve electrical connection. At present, most high-density wiring circuit boards are manufactured by a build-up method.

The internal circuit structure may include a conductive connection structure and an internal circuit layer. The internal circuit layer is electrically connected to the conductive connection structure, and the conductive connection structure is, for example, a conductive through hole structure or a conductive buried hole structure. ) Or conductive blind hole structure. When making a conductive connection structure, a roughening process may be performed on the conductive material first, but the roughening process may cause the conductive material to be excessively removed, and a good electrical component connection effect cannot be achieved, because Therefore, the industry urgently needs to improve the conductive connection structure of the substrate.

The invention provides a circuit board structure including: a substrate; a dielectric layer formed on the substrate; a first circuit layer formed in the dielectric layer, wherein the first circuit layer has an upper width A lower narrow structure; a conductive lining layer formed on the first circuit layer; and a second circuit layer formed on the conductive lining layer, wherein the second circuit layer is electrically conductive through the conductive lining layer Connected to this first line layer.

The invention also provides a method for manufacturing a circuit board structure, which includes the following steps: providing a substrate; forming a dielectric layer on the substrate; removing a portion of the dielectric layer to be in the dielectric layer Forming a trench; filling a conductive material in and above the trench; removing a portion of the conductive material to expose a portion above the trench and forming a first circuit layer; forming a conductive liner In the trench and on the dielectric layer; and forming a second circuit layer on the conductive liner layer.

10‧‧‧ Central District

20‧‧‧Peripheral area

12‧‧‧ conductive pattern alienation area

14‧‧‧ conductive pattern dense area

102‧‧‧ substrate

104、104’‧‧‧conductive layer

106‧‧‧ Dielectric layer

107‧‧‧Trench

107a‧‧‧ above the trench

108‧‧‧ conductive material

110‧‧‧First circuit layer

120‧‧‧ conductive liner

122‧‧‧Photoresist

130‧‧‧Second circuit layer

140‧‧‧via

W ₁ ‧‧‧Top width

W ₂ ‧‧‧ bottom width

D ₁ ‧‧‧ first depth

D ₂ ‧‧‧Second Depth

H ₁ ‧‧‧ height

T ₁ ‧‧‧ first thickness

T ₂ ‧‧‧ second thickness

Complete disclosure according to the following detailed description and accompanying drawings. It should be noted that, according to the general operations of the industry, the drawings are not necessarily drawn to scale. In fact, the size of the element may be arbitrarily enlarged or reduced for clarity.

Figures 1A-1J show cross-sectional views of forming a circuit board structure at various process stages according to some embodiments of the present invention.

FIG. 2A shows a top view of a circuit board structure according to some embodiments of the present invention.

FIG. 2B is a top view of a circuit board structure according to some embodiments of the present invention.

The following summary provides many different embodiments or examples to implement different features of the present application. The following summary describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present invention describes that a first feature is formed on or above a second feature, it means that it may include an embodiment where the first feature is in direct contact with the second feature, or it may include additional The feature is an embodiment in which the feature is formed between the first feature and the second feature, and the first feature and the second feature may not be in direct contact. In addition, the same reference symbols and / or marks may be repeatedly used in different examples of the following invention. These repetitions are for simplicity and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

Various variations of the embodiments are described below. Through various views and illustrated embodiments, similar component numbers are used to identify similar components. It should be understood that the additional operation steps may be implemented before, during or after the method, and in other embodiments of the method, part of the operation steps may be replaced or omitted.

The present invention provides various embodiments of a circuit board structure and a manufacturing method thereof. Figures 1A-1J show cross-sectional views of forming a circuit board structure at various process stages according to some embodiments of the present invention. FIG. 2A shows a top view of a circuit board structure according to some embodiments of the present invention. Fig. 1A is a sectional view taken along the line AA 'in Fig. 2A. It should be noted here that these diagrams are simplified illustrations The drawings emphasize the features of the present invention, so the dimensions of the components in the drawings are not drawn according to actual scale. Moreover, the embodiments of the present invention may also include elements not shown in the figure.

Referring to FIGS. 1A and 2A, a substrate 102 is provided. The substrate 102 includes a central region 10 and a peripheral region 20. The central area 10 is a main line distribution area, and the peripheral area is not provided with any circuits. The central region 10 includes a conductive pattern alienation region 12 and a conductive pattern dense region 14. A conductive layer 104 is formed on the substrate 102 and is located in the conductive pattern alienation region 12. 14. The number of the conductive layers 104 in the conductive pattern alienation region 12 is less than the number of the conductive layers 104 'in the conductive pattern dense region 14. That is, the density of the conductive layer 104 in the conductive pattern alienation region 12 is smaller than the density of the conductive layer 104 'in the conductive pattern dense region 14. When the density of the conductive patterns in the two regions is different, when the subsequent plating process is performed, the current density will be different due to the pattern density in different regions, which will cause the thickness of the conductive material in the different regions to be uneven, and then affect the quality of the circuit structure.

The core material of the substrate 102 includes paper phenolic resin, composite epoxy, polyimide resin, or glass fiber. In some embodiments, the material of the conductive layer 104 is composed of a metal, such as copper (Cu), aluminum (Al), nickel (Ni), gold (Cu), the alloy described above, or a combination thereof.

Referring to FIG. 1B, a dielectric layer 106 is formed on the conductive layer 104. The material of the dielectric layer 106 includes a non-photosensitive resin, an epoxy resin, or a light-sensitive resin, and the epoxy resin is, for example, bismaleimide-triazabenzene resin. (bismaleimide triacine (BT)), ABF (ajinomoto build-up film), polyphenylene oxide (PPE), polytetrafluoroethylene (PTFE), or a combination thereof. The method of forming the dielectric layer 106 includes chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, or other suitable manufacturing methods.

Referring to FIG. 1C, a portion of the dielectric layer 106 is removed to form a trench 107 in the dielectric layer 106 and expose the conductive layer 104. The method for forming the trench 107 includes a mechanical drill process, a laser drill process, or other suitable processes. The purpose of forming the trench 107 is to subsequently fill the trench 107 with a conductive material to form a via hole 140 (see FIG. 1J) on the conductive layer 104 as an electrical connection.

In some embodiments, the trench 107 is formed by a laser drilling process. The advantages of using the laser drilling process are that the depth of the hole is easier to control accurately, and the range of materials used for drilling is wider, and it is easy to make smaller hole diameters, so a better aspect ratio can be obtained.

Because the laser drilling process is used, the trench 107 has a cross-sectional profile that is wide up and narrow, and has inclined sidewalls. In short, the groove 107 has a trapezoidal cross-sectional profile. The trench 107 has a top surface width W ₁ and a bottom surface width W _{2. The} top surface width W _{1 is} larger than the bottom surface width W ₂ . The depth of the trench 107 is defined as a first depth D ₁ . In some embodiments, the ratio of the depth (D ₁ ) to the width (W ₁ ) ranges from about 1 to 3. It should be noted that when the trench 107 has a high aspect ratio, it is not conducive to the filling of the conductive material, which may cause incomplete filling of the holes and generate holes, thereby reducing the conductivity of the vias. In order to avoid the disadvantages caused by filling the trench 107 with a high aspect ratio, in the subsequent process steps of the present invention, the conductive material is filled in the trench 107 in sections to reduce the risk of incomplete hole filling.

In some embodiments, the laser used in the laser drilling process is, for example, a neodymium yttrium aluminum garnet (Nd: YAG) laser. In some other embodiments, the laser used in the laser drilling process is, for example, a carbon dioxide (CO ₂ ) laser or a UV laser. The energy and time of the laser applied during the laser drilling process can be appropriately adjusted according to the material of the dielectric layer 106 and the thickness of the trench 107 to be formed. After the laser drilling process, a desmear step is performed to remove the glue slag generated by the laser drilling.

Referring to FIG. 1D, a conductive material 108 is filled in and on the trench 107. In some embodiments, the conductive material 108 includes copper (Cu), aluminum (Al), nickel (Ni), gold (Cu), or a combination thereof. In some embodiments, the method of forming the conductive material 108 is panel plating.

Please also refer to FIG. 2B, which illustrates a top view of a conductive material 108 according to some embodiments of the present invention.

It should be noted that, since the central region 10 has the conductive pattern alienation region 12 and the conductive pattern dense region 14, if the trench 107 on the conductive pattern alienation region 12 and the conductive pattern dense region 14 is respectively plated with conductive material, The density of the conductive pattern in each area is different, and the current density generated will be different, that is, the current distribution is uneven, which makes the thickness uniformity of the conductive material in the groove 107 of the entire substrate (or circuit board) worse. Will affect the conductivity of the circuit board structure.

In order to improve the thickness uniformity of the conductive material in the vias, the present invention first performs panel plating, and then removes unnecessary portions of the metal layer to ensure that it is above the conductive layer 104 in each region of the substrate 102 Front line The circuit layer 110 (see FIG. 1E) has substantially the same thickness to prevent the thickness of the circuit layer formed by subsequent plating from being different, so the problem of poor uniformity of the thickness of the conductive material in the via is solved.

In some embodiments, in the process of forming the conductive material 108 by panel plating, the conductive material 108 is entirely deposited on all regions of the substrate 102, including the conductive pattern detached region 12 and the conductive pattern of the central region 10. The dense region 14 can improve the thickness uniformity of the conductive material 108 (or the first circuit layer 110 formed subsequently). After the full-plate electroplating process, the upper surface of the conductive material 108 is substantially flat.

Referring to FIG. 1E, a portion of the conductive material 108 is removed to expose a portion 107 a above the trench 107 and form a first circuit layer 110. As such, the first circuit layer 110 is electrically connected to the conductive layer 104 and directly contacts the conductive layer 104. In some embodiments, a portion of the conductive material 108 is removed by an etching process, such as a wet etching process. In some embodiments, the step of removing a portion of the conductive material 108 may also be referred to as an etching back process.

As shown in FIG. 1E, the depth of the portion 107 a above the trench 107 is defined as the second depth D ₂ . If the second depth D _{2 is} too small, it will be detrimental to the subsequent deposition of the conductive liner layer 120 and the second circuit layer 130 (as shown in FIG. 1I), that is, the etching solution cannot be easily filled into the second depth D ₂ , resulting Subsequent materials cannot fill the second depth D _2. In addition, it is possible that the conductive material 108 remains on the dielectric layer 106, which will affect the deposition of the subsequent conductive liner 120. Therefore, the etching process must at least be located on the dielectric layer 106. The conductive material 108 above is completely removed. If the second depth D _{2 is} too large, that is, the thickness of the material of the first circuit layer 110 is too thin, because the subsequent roughening process (as shown in FIG. 1G), the roughening process may excessively remove the conductive liner. 120, it is even possible to remove a portion of the first circuit layer 110 and create a void between the first circuit layer 110 and the conductive layer 104.

After the etching process, the remaining conductive material 108 remains in the lower portion of the trench 107 to form a first circuit layer 110, where the first circuit layer 110 has a first height H ₁ . In some embodiments, the ratio of the first height (H ₁ ) of the first circuit layer 110 to the first depth (D ₁ ) of the trench 107 ranges from about 15% to about 97%. If this ratio is less than 15%, it means that the thickness of the first circuit layer 110 is too thin. When the roughening process is subsequently performed, the roughening process may excessively remove the first circuit layer 110 and cause a part of the conductive layer 104 to be exposed, and Undesirable voids are generated between the first circuit layer 110 and the conductive layer 104. When this ratio is greater than 97%, it means that the thickness of the first circuit layer 110 is too thick, and it is possible that the conductive material 108 remains on the dielectric layer 106, which will affect the subsequent deposition of the conductive liner layer 120. Therefore, the etching process At least the conductive material 108 above the dielectric layer 106 must be completely removed.

Since the trench 107 has a cross-sectional structure with a wide upper width and a narrow cross-section, the first circuit layer 110 filling the lower portion of the trench 107 also has a cross-sectional structure with a wide upper width and a narrow cross-section. (Panel plating) is formed, and therefore, the thickness of the first circuit layer 110 is the same in different regions (for example, in the conductive pattern alienation region 12 and the conductive pattern dense region 14). That is, by this method, the thickness uniformity of the first wiring layer 110 can be improved.

Referring to FIG. 1F, a conductive liner 120 is formed in the upper portion 107a of the trench 107 and on the dielectric layer 106. More specifically, the conductive liner 120 is conformally formed on the bottom and sidewalls of the portion 107a above the trench 107 and extends above the dielectric layer 106, but the conductive liner 120 does not fill the trench groove Part 107a above 107. Therefore, the conductive liner 120 directly contacts the first wiring layer 110 and is electrically connected to the first wiring layer 110. Because the trench 107 has a wide cross section with a narrow upper profile, the conductive liner 120 has inclined sidewalls, and the bottom of the conductive liner 120 is not perpendicular to the sidewall of the conductive liner 120.

The purpose of forming the conductive liner layer 120 is to serve as a seed layer of the second circuit layer 130 to be formed later, so as to facilitate the formation of the subsequent second circuit layer 130 (see FIG. 1I).

In some embodiments, the material of the conductive liner 120 includes copper (Cu), aluminum (Al), nickel (Ni), gold (Cu), palladium (Pd), or a combination thereof. In some embodiments, the method for forming the conductive liner 120 is an electroless plating method. In some embodiments, the conductive liner layer 120 is composed of palladium (Pd), and the first circuit layer 110 is composed of copper (Cu). Since the material of the conductive liner layer 120 is different from that of the first circuit layer 110, There is a clear interface between the two materials.

Since the conductive liner 120 is compliantly deposited in the trench 107, the first thickness T ₁ of the conductive liner 120 deposited on the bottom of the trench 107 will be smaller than that of the conductive liner deposited on the dielectric layer 106. The second thickness T _{2 of} 120. Especially when the depth of the trench 107 is deeper, the difference between the first thickness T ₁ of the conductive liner 120 at the bottom of the trench 107 and the second thickness T ₂ of the conductive liner 120 deposited on the dielectric layer 106 will be even greater. To obviously. Moreover, the deposition thickness of the conductive liner 120 is relatively thin compared to the first depth D _{1 of the} entire trench 107. Therefore, when the roughening process is subsequently performed (see FIG. 1G), the conductive The liner layer 120 is easily removed and cannot be used as a seed layer or generates voids that are not intended to be formed. The voids may affect subsequent conductivity. In some embodiments, the first thickness T ₁ of the conductive liner 120 ranges from about 0.1 μm to about 5 μm. In some embodiments, the first thickness T _{1 is} smaller than the second thickness T ₂ , and the difference between the first thickness T ₁ and the second thickness T ₂ is about 0.01 μm to about 4 μm.

Referring to FIG. 1G, the conductive liner 120 is roughened so that the conductive liner 120 has a roughened surface 120a. That is, the surface roughening process is performed on the conductive liner 120 to improve the roughness of the upper surface of the conductive liner 120. The purpose of the roughening process is to roughen the surface of the conductive liner 120 to improve the adhesion between the photoresist 122 (see FIG. 1H) and the conductive liner 120 formed later.

In one embodiment, the roughened surface 120a has a surface roughness (Ra) of about 0.01 micrometer (μm) to about 0.6 micrometer (μm). When the surface roughness (Ra) of the roughened surface 120a is within the above range, the adhesion between the photoresist 122 (as shown in FIG. 1H) and the conductive liner 120 can be effectively improved. When the surface roughness is less than 0.1 micrometer (μm), the adhesion between the photoresist 122 (as shown in FIG. 1H) and the conductive liner 120 is too low, which may cause the photoresist 122 to peel or peel off, and it is impossible to define Area forms a second wiring layer 130. When the surface roughness is higher than 0.4 micrometer (μm), it may be disadvantageous for subsequent deposition of the second circuit layer 130.

In some embodiments, the conductive liner 120 is subjected to a surface roughening process by an etching process, so that the upper surface of the conductive liner 120 has a certain roughness. In some embodiments, the conductive liner 120 is subjected to a wet etching (etching solution) process, so that the conductive liner 120 has a roughened surface 120a. When the roughening process is performed, a suitable roughening method may be selected according to different materials of the conductive liner 120 as long as the surface of the conductive liner 120 can reach a certain range of surface roughness.

It should be noted that if the first circuit layer 110 is not formed in advance, the conductive liner layer 120 is directly formed in the trench 107 directly. During the roughening process, part of the conductive liner 120 may be removed by the roughening process, especially the thickness of the conductive liner 120 located at the bottom of the trench 107 is relatively thin. The conductive liner 120 may be completely removed by the roughening process and formed. Voids, which makes it impossible to achieve good electrical contact.

Referring to FIG. 1H, a patterned photoresist 122 is formed on a portion of the roughened surface 120a to expose other portions of the roughened surface 120a. A patterned photoresist 122 is formed by an image transfer process. The image transfer process includes a lithography process and an etching process. Lithography processes include photoresist coating (eg, spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (eg, hard baking). The etching process is, for example, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or other suitable processes.

It should be noted that, in the present invention, the conductive liner 120 having a roughened surface 120a is formed in advance to improve the adhesion between the photoresist 122 and the conductive liner 120, so as to further improve the accuracy of the patterning process. If the roughened surface is not formed, the photoresist 122 is easily peeled off, and the position of the second circuit layer 130 cannot be correctly positioned, which reduces the accuracy of the circuit layout and further reduces the yield of the circuit board.

Referring to FIG. 11, a second circuit layer 130 is formed on the exposed roughened surface 120 a. The second circuit layer 130 is electrically connected to the first circuit layer 110 through the conductive liner layer 120.

The material of the second circuit layer 130 may be the same as or different from that of the first circuit layer 110. In some embodiments, the material of the second circuit layer 130 includes copper (Cu), aluminum (Al), nickel (Ni), gold (Cu), or a combination thereof. In some embodiments, the second circuit layer 130 may be formed by a plating process.

It should be noted that because the first The circuit layer 110 and the portion under the trench 107 have been partially filled. When the second circuit layer 130 is to be formed subsequently, the depth required to fill the trench 107 has been reduced, that is, the depth of the trench filling has been reduced. The difficulty of subsequent deposition of the second circuit layer 130 to the trench 107 is reduced. Especially when making a via structure with a high aspect ratio, since the first circuit layer 110 can be formed in the trench 107 in advance, and the conductive liner layer 120 and the second circuit layer 130 can be filled in sequence subsequently, therefore, It can more effectively reduce the difficulty of trench filling of the second circuit layer 130 to improve the yield of the overall process.

Referring to FIG. 1J, the photoresist 122 is removed to obtain the structure of the vias 140. The vias 140 are composed of the first circuit layer 110, the conductive liner layer 120, and the second circuit layer 130. The conductive liner layer 120 is between Between the first circuit layer 110 and the second circuit layer 130, and a conductive liner 120 surrounds a part of the second circuit layer 130. The conductive backing layer 120 has a rough surface 120 a, and the rough surface 120 a directly contacts the second circuit layer 130. The lower surface of the second circuit layer 130 is wider than the lower surface of the first circuit layer 110.

The present invention sequentially fills the first circuit layer 110, the conductive liner layer 120, and the second circuit layer 130 in the trench 107 through a three-stage deposition step, so that the circuit board structure has a via hole 140. First, as shown in FIG. 1D, the entire substrate 102 (or circuit board) is firstly subjected to a full-plate electroplating process to form a first circuit layer 110 in the trench 107 to improve the first circuit layer 110 in all regions of the substrate 102. Uniformity of thickness. Furthermore, as shown in FIG. 1F, the conductive liner layer 120 is filled as a seed layer, and the conductive liner layer 120 is directly formed on the first circuit layer 110. Before the subsequent roughening process, since the first circuit layer is used, 110 is used as a protective layer to avoid excessive removal of the conductive liner 120 during the roughening process, which causes problems such as pits. Finally, as shown in FIG. 1J, a portion of the second circuit layer 130 over the trench 107 is formed. Among other things, the present invention forms a circuit structure by segmenting to solve the problem of uneven thickness of the circuit structure in different regions, and avoids the problem of pits caused by the excessive removal of the conductive liner 120 during the roughening process.

In summary, the present invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes a via hole 140 which is wide at the top and narrow at the bottom. The conductive material is filled in the trench 107 in sections during the manufacturing process. First, a first circuit layer 110 having a certain thickness ratio is formed by the full-plate plating method, and then conformally formed. The conductive backing layer 120 is finally formed on the conductive backing layer 120 having the roughened surface 120a. The advantages of the circuit board structure of the present invention are that it can not only improve the uniformity of the thickness of the conductive layer of the circuit pattern of the entire substrate, but also avoid the roughening process from excessively etching the conductive liner, and because the conductive material is filled in sections, the filling trench can be reduced. Complete risk, therefore, improving the conductive ability of the vias and improving the yield of the circuit board structure.

The foregoing text summarizes the features of many embodiments so that those having ordinary skill in the art can better understand the present invention from various aspects. Those with ordinary knowledge in the technical field should understand that other processes and structures can be easily designed or modified based on the present invention, so as to achieve the same purpose and / or achieve the same as the embodiments and the like described herein. Advantages. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention. Without departing from the spirit and scope of the invention, various changes, substitutions, or modifications can be made to the invention.

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make any changes without departing from the spirit and scope of the present invention. And retouching, Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

Claims (19)

A circuit board structure includes: a substrate; a dielectric layer formed on the substrate; a first circuit layer formed in the dielectric layer, wherein the first circuit layer has an upper width and a lower width. A structure; a conductive liner layer formed on the first circuit layer; and a second circuit layer formed on the conductive line layer, wherein the second circuit layer is electrically connected to the conductive line layer through the conductive line layer First line layer. According to the circuit board structure described in the first item of the patent application scope, wherein the conductive liner layer has a roughened surface, and the roughened surface directly contacts the second circuit layer. The circuit board structure according to item 2 of the patent application scope, wherein the roughened surface has a surface roughness (Ra) of 0.01 micrometer (μm) to 0.6 micrometer (μm). According to the circuit board structure described in the first item of the patent application scope, wherein the dielectric layer has a groove, the groove has a bottom surface width and a top surface width, and the top surface width is greater than the bottom surface width. The circuit board structure according to item 4 of the scope of patent application, wherein the first circuit layer, the conductive liner layer, and the second circuit layer are formed in the trench. The circuit board structure described in item 5 of the scope of patent application, wherein the first circuit layer is located below the trench, and the conductive liner layer extends from a part of the sidewall of the trench to above the dielectric layer, The conductive liner is interposed between the second circuit layer and the dielectric layer. The circuit board structure described in item 4 of the scope of patent application, wherein the ratio of the height of the first circuit layer to the depth of the trench ranges from 15% to 97%. The circuit board structure according to item 1 of the patent application scope further includes: a conductive layer formed under the first circuit layer, wherein the first circuit layer is electrically connected to the conductive layer. The circuit board structure according to item 1 of the scope of patent application, wherein the lower surface of the second circuit layer is wider than the lower surface of the first circuit layer. A method for manufacturing a circuit board structure includes the following steps: providing a substrate; forming a dielectric layer on the substrate; removing a portion of the dielectric layer to form a trench in the dielectric layer ; Filling a conductive material into the trench; removing a part of the conductive material to expose a portion above the trench and forming a first circuit layer; forming a conductive liner layer on the upper portion of the trench A bottom surface and a sidewall; and a second circuit layer is formed on the conductive liner layer. The method for manufacturing a circuit board structure according to item 10 of the scope of patent application, further comprising: forming a conductive layer on the substrate, wherein the first circuit layer is formed on the conductive layer. According to the method for manufacturing a circuit board structure described in item 10 of the patent application scope, the method further includes: roughening the conductive liner layer so that the conductive liner layer has a roughened surface, and forming the second circuit layer on the conductive liner. Before the steps above the layer. The method for manufacturing a circuit board structure according to item 12 of the scope of patent application, wherein forming the second circuit layer on the conductive liner layer comprises: forming a patterned photoresist on a portion of the roughened surface To expose other parts of the roughened surface; and to form the second circuit layer on the exposed roughened surface. The method for manufacturing a circuit board structure according to item 12 of the application, wherein the roughened surface has a surface roughness (Ra) of 0.01 micrometer (μm) to 0.6 micrometer (μm). According to the method for manufacturing a circuit board structure described in item 10 of the scope of patent application, wherein the groove has a bottom surface width and a top surface width, and the top surface width is greater than the bottom surface width. The method for manufacturing a circuit board structure according to item 10 of the scope of patent application, wherein the substrate has a circuit region and a peripheral region, the trench is formed in the circuit region, and the conductive material is filled in the trench and The above steps further include: forming the conductive material on the entire surface of the substrate. The manufacturing method of the circuit board structure according to item 10 of the patent application scope, wherein removing a part of the dielectric layer is formed by a laser drilling process. The method for manufacturing a circuit board structure according to item 10 of the scope of patent application, wherein filling the conductive material into the trench further includes: filling the trench and filling the dielectric layer, wherein the conductive material One upper surface is higher than one upper surface of the dielectric layer. The method for manufacturing a circuit board structure according to item 10 of the scope of patent application, wherein forming the bottom surface and the side wall of the conductive liner layer on the trench further includes: forming the conductive liner layer on the dielectric layer. Above, wherein the conductive liner layer is interposed between the dielectric layer and the second circuit layer.