TWI691245B - Manufacturing method of circuit board - Google Patents
Manufacturing method of circuit board Download PDFInfo
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- TWI691245B TWI691245B TW107116208A TW107116208A TWI691245B TW I691245 B TWI691245 B TW I691245B TW 107116208 A TW107116208 A TW 107116208A TW 107116208 A TW107116208 A TW 107116208A TW I691245 B TWI691245 B TW I691245B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 229920005989 resin Polymers 0.000 claims abstract description 76
- 239000011347 resin Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 171
- 239000002184 metal Substances 0.000 claims description 171
- 238000000034 method Methods 0.000 claims description 45
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 38
- 239000011889 copper foil Substances 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 19
- 230000000903 blocking effect Effects 0.000 claims description 17
- 238000005553 drilling Methods 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000011651 chromium Substances 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 238000010329 laser etching Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000012779 reinforcing material Substances 0.000 claims description 8
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229920000049 Carbon (fiber) Polymers 0.000 claims description 4
- 239000004917 carbon fiber Substances 0.000 claims description 4
- 239000003365 glass fiber Substances 0.000 claims description 4
- -1 polypropylene Polymers 0.000 claims description 4
- 239000004743 Polypropylene Substances 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229920001155 polypropylene Polymers 0.000 claims description 3
- 229920001296 polysiloxane Polymers 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 4
- USIUVYZYUHIAEV-UHFFFAOYSA-N diphenyl ether Chemical compound C=1C=CC=CC=1OC1=CC=CC=C1 USIUVYZYUHIAEV-UHFFFAOYSA-N 0.000 claims 2
- 229920000642 polymer Polymers 0.000 claims 2
- 238000002203 pretreatment Methods 0.000 claims 1
- 238000007747 plating Methods 0.000 abstract description 12
- 238000004544 sputter deposition Methods 0.000 abstract description 7
- 238000007772 electroless plating Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 176
- 239000000126 substance Substances 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000004721 Polyphenylene oxide Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229920006380 polyphenylene oxide Polymers 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
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Abstract
Description
本發明係有關於一種線路板的製作方法,尤其是依序利用濺鍍處理、化學敷鍍處理、電鍍處理,而在基板上形成堆疊的第一金屬層、第二金屬層以及具有線路圖案第三金屬層,再藉線路蝕刻處理以蝕刻部分的第一、第二金屬層而形成細線寬/線距的線路。 The present invention relates to a method for manufacturing a circuit board, in particular, a first metal layer, a second metal layer and a circuit pattern having a circuit pattern are formed on a substrate by sequentially using a sputtering process, a chemical plating process, and an electroplating process The three metal layers are then etched to etch part of the first and second metal layers to form a thin line width/line spacing line.
近年來,隨著大型積體電路(VLSI)的快速發展,連接線路也越來越細。例如,在半導體22nm技術中,單位面積上的晶片密度和信號處理能力已不斷提高,而迫使連接線路進一步細微化,結果導致現有的生產、製造設備及製程面臨到前所未有的艱鉅挑戰。再者,為進一步提高封裝密度,將晶片進行堆疊以形成三維封裝,此時,線路基板的線寬/線距需從100um縮小到30-50um。對於業界不斷縮小線寬/線距的要求,線路的銅表面結構要求也不斷嚴格。通常,一般的印刷電路板(Printed Circuit Board,PCB)中的銅粗糙度Rz為5-7um,其中載板的粗糙度須低於5um,但是對於線寬/線距10-20um,線路的銅線表面粗糙度Rz一般要在2um,否則很容易會發生線路變形而導致整體的電氣功能失效,或者,線間會因殘留的銅而導致短路,因而無法實現高精度、高可靠度的互連。 In recent years, with the rapid development of large-scale integrated circuits (VLSI), connection lines have become thinner and thinner. For example, in the semiconductor 22nm technology, the wafer density and signal processing capability per unit area have been continuously improved, which has forced the connection lines to be further miniaturized. As a result, the existing production, manufacturing equipment and processes are facing unprecedented challenges. Furthermore, in order to further increase the packaging density, the chips are stacked to form a three-dimensional package. At this time, the line width/line spacing of the circuit substrate needs to be reduced from 100um to 30-50um. For the industry's requirements to continuously reduce the line width/line spacing, the copper surface structure requirements of the circuit are also constantly strict. Generally, the roughness Rz of copper in a printed circuit board (Printed Circuit Board, PCB) is 5-7um, where the roughness of the carrier board must be less than 5um, but for line width/line spacing 10-20um, the copper of the line The surface roughness Rz of the wire is generally 2um, otherwise it is easy to deform the wire and cause the overall electrical function to fail, or the wire will cause a short circuit due to the residual copper, which cannot achieve high-precision and high-reliability interconnect .
在習用技術中,一般是利用半加成法(Semi Additive Process,SAP)以製作細線寬/線距50um以下的線路,而線寬小於25um的 半加成SAP技術是使用素之味的ABF樹脂當絕緣層材料,或採用三菱瓦斯所生產的包覆樹脂銅箔(Primer Coated Copper Foil,PCF)及半固化片(或稱膠片,Prepreg),藉壓合方式而實現。對於包覆樹脂銅箔(PCF),主要是先在單面粗化好的銅箔面上塗覆一層2-3微米厚度的樹脂,經固化後再與半固化片一同壓合而形成,而壓合後,可將銅箔去除以形成表面有一定粗糙度的樹脂表面,因而可在樹脂表面藉化學鍍銅法(或化學膚鍍方式)而得到結合力良好的化學鍍銅層,藉以製作要求更為精細的線路。 In the conventional technology, the semi-additive process (Semi Additive Process, SAP) is generally used to make a line with a thin line width/line spacing below 50um, and the line width is less than 25um Semi-additive SAP technology is to use plain ABF resin as the insulating layer material, or to use Primer Coated Copper Foil (PCF) and prepreg (or film, Prepreg) produced by Mitsubishi Gas. Be achieved in a combined manner. For resin-coated copper foil (PCF), a layer of resin with a thickness of 2-3 microns is mainly coated on the surface of the copper foil roughened on one side, after curing, it is formed by pressing together with the prepreg, and after pressing , The copper foil can be removed to form a resin surface with a certain surface roughness, so the chemical copper plating layer (or chemical skin plating method) can be obtained on the resin surface to obtain a chemically copper plating layer with good binding force, so as to make the requirements more Fine lines.
以利用包覆樹脂銅箔(PCF)的SAP法為例,其具體作法是先將PCF壓合於內層線路上,再去除PCF上的銅箔,留下具有高度表面特性的樹脂,用以藉化學膚鍍方式,在樹脂的表面上形成具細線寬/線距的線路圖案層。 Take the SAP method using a resin-coated copper foil (PCF) as an example. The specific method is to first press the PCF on the inner layer circuit, and then remove the copper foil on the PCF, leaving the resin with high surface characteristics for By means of chemical skin plating, a circuit pattern layer with fine line width/line spacing is formed on the surface of the resin.
然而,上述習用技術的缺點在於去除PCF的銅箔後所留下的樹脂不夠穩固,使得利用化學膚鍍方式所形成的線路圖案層很容易因附著力不足而發生斷裂、剝離、脫落,而且很難保持線路圖案層在填滿盲孔以當作連接柱的直立形狀不發生偏移,影響線路的電氣品質及操作的可靠度。 However, the disadvantage of the above-mentioned conventional technology is that the resin left after removing the PCF copper foil is not stable enough, so that the circuit pattern layer formed by the chemical skin plating method is easily broken, peeled, and peeled off due to insufficient adhesion. It is difficult to keep the line pattern layer filled with blind holes as the upright shape of the connecting post without deviation, which affects the electrical quality of the line and the reliability of operation.
因此,非常需要一種線路板的製作方法,依序利用濺鍍處理、化學敷鍍處理或無電鍍處理、電鍍處理,而在基板上形成堆疊的第一金屬層、第二金屬層以及具有線路圖案第三金屬層,再藉蝕刻處理以蝕刻部分的第一、第二金屬層,形成細線寬/線距的線路,因而解決上述習用技術的所有問題。 Therefore, there is a great need for a method of manufacturing a circuit board, in which a first metal layer, a second metal layer and a circuit pattern with a stack are formed on the substrate by sequentially using sputtering, chemical plating, electroless plating, or electroplating The third metal layer is then etched to etch part of the first and second metal layers to form a thin line width/line spacing circuit, thus solving all the problems of the above-mentioned conventional techniques.
本發明之主要目的在於提供一種線路板的製作方法,用以製作易於形成細線寬/線距線路的線路板,並改善線路的精確度。 The main object of the present invention is to provide a method for manufacturing a circuit board, which is used to manufacture a circuit board that is easy to form a thin line width/line distance circuit, and to improve the accuracy of the circuit.
首先,本發明線路板的製作方法包括備製基板,且基板上具有阻止層以及樹脂層,其中樹脂層是在阻止層上,且表面具有Ra=0~1um及Rz=0~10um的粗糙度,並位於基板的表面,而阻止層具有圖案,且可為金屬或合金所構成。 First, the manufacturing method of the circuit board of the present invention includes preparing a substrate, and the substrate has a blocking layer and a resin layer, wherein the resin layer is on the blocking layer, and the surface has a roughness of Ra=0~1um and Rz=0~10um , And is located on the surface of the substrate, and the blocking layer has a pattern, and can be composed of metal or alloy.
接著,利用雷射鑽孔及/或機械鑽孔以貫穿樹脂層而形成至少一導通孔,其中導通孔為貫穿基板之底部的盲孔,且停止於阻止層而未進入阻止層,亦即,由阻止層阻止導通孔進入。此外,導通孔也可直接利用雷射光束的雷射鑽孔方式而形成,比如,可先在樹脂層上形成具有特定圖案的光阻層,再利用光阻層當作光罩而進行雷射蝕刻處理的雷射鑽孔,藉以形成導通孔。 Next, laser drilling and/or mechanical drilling are used to penetrate the resin layer to form at least one via hole, wherein the via hole is a blind hole penetrating the bottom of the substrate and stops at the blocking layer without entering the blocking layer, that is, The blocking layer prevents the via hole from entering. In addition, the via hole can also be directly formed by laser drilling of the laser beam. For example, a photoresist layer with a specific pattern can be formed on the resin layer first, and then the photoresist layer can be used as a photomask for laser Etching laser drilling to form via holes.
然後進行濺鍍處理,形成第一金屬層於樹脂層上,且覆蓋導通孔的表面。之後,進行化學敷鍍處理或無電鍍處理,形成第二金屬層,覆蓋第一金屬層的表面。接著,在第二金屬層上,利用電鍍處理形成第三金屬層,其中第三金屬層具有線路圖案以曝露出部分的第二金屬層並填滿導通孔,使得第一金屬層、第二金屬層及第三金屬層可相互電氣連接。 Then, a sputtering process is performed to form a first metal layer on the resin layer and cover the surface of the via hole. After that, chemical plating or electroless plating is performed to form a second metal layer to cover the surface of the first metal layer. Next, a third metal layer is formed on the second metal layer by electroplating, wherein the third metal layer has a circuit pattern to expose a portion of the second metal layer and fill the via holes, so that the first metal layer and the second metal The layer and the third metal layer can be electrically connected to each other.
最後,對曝露的第二金屬層進行線路蝕刻,並進一步蝕刻底下的第一金屬層而曝露出底下的部分樹脂,完成所需的線路板製作。 Finally, the exposed second metal layer is subjected to circuit etching, and the first metal layer underneath is further etched to expose part of the resin underneath to complete the required circuit board fabrication.
再者,樹脂層還可進一步包含均勻分佈於樹脂基材中的強化材料,且強化材料可包含多個玻璃纖維或碳纖維,用以增加抗撓性的作用,加強整體結構的機械強度,能避免發生撓曲、變形。 In addition, the resin layer may further include a reinforcing material uniformly distributed in the resin substrate, and the reinforcing material may include a plurality of glass fibers or carbon fibers to increase the flexibility resistance and enhance the mechanical strength of the overall structure, which can be avoided Deflection and deformation occurred.
此外,也可在樹脂層的上表面覆蓋銅箔層,因而在形成導通孔時,是先對銅箔層進行預先處理,比如對銅箔層進行黑化處理或棕化處理以氧化銅箔層的表面,再進行雷射蝕刻處理以形成導通孔。基板的上表面及/或下表面也可分別具有內層線路,比如由導金屬材料構成,並具有電氣圖案。 In addition, the upper surface of the resin layer may be covered with a copper foil layer, so when forming the via hole, the copper foil layer is pre-treated, such as blackening or browning the copper foil layer to oxidize the copper foil layer Then, laser etching treatment is performed to form via holes. The upper surface and /or the lower surface of the substrate may also have inner layer circuits, for example, made of a conductive metal material, and have electrical patterns.
更加具體而言,第一金屬層可包含上部金屬層及下部金屬層,其中上部金屬層是堆疊於下部金屬層之上,而且下部金屬層是堆疊於基板的內層線路層的裸露部分上。此外,上部金屬層包含銅(Cu),而下部金屬層包含鈦(Ti)、鉻(Cr)或鉭(Ta),且第二金屬層及第三金屬層可包含銅。第一金屬層還可包含底部金屬層,位於上述下部金屬層之下,並接觸到內層線路層的裸露部分,其中底部金屬層可包含氮化鈦(TiN)。 More specifically, the first metal layer may include an upper metal layer and a lower metal layer, wherein the upper metal layer is stacked on the lower metal layer, and the lower metal layer is stacked on the exposed portion of the inner circuit layer of the substrate. In addition, the upper metal layer includes copper (Cu), and the lower metal layer includes titanium (Ti), chromium (Cr), or tantalum (Ta), and the second metal layer and the third metal layer may include copper. The first metal layer may further include a bottom metal layer located below the above-mentioned lower metal layer and contacting the exposed portion of the inner circuit layer, wherein the bottom metal layer may include titanium nitride (TiN).
本發明之另一目的在於提供一種線路板的製作方法,包括備製基板、形成導通孔、形成第一金屬層、形成第二金屬層、形成第三金屬層、線路蝕刻,其中導通孔是貫穿基板的貫穿孔,而第一、第二、第三金屬層依序覆蓋基板的上表面、下表面以及貫穿孔的表面,且第三金屬層具有線路圖案,可曝露出部分的第二金屬層並填滿整個貫穿孔。尤其是,第一、第二金屬層是藉第三金屬層的線路圖案而在線路蝕刻時被蝕刻移除,進而曝露出第一金屬層底下的部分樹脂層。 Another object of the present invention is to provide a method for manufacturing a circuit board, which includes preparing a substrate, forming a via hole, forming a first metal layer, forming a second metal layer, forming a third metal layer, and etching a circuit, wherein the via hole is through The through hole of the substrate, and the first, second, and third metal layers sequentially cover the upper surface, the lower surface, and the surface of the through hole of the substrate, and the third metal layer has a circuit pattern, which can expose part of the second metal layer And fill the entire through hole. In particular, the first and second metal layers are etched and removed during circuit etching by the circuit pattern of the third metal layer, thereby exposing part of the resin layer under the first metal layer.
具體而言,本發明所製作的線路板可具有小於10um的線寬/線距,大幅改善線路板的品質,尤其是製程步驟簡單,易於實施,同時還能降低製作成本,具有價格優勢,能確實滿足電子元件封裝及電子應用產品對線路板的細線寬/線距的要求,有利於市場競爭。 Specifically, the circuit board manufactured by the present invention can have a line width/pitch less than 10um, which greatly improves the quality of the circuit board, especially the process steps are simple, easy to implement, and at the same time can reduce the manufacturing cost, has a price advantage, can It really meets the requirements of electronic components packaging and electronic application products for fine line width/line spacing of circuit boards, which is conducive to market competition.
10:基板 10: substrate
12:阻止層 12: Block layer
20:樹脂層 20: resin layer
30:導通孔 30: Via
40:第一金屬層 40: First metal layer
50:第二金屬層 50: second metal layer
60:第三金屬層 60: third metal layer
62:開口 62: opening
S10~S60:步驟 S10~S60: Step
第一圖顯示依據本發明第一實施例線路板的製作方法的操作流程圖。 The first figure shows the operation flow chart of the manufacturing method of the circuit board according to the first embodiment of the present invention.
第二A圖至第二F圖依序顯示本發明第一實施例製作方法之處理步驟的示意圖。 FIGS. 2A to 2F sequentially show the processing steps of the manufacturing method of the first embodiment of the present invention.
第三A圖至第三F圖依序顯示本發明第二實施例製作方法之處理步驟的示意圖。 FIGS. 3A to 3F sequentially show the processing steps of the manufacturing method of the second embodiment of the present invention.
以下配合圖示及元件符號對本發明之實施方式做更詳細的說明,俾使熟習該項技藝者在研讀本說明書後能據以實施。 The embodiments of the present invention will be described in more detail below with reference to icons and component symbols, so that those skilled in the art can implement them after studying this specification.
參閱第一圖,本發明第一實施例線路板的製作方法的操作流程圖。如第一圖所示,本發明第一實施例線路板的製作方法主要包括依序進行的步驟S10、S20、S24、S30、S40、S50及S60,用以製作易於形成細線寬/線距線路的線路板。此外,為進一步方便了解本發明製作方法的技術特徵,可同時參考第二A圖至第二F圖的示意圖。 Referring to the first figure, an operation flowchart of the method for manufacturing a circuit board according to the first embodiment of the present invention. As shown in the first figure, the manufacturing method of the circuit board according to the first embodiment of the present invention mainly includes the steps S10, S20, S24, S30, S40, S50, and S60 performed in order to make a line with a fine line width/pitch Circuit board. In addition, in order to further facilitate the understanding of the technical features of the manufacturing method of the present invention, reference may be made to the schematic diagrams of the second drawings A to F at the same time.
首先,本發明的製作方法是由步驟S10開始,備製基板10,如第二A圖所示,其中基板10係上具有阻止層12以及樹脂層20。樹脂層20是在阻止層12上,且位於基板10的表面,而阻止層12具有圖案,並為金屬或合金所構成。樹脂層20可利用壓合方式而形成,不過,本發明並非以此為限,亦即可使用其他方式,比如塗佈、噴塗。尤其是,樹脂層20是包含樹脂基材,其中樹脂基材包含環氧樹脂、FR4、FR5、Modified FR4)矽膠(Silicon)、BT樹脂、聚苯醚樹脂(PPO)、聚醯亞胺(PI)、
ABF(Ajinomoto build-up film)、聚丙烯或光可成像介電材料(Photo Imageable Dielectric Material,PIDM),而且樹脂層20的表面具有Ra=0~1um及Rz=0~10um的粗糙度。
First, the manufacturing method of the present invention starts from step S10 to prepare a
接著,進入步驟S20,如第二B圖所示,利用雷射鑽孔及/或機械鑽孔以貫穿樹脂層20而形成至少一導通孔30,其中導通孔30為貫穿基板10之底部的盲孔,且停止於阻止層12而未進入阻止層12。亦即,阻止層12是用以阻止導通孔30進入。導通孔30可直接利用雷射光束的雷射鑽孔方式而形成,不過本發明並非以此為限,比如,也可先在樹脂層20上,形成具有特定圖案的光阻層(圖中未顯示),然後再利用光阻層當作光罩而進行雷射蝕刻處理的雷射鑽孔,藉以形成所需的至少一導通孔30。
Next, proceed to step S20, as shown in FIG. 2B, use laser drilling and/or mechanical drilling to penetrate the
然後在步驟S30中,如第二C圖所示,進行濺鍍處理,而在樹脂層20上形成第一金屬層40,且第一金屬層40覆蓋導通孔30的表面。
Then in step S30, as shown in FIG. 2C, a sputtering process is performed to form a
執行步驟S40,如第二D圖所示,進行化學敷鍍處理或無電鍍處理,形成第二金屬層50,其中第二金屬層50覆蓋第一金屬層40的表面。
Step S40 is performed, as shown in the second D figure, a chemical plating process or an electroless plating process is performed to form a
在步驟S50中,如第二E圖所示,在第二金屬層50上,利用電鍍處理而形成第三金屬層60,其中第三金屬層60具有線路圖案以曝露出部分的第二金屬層50,並填滿導通孔30,使得第一金屬層40、第二金屬層50及第三金屬層60可相互電氣連接。
In step S50, as shown in the second E diagram, a
最後在步驟S60,如第二F圖所示,對曝露的第二金屬層
50進行線路蝕刻,並進一步蝕刻底下的第一金屬層40,藉以曝露出底下的部分樹脂層20,進而完成所需的線路板製作。
Finally, in step S60, as shown in the second F diagram, the exposed
上述的樹脂層20還可進一步包含均勻分佈於樹脂基材中的強化材料(圖中未顯示),且強化材料可包含多個玻璃纖維或碳纖維,用以增加抗撓性的作用,加強整體結構的機械強度,避免發生撓曲、變形。
The above-mentioned
此外,在備製基板10的步驟S10中,也可在基板10的樹脂層20的上表面上覆蓋銅箔層(圖中未顯示),因而,在形成導通孔30的步驟S20中,是先對銅箔層進行預先處理,比如包含該銅箔層進行黑化處理或棕化處理,用以氧化銅箔層的表面,接著再進行雷射蝕刻處理,以形成所需的至少一導通孔30。
In addition, in the step S10 of preparing the
再者,基板10的上表面上及下表面上可分別具有內層線路(圖中未顯示),或者是,基板10的上表面上或下表面上具有內層線路(圖中未顯示),內層線路是由導金屬材料構成,並可進一步具有電氣圖案。
Furthermore, the upper and lower surfaces of the
更加具體而言,第一金屬層40可進一步包含上部金屬層及下部金屬層(圖中未顯示),其中上部金屬層是堆疊於下部金屬層之上,而且下部金屬層是堆疊於基板10的內層線路層的裸露部分上,因為在步驟S20中所形成的導通孔30會曝露出部分的內層線路層。此外,上部金屬層包含銅(Cu),而下部金屬層包含鈦(Ti)、鉻(Cr)或鉭(Ta),且第二金屬層50及第三金屬層60可包含銅。
More specifically, the
再者,第一金屬層40還可包含底部金屬層(圖中未顯示),係位於上述下部金屬層之下,並接觸到內層線路層的裸露部分,其中底部金屬層可包含氮化鈦(TiN)。
Furthermore, the
此外,本發明的第二實施例為另一製作線路板的方法,其中第二實施例製作方法的操作流程圖仍如第一圖所示,包含步驟S10、S20、S24、S30、S40、S50及S60,用以製作易於形成細線寬/線距線路的線路板,且第二實施例是類似於第一實施例,不過為進一步方便了解本實施例的特徵,請配合第三A圖至第三F圖的示意圖。 In addition, the second embodiment of the present invention is another method of manufacturing a circuit board, wherein the operation flowchart of the manufacturing method of the second embodiment is still as shown in the first figure, including steps S10, S20, S24, S30, S40, S50 And S60, used to make a circuit board that is easy to form thin line width/line spacing, and the second embodiment is similar to the first embodiment, but to further facilitate the understanding of the characteristics of this embodiment, please cooperate with the third A to the third Schematic diagram of three F diagrams.
首先進行步驟S10的操作,備製基板10,其中基板10的上表面及下表面上分別具有樹脂層20,如第三A圖所示。接著,進入步驟S20,利用雷射鑽孔及/或機械鑽孔,貫穿基板10以及位於基板10之上、下表面的樹脂層20,藉以形成至少一導通孔30,而該至少一導通孔30本質上是貫穿孔,如第三B圖所示。
First, the operation of step S10 is performed to prepare the
在步驟S30中,如第三C圖所示,進行濺鍍處理,主要在樹脂層20上形成第一金屬層40,且第一金屬層40覆蓋導通孔30的表面。執行步驟S40,如第三D圖所示,進行化學敷鍍處理或無電鍍處理,形成第二金屬層50,其中第二金屬層50覆蓋第一金屬層40的表面。然後進入步驟S50,如第三E圖所示,在第二金屬層50上,利用電鍍處理而形成第三金屬層60,其中第三金屬層60具有線路圖案,並在該線路圖案上具有一開口62,該開口62對應曝露出部分的第二金屬層50,並填滿導通孔30,使得第一金屬層40、第二金屬層50及第三金屬層60可相互電氣連接,進而完成所需的線路板之製作。
In step S30, as shown in FIG. 3C, a sputtering process is performed, and a
最後在步驟S60,如第三F圖所示,對曝露的第二金屬層50進行線路蝕刻,並進一步蝕刻底下的第一金屬層40,藉以曝露出底下的部分樹脂層20,進而完成所需的線路板製作。
Finally, in step S60, as shown in FIG. 3F, the exposed
第二實施例的其餘元件如同第一實施例,在此不再贅述。 The remaining elements of the second embodiment are the same as those of the first embodiment, and are not repeated here.
綜上所述,本實施例製作方法的主要特點在於利用濺鍍方式而在樹脂層上形成附著性高的第一金屬層,並利用化學膚鍍方式在第一金屬層上以形成第二金屬層,再利用電鍍形成第三金屬層以覆蓋第二金屬層,並填滿盲孔,且由於第一金屬層提供較佳的表面特性,使得第二金屬層、第三金屬層更加穩固,並於線路蝕刻後可形成線寬/線距小於10um的線路,因而能確實滿足電子元件封裝及電子應用產品對線路板的細線寬/線距的要求。 In summary, the main feature of the manufacturing method of this embodiment is that a first metal layer with high adhesion is formed on the resin layer by sputtering, and a second metal is formed on the first metal layer by chemical skin plating Layer, and then use electroplating to form a third metal layer to cover the second metal layer and fill the blind holes, and because the first metal layer provides better surface characteristics, the second metal layer and the third metal layer are more stable, and After the circuit is etched, a circuit with a line width/line distance of less than 10um can be formed, so that it can truly meet the requirements of electronic device packaging and electronic application products for the fine line width/line distance of the circuit board.
尤其是,第一金屬層包含由容易氧化的銅或鋁所構成的上部金屬層,還包含由用以提高活性的鈦、鉻或鉭所構成的下部金屬層,可改善後續處理的加工性及品質。此外,第一金屬層還可進一步包含由氮化鈦所構成的底部金屬層,位於下部金屬層下,用以接觸內層線路層,使得第一金屬層的整體材料強度以及與內層線路層之間的結合力獲得大幅改善。再者,第二金屬層可當作層間導通層,而第三金屬層可用以增加金屬層的整體厚度,並同時使金屬填滿導通孔。 In particular, the first metal layer includes an upper metal layer composed of easily oxidized copper or aluminum, and a lower metal layer composed of titanium, chromium, or tantalum for improving activity, which can improve the workability and subsequent processing quality. In addition, the first metal layer may further include a bottom metal layer made of titanium nitride, located under the lower metal layer, for contacting the inner circuit layer, so that the overall material strength of the first metal layer and the inner circuit layer The cohesion between them has been greatly improved. Furthermore, the second metal layer can be used as an interlayer conduction layer, and the third metal layer can be used to increase the overall thickness of the metal layer, and at the same time, the metal fills the via hole.
因此,本發明方法所製作的線路板確實具有較高的操作穩定性及可靠度,有效解決習用技術的缺點。 Therefore, the circuit board manufactured by the method of the present invention does have higher operating stability and reliability, and effectively solves the shortcomings of the conventional technology.
由於本發明的技術內並未見於已公開的刊物、期刊、雜誌、媒體、展覽場,因而具有新穎性,且能突破目前的技術瓶頸而具體實施,確實具有進步性。此外,本發明能解決習用技術的問題,改善整體使用效率,而能達到具產業利用性的價值。 Since the technology of the present invention is not found in published journals, periodicals, magazines, media, and exhibition venues, it is novel and can be broken through the current technical bottlenecks for specific implementation, which is indeed progressive. In addition, the present invention can solve the problems of conventional technology, improve the overall use efficiency, and can achieve industrially useful value.
以上所述者僅為用以解釋本發明之較佳實施例,並非企圖據 以對本發明做任何形式上之限制,是以,凡有在相同之發明精神下所作有關本發明之任何修飾或變更,皆仍應包括在本發明意圖保護之範疇。 The above is only for explaining the preferred embodiments of the present invention and is not intended to be In order to limit the present invention in any form, any modifications or changes made to the present invention under the same spirit of the invention should still be included in the scope of protection of the present invention.
S10~S60‧‧‧步驟 S10~S60‧‧‧Step
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