TWI698971B - Package structure - Google Patents

Abstract

A package structure includes a metal substrate, a core structure layer and a package component. The core structure layer is disposed on the metal substrate and has an opening and a patterned conductive layer. The package component is disposed on the metal substrate and located in the opening of the core structure layer. The package component includes a plurality of outer pins, and the outer pins are electrically connected to the patterned conductive layer of the core structure layer. An outer surface of each of the outer pins is flush with a top surface of the patterned conductive layer.

Description

Package structure

The present invention relates to a packaging structure, and more particularly to a packaging structure that can embed packaging components.

When considering the overall thickness of the electronic device or packaging structure, it is necessary to discuss the packaging method of the embedded component. By embedding the components, the package volume can be greatly reduced, and more high-functional components can be put in to increase the layout area of the substrate surface to achieve the goal of thinning the electronic product. Generally speaking, in the conventional packaging technology using embedded components, it is necessary to first form an accommodating groove on the substrate so that the components are arranged in the accommodating groove of the substrate. After that, the step of filling the insulating colloid is performed to make the component buried in the substrate. However, the embedded components often face the problem of poor heat dissipation, which further affects the overall heat dissipation performance of the electronic device or the package structure.

The invention provides a packaging structure, which can embed packaging components and has the effect of reducing the packaging height.

A packaging structure of the present invention includes a metal substrate, a core structure layer and a packaging element. The core structure layer is disposed on the metal substrate and has an opening and a patterned conductive layer. The packaging element is disposed on the metal substrate and is located in the opening of the core structure layer. The package component includes a plurality of external pins, and the external pins are electrically connected to the patterned conductive layer of the core structure layer, and an outer surface of each external pin is aligned with an upper surface of the patterned conductive layer.

In an embodiment of the present invention, the above-mentioned metal substrate has a configuration surface and a groove, the core structure layer is disposed on the configuration surface, and the package component is disposed in the groove, and the configuration surface and a bottom surface of the groove have A height difference.

In an embodiment of the present invention, the bottom surface of the aforementioned groove is a rough surface.

In an embodiment of the present invention, the aforementioned metal substrate has a configuration surface, and the core structure layer and the packaging components are disposed on the configuration surface.

In an embodiment of the present invention, the aforementioned core structure layer includes a dielectric layer located between the patterned conductive layer and the metal substrate.

In an embodiment of the present invention, the above-mentioned packaging component further includes a chip and a packaging compound. The chip has multiple pads. The packaging glue covers the chip and exposes a surface of each pad, wherein the outer pins are arranged on the packaging glue and are respectively connected to the surface of each pad.

In an embodiment of the present invention, the above-mentioned package component further includes a chip holder, a chip, a package compound, and a plurality of wires. The chip is arranged on the chip holder. The package glue covers the chip and the chip holder, wherein the external pins are arranged on the package glue, and the wires are electrically connected between the chip and the external pins.

In an embodiment of the present invention, the aforementioned external pins are electrically connected to the patterned conductive layer of the core structure layer through a plurality of wires.

In an embodiment of the present invention, the aforementioned external pins are structurally and electrically connected to the patterned conductive layer of the core structure layer.

In an embodiment of the present invention, the aforementioned package structure further includes an insulating layer filled between the package element and the opening of the core structure layer.

In an embodiment of the present invention, the aforementioned package structure further includes an adhesive layer disposed between the core structure layer and the metal substrate.

In an embodiment of the present invention, the aforementioned packaging structure further includes a thermally conductive adhesive layer disposed between the packaging element and the metal substrate.

In an embodiment of the present invention, the aforementioned package structure further includes a surface treatment layer disposed on the upper surface of the patterned conductive layer and the outer surface of each external pin.

In an embodiment of the present invention, the above-mentioned package structure further includes a solder mask layer disposed on the core structure layer and at least covering the patterned conductive layer and the outer pins of the package component.

In an embodiment of the present invention, the aforementioned packaging structure further includes an electronic component and a plurality of conductive vias. The electronic components are arranged on the solder mask. The conductive through hole penetrates the solder mask layer and exposes a part of the patterned conductive layer, wherein the electronic component is electrically connected to the patterned conductive layer through a plurality of conductive through holes.

In an embodiment of the present invention, the aforementioned package structure further includes a solder mask layer and a surface treatment layer. The solder mask is disposed on the core structure layer and covers the patterned conductive layer, wherein the solder mask exposes part of the upper surface of the patterned conductive layer. The surface treatment layer is arranged on the upper surface of the patterned conductive layer exposed by the solder mask and the outer surface of each external pin.

Based on the above, in the configuration of the package structure of the present invention, the package component is arranged on the metal substrate and located in the opening of the core structure layer. In this way, the package component is embedded in the core structure layer, and the outer pins of the package component and the patterned conductive layer of the core structure layer are coplanar, thereby reducing the overall package height of the package structure. In addition, the package component is disposed on the metal substrate, and the heat dissipation efficiency of the package component can be improved by the thermal conductivity of the metal substrate.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1 is a schematic cross-sectional view of a package structure according to an embodiment of the invention. Please refer to FIG. 1, the package structure 100A of this embodiment includes a metal substrate 110, a core structure layer 120 and a package component 130. The core structure layer 120 is disposed on the metal substrate 110 and has an opening 122 and a patterned conductive layer 124. The package element 130 is disposed on the metal substrate 110 and located in the opening 122 of the core structure layer 110. The package component 130 includes a plurality of external pins 132, and each of the external pins 132 is electrically connected to the patterned conductive layer 124 of the core structure layer 120. In particular, an outer surface S1 of each outer pin 132 is aligned with an upper surface S2 of the patterned conductive layer 124.

In detail, the metal substrate 110 of this embodiment has a configuration surface 112, and the core structure layer 120 and the package component 130 are respectively disposed on the configuration surface 112. There is an air gap G between the packaging element 130 and the core structure layer 120, which means that the packaging element 130 does not contact the inner wall of the opening 122 of the core structure layer 120. The core structure layer 120 further includes a dielectric layer 126, wherein the dielectric layer 126 is located between the patterned conductive layer 124 and the metal substrate 110. The package component 130 further includes a chip 134 and a package compound 136. The chip 134 has a plurality of pads 1342, and the package compound 136 covers the chip 134 and exposes a surface S3 of each pad 1342. Each external pin 132 is disposed on the packaging compound 136, and is structurally and electrically connected to the surface S3 of each pad 1342, so that the chip 134 can be electrically connected to the core structure layer 120 through the external pins 132 The patterned conductive layer 124. As shown in FIG. 1, the package component 130 of this embodiment is embodied as a flip-chip package component, and the outer pins 132 of the package component 130 are structurally and electrically connected to the patterned conductive layer of the core structure layer 120 124.

1 again, in order to further fix the position of the package element 130, the package structure 100A of this embodiment may include an insulating layer 140, wherein the insulating layer 140 is filled with air between the package element 130 and the opening 122 of the core structure layer 120 Within the gap G, the package component 130 is positioned in the opening 122. Furthermore, the package structure 100A of this embodiment may further include an adhesive layer 150, wherein the adhesive layer 150 is disposed between the core structure layer 120 and the metal substrate 110, and the core structure layer 120 is adhered and fixed to the metal through the adhesive layer 150 On the substrate 110. In addition, in order to increase the heat dissipation effect of the package component 130, the package structure 100A of this embodiment further includes a thermally conductive adhesive layer 160, wherein the thermally conductive adhesive layer 160 is disposed between the package component 130 and the metal substrate 110, and the package component 130 can penetrate The thermally conductive adhesive layer 160 is adhered and fixed on the metal substrate 110, and the package element 130 can quickly transfer the generated heat to the outside through the thermally conductive adhesive layer 160 and the metal substrate 110 in sequence.

In short, in the configuration of the packaging structure 100A of this embodiment, the packaging element 130 is disposed on the metal substrate 110 and located in the opening 122 of the core structure layer 120. In this way, the package component 130 is embedded in the core structure layer 120, and the outer pins 132 of the package component 130 and the patterned conductive layer 124 of the core structure layer 120 are coplanar, thereby reducing the overall package structure 100A. Package height. In addition, the package element 130 is disposed on the metal substrate 110, and the heat dissipation efficiency of the package element 130 can be improved by the thermal conductivity of the metal substrate 110.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiments, and the following embodiments will not be repeated.

2 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. Please refer to FIGS. 1 and 2 at the same time. The package structure 100B of this embodiment is similar to the package structure 100A of FIG. 1. The difference between the two is that the package component 230 of this embodiment is embodied as a wire-bonded package component. In detail, the packaged component 230 of this embodiment includes a die base 231, external pins 232, a die 234, a packaging compound 236, and a plurality of wires 238. The chip 234 is disposed on the chip holder 231, and the wire 238 is electrically connected between the chip 234 and the outer pins 232, and the encapsulant 236 covers the chip 234, the chip holder 231 and the wires 238 and is filled between the outer pins 232 . The outer pins 232 are disposed on the packaging glue 236, and an outer surface S1' of each outer pin 232 is aligned with the upper surface S2 of the patterned conductive layer 124.

3 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. Please refer to FIGS. 1 and 3 at the same time. The package structure 100C of this embodiment is similar to the package structure 100A of FIG. 1. The difference between the two is that the metal substrate 110c of this embodiment further has a groove 114c in which the package element 130 is configured Inside the groove 114c, the disposition surface 112 and a bottom surface 115c of the groove 114c have a height difference H. In detail, the groove 114c of the metal substrate 110c can be used to accommodate a package component 130 with a relatively large thickness, so that the package component 130 can be embedded in the opening 122 of the core structure layer 120 to reach the outer surface S1 of the outer pin 132 It is cut to the upper surface S2 of the patterned conductive layer 124 to reduce the overall package height.

4 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. 3 and 4 at the same time, the package structure 100D of this embodiment is similar to the package structure 100C of FIG. 3, the difference between the two is: the bottom surface 115d of the groove 114d of the metal substrate 110d of this embodiment is embodied as a rough The surface, wherein the rough surface shape is, for example, a rectangular saw-tooth structure, but the present invention is not limited thereto. The bottom surface 115d of the groove 114d of the metal substrate 110d of this embodiment can increase the contact area between the insulating layer 140 and the thermally conductive adhesive layer 160 and the metal substrate 110d to increase the bonding force with the metal substrate 110d, thereby improving insulation The bonding strength between the layer 140, the thermally conductive adhesive layer 160 and the metal substrate 110d.

5 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. 1 and 5 at the same time, the package structure 100E of this embodiment is similar to the package structure 100A of FIG. 1, the difference between the two is: the package structure 100E of this embodiment further includes a surface treatment layer 170, which is configured in the patterning On the upper surface S2 of the conductive layer 124 and on the outer surface S1 of the outer pin 132, the surface treatment layer 170 is, for example, a nickel layer, a gold layer, a silver layer, a nickel-palladium-gold layer or other suitable metals or alloys to prevent The patterned conductive layer 124 and the outer pins 132 are attacked by water and oxygen to cause oxidation.

6 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. 1 and 6 at the same time, the package structure 100F of this embodiment is similar to the package structure 100A of FIG. 1, the difference between the two is: the package structure 100F of this embodiment further includes a solder mask layer 180, which is disposed on the core structure The layer 120 at least covers the patterned conductive layer 124 and the outer pins 132 of the package component 130. In detail, in this embodiment, the solder mask layer 180 covers the patterned conductive layer 124, the dielectric layer 126 exposed by the patterned conductive layer 124, and the outer leads 132 of the package component 130 and the outer leads 132 located thereon. Part of the encapsulation gel 136 between. The solder mask layer 180 can be used to prevent abnormal electrical contact of the patterned conductive layer 124 or the outer pins 132 from causing electrical interference or short circuit.

FIG. 7 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. 1 and 7 at the same time, the package structure 100G of this embodiment is similar to the package structure 100A of FIG. 1, the difference between the two is: the package structure 100G of this embodiment further includes a surface treatment layer 170' and a solder mask Layer 180'. The solder mask 180' is disposed on the core structure layer 120 and covers the patterned conductive layer 124, wherein the solder mask 180' exposes a part of the upper surface S2 of the patterned conductive layer 124. The surface treatment layer 170' is disposed on the upper surface S2 of the patterned conductive layer 124 exposed by the solder mask layer 180' and on the outer surface S1 of each outer pin 132, so as to prevent the patterned conductive layer 124 and the external lead The feet 132 are attacked by water and oxygen to produce oxidation. Each external pin 132 of the package component 130 is electrically connected to the patterned conductive layer 124 of the core structure layer 120 through a wire W. Furthermore, both ends of the wire W are electrically connected to the surface treatment layer 170' disposed on the patterned conductive layer 124 and the pins 132, respectively. In other words, the package component 130 of this embodiment is electrically connected to the patterned conductive layer 124 of the core structure layer 120 through the wire W.

FIG. 8 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. 6 and 8 at the same time, the package structure 100H of this embodiment is similar to the package structure 100F of FIG. 6, the difference between the two is: the package structure 100H of this embodiment further includes an electronic component 190 and a plurality of conductive vias 190A. The electronic component 190 is disposed on the solder mask 180. The conductive via 190A penetrates the solder mask layer 180 and exposes a portion of the patterned conductive layer 124, wherein the electronic component 190 is electrically connected to the patterned conductive layer 124 through the conductive via 190A. Here, the electronic component 190 is, for example, a sensor, a transmitter, a receiver, or other appropriate components, which is not limited herein.

To sum up, in the configuration of the packaging structure of the present invention, the packaging element is configured on the metal substrate and located in the opening of the core structure layer. In this way, the package component is embedded in the core structure layer, and the outer pins of the package component and the patterned conductive layer of the core structure layer are coplanar, thereby reducing the overall package height of the package structure. In addition, the package component is disposed on the metal substrate, and the heat dissipation efficiency of the package component can be improved by the thermal conductivity of the metal substrate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H‧‧‧Packaging structure 110, 110c, 110d‧‧‧Metal substrate 112‧‧ ‧‧Bottom surface 120‧‧‧Core structure layer 122‧‧‧Opening 124‧‧‧Patterned conductive layer 126‧‧‧Dielectric layer 130,230‧‧Packing component 231‧‧‧Chip holder 132,232‧‧‧ External pins 134, 234‧‧‧Chip 1342‧‧‧Pad 136,236‧‧‧Packaging glue 238‧‧‧Wire 140‧‧‧Insulation layer 150‧‧‧Adhesive layer 160‧‧‧Thermal conductive adhesive layer 170, 170'‧‧‧Surface treatment layer 180, 180'‧‧‧Soldering layer 190‧‧‧Electronic component 190A‧‧‧Conductive through hole W‧‧‧Wire H‧‧‧Height difference S1, S1'‧‧ Outside Surface S2‧‧‧Upper surface S3‧‧‧Surface G‧‧‧Air gap

FIG. 1 is a schematic cross-sectional view of a package structure according to an embodiment of the invention. 2 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. 3 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. 4 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. 5 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. 6 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. FIG. 7 is a schematic cross-sectional view of a package structure according to another embodiment of the invention. FIG. 8 is a schematic cross-sectional view of a package structure according to another embodiment of the invention.

100A‧‧‧Packaging structure

110‧‧‧Metal substrate

112‧‧‧Configuration surface

120‧‧‧Core structure layer

122‧‧‧Open

124‧‧‧Patterned conductive layer

126‧‧‧Dielectric layer

130‧‧‧Packaging components

132‧‧‧External pin

134‧‧‧chip

1342‧‧‧Connector

136‧‧‧Packaging gel

140‧‧‧Insulation layer

150‧‧‧Adhesive layer

160‧‧‧Thermal conductive adhesive layer

S1‧‧‧Outer surface

S2‧‧‧Upper surface

S3‧‧‧surface

G‧‧‧Air gap

Claims (16)

A packaging structure includes: a metal substrate; a core structure layer disposed on the metal substrate and having an opening and a patterned conductive layer, wherein the patterned conductive layer has an upper surface away from the metal substrate; and A package component is disposed on the metal substrate and located in the opening of the core structure layer, wherein the package component includes: a chip having a first surface and a second surface opposite to each other, and connecting the first surface and A peripheral surface of the second surface, wherein the second surface faces the metal substrate; a plurality of outer pins, the outer pins have an outer surface away from the metal substrate, and the outer pins and the core The patterned conductive layer of the structural layer is electrically connected, and the outer surface of each of the outer pins is aligned with the upper surface of the patterned conductive layer; and an encapsulant, wherein the encapsulant covers the second part of the chip There is a gap between the two surfaces and the surrounding surface, and between the packaging glue and the core structure layer. According to the package structure described in claim 1, wherein the metal substrate has a configuration surface and a groove, the core structure layer is disposed on the configuration surface, and the package component is disposed in the groove, and the There is a height difference between the disposition surface and a bottom surface of the groove. According to the package structure described in item 2 of the scope of patent application, the bottom surface of the groove is a rough surface. According to the package structure described in claim 1, wherein the metal substrate has a configuration surface, and the core structure layer and the package component are disposed on the configuration surface. According to the package structure described in claim 1, wherein the core structure layer includes a dielectric layer, and the dielectric layer is located between the patterned conductive layer and the metal substrate. According to the package structure described in claim 1, wherein the chip has a plurality of pads, the package glue covers the chip and exposes a surface of each of the pads, wherein the external pins are arranged on the package The glue is connected to the surface of each pad. For the package structure described in claim 1, wherein the package component further includes: a die holder, wherein the chip is disposed on the die holder, the packaging compound covers the chip and the die holder, wherein the outer The pins are arranged on the packaging glue; and a plurality of wires are electrically connected between the chip and the external pins. According to the package structure described in claim 1, wherein the external pins of the package element are electrically connected to the patterned conductive layer of the core structure layer through a plurality of wires. The package structure according to the first item of the scope of patent application, wherein the external pins of the package element are structurally and electrically connected to the patterned conductive layer of the core structure layer. The package structure as described in item 1 of the scope of patent application further includes: an insulating layer filled between the package element and the opening of the core structure layer. The package structure described in item 1 of the scope of patent application further includes: an adhesive layer disposed between the core structure layer and the metal substrate. The package structure as described in item 1 of the scope of patent application further includes: a thermally conductive adhesive layer disposed between the package element and the metal substrate. The package structure described in item 1 of the scope of patent application further includes: a surface treatment layer disposed on the upper surface of the patterned conductive layer and the outer surface of each of the outer pins. The package structure described in item 1 of the scope of patent application further includes: a solder mask layer disposed on the core structure layer and at least covering the patterned conductive layer and the external pins of the package component. As described in item 14 of the scope of the patent application, the package structure further includes: an electronic component disposed on the solder mask; and a plurality of conductive vias penetrating the solder mask and exposing a portion of the patterned conductive layer, the Electronic components are electrically connected to the patterned conductive layer through the conductive through holes. The package structure described in item 1 of the scope of patent application further includes: a solder mask layer disposed on the core structure layer and covering the patterned conductive layer, wherein the solder mask layer exposes a portion of the patterned conductive layer The upper surface; and A surface treatment layer is arranged on the upper surface of the patterned conductive layer exposed by the solder mask layer and the outer surface of each of the outer pins.

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