200929462 九、發明說明： 【發明所屬之技術領域】 ，發明關於-種晶片、晶片製造方法以及晶片封裝結構，並 構以^造種具有高散熱效率之晶片、日日日片封裝結 【先前技術】 # Ϊ年ΐ由於半導體科技快速發展，晶片的功能越來越多變 ϊιίίϊϋ來越小。對於單—晶片來說，越多變化的功能 够訊號傳輸接腳’另―方面’越小尺寸則代表晶片以及 過往高出了許多。因此，晶片散熱技術成為半i 體科技持續發展的重要研究課題。 播，’台料利第1264125號提出—種晶片散熱結 元。：设置虛擬/日片，並在虛擬晶片上再設置散熱單 ❹ 傳遞曰1二時ί生之熱量’能藉由虛擬晶片以及散熱單元有效 ，遞至外界，進而收到良好散熱效果。另外，= =512酬提出另—種晶讀熱綠，其係以電鍍方 形成整合型散熱單元。此整合型散熱料可形i於以 能。‘刀面積而不遮蓋晶片上之接點，並且提供良好的散熱功 、查先前技術所使用之方法，皆於原上設置躺材質以 熱效果。飾’此種增設散_質於^本體外之 封裝整體而言造成了重量增加的缺點，尤其是在使用軟 =。此外，增加材料的方式散 礙。另-方面，增加材料會提升製造成本，對於此種散熱晶= 200929462 量產也有不利的影響。200929462 IX. Description of the Invention: [Technical Fields of the Invention] The invention relates to a wafer, a wafer manufacturing method, and a chip package structure, and is configured to produce a wafer with high heat dissipation efficiency, and a solar wafer package junction. 】 # Ϊ年ΐ Due to the rapid development of semiconductor technology, the function of the chip is getting smaller and smaller. For a single-wafer, the more varied functions are the signal transmission pins. The smaller the size, the more representative the wafer and the higher the past. Therefore, wafer heat dissipation technology has become an important research topic for the continued development of semiconductor technology. Broadcast, 'Taiwan Lee No. 1264125 proposed a kind of wafer heat dissipation. : Set the virtual/day film and set the heat sink on the virtual chip. 曰 Passing the heat of the 曰1 2 ί can be effectively transmitted to the outside world by the virtual chip and the heat sink unit, and then receive a good heat dissipation effect. In addition, == 512 rewards another type of crystal read hot green, which is formed by electroplating to form an integrated heat sink unit. This integrated heat sink is configurable. ‘The knife area does not cover the contacts on the wafer, and provides good heat dissipation. Check the methods used in the prior art. The decoration of the package is a disadvantage of weight increase, especially in the use of soft =. In addition, the way in which materials are added is diminished. On the other hand, increasing the material will increase the manufacturing cost, and it will also have an adverse effect on the mass production of the crystal = 200929462.
【發明内容J 因此，本發明之一範疇在於 — 量的前提下具有良好的散熱效果。，、一種晶片，其可在不增加重 j-具體實施例，本發明之晶 一面之第二面。第—面具有功能區，可—面以及相對於第 板。第二面上以侧方式形成散熱結構於觸基材或電路 可以是凸點、凹點•、凸出圖樣、凹陷圖像，該散熱結構 其目的是增加散熱面積以加速散熱述結構之組合， 形成於第二面，降低了晶片的重量。；散'、、、、，、吉構係以蝕刻方式 ^ 體實施例’本發明之晶片係以打線接合_ bonding)封裝製程封裝於基材上。基材接觸晶片第二面之接觸面 上形成辅助結構，並當晶片接觸基材時散熱結構可嵌合輔助結 構。因此，藉由散熱結構與基材較大之接觸面積，可有效將晶片 之熱量傳導至基材以散熱。 θθ 本發明之另一範疇在於提供一種晶片製造方法，其製造出的 晶片不需要增設額外的散熱材質即可達到良好的散熱效果。 根據一具體實施例，本發明之晶片製造方法係用以製造具有 第一面以及相對於第一面之第二面的晶片，其中，第一面上設置 有功能區。於本具體實施例中，晶片製造方法包含下列步驟：蝕 刻第二面以形成散熱結構。於實務中，散熱結構可以是凸點、凹 200929462 點、凸出圖樣、凹陷圖像或是前述結構之組合，其目的是增加散 熱面積以加速散熱。 關於本發明之優點與精神可以藉由以下的發明詳述及所附圖 式得到進一步的暸解。 【實施方式】 Ο e 言月參閱圖一，圖一係繪示根據本發明之一具體實施例之㈢ 1的側視圖。如圖一所示，晶片1具有第一面1〇以及第=面 12。第一面1〇包含功能區(未顯示）’可用以電性接觸基材或^路 板。第二面12係經由蝕刻而於其上形成散熱結構12〇。 於本具體實施例中，散熱結構12〇之主要作用，係增加 之表面積以增進散熱效能。請參閱圖二A至圖二D，圖二A、 及圖二D係繪示圖-之晶片1之散熱結構⑽的上視圖， 而圖一 C則係圖二B之晶片i之散熱結構12〇 所示，散熱結構120之外觀為^= 的外觀可具林_外型及圖樣，並不限G上述且 =所f述者’端看使用者或設計者需求而財。另外，ς 了3 f ΐ對2Ξί增片隹1之錄熱面積之外，於實務中:、還可： 速逸散晶片熱=__少晶片1之厚度，藉此能加 咖恤1^形|式_製程㈣獅㈣或者雷射加工製程_ 8 200929462 曰片t :據本發明之一具體實施例之 ^ 所示’晶片封裝結構2係使SUMMARY OF THE INVENTION Therefore, one aspect of the present invention is that it has a good heat dissipation effect on the premise of quantity. , a wafer which can be used without adding a weight to the second side of the crystal side of the present invention. The first face has a functional area, which can be face-to-face and relative to the first plate. Forming the heat dissipation structure on the second surface in a side manner on the contact substrate or the circuit may be a bump, a pit, a convex pattern, a concave image, and the heat dissipation structure is designed to increase the heat dissipation area to accelerate the combination of the heat dissipation structure. Formed on the second side, the weight of the wafer is reduced. The dispersion of the ',,,, and ji structures is etched. The embodiment of the invention is packaged on a substrate by a bonding process. An auxiliary structure is formed on the contact surface of the substrate contacting the second side of the wafer, and the heat dissipation structure can be fitted to the auxiliary structure when the wafer contacts the substrate. Therefore, by the large contact area of the heat dissipation structure and the substrate, the heat of the wafer can be efficiently conducted to the substrate to dissipate heat. Θθ Another scope of the present invention is to provide a wafer manufacturing method which can produce a wafer which does not require an additional heat dissipating material to achieve a good heat dissipation effect. According to one embodiment, the wafer fabrication method of the present invention is for fabricating a wafer having a first side and a second side relative to the first side, wherein the first side is provided with a functional area. In this embodiment, the wafer fabrication method includes the steps of etching the second side to form a heat dissipation structure. In practice, the heat dissipation structure may be a bump, a concave 200929462 point, a convex pattern, a concave image, or a combination of the foregoing structures, the purpose of which is to increase the heat dissipation area to accelerate heat dissipation. The advantages and spirit of the present invention will be further understood from the following detailed description of the invention. [Embodiment] Referring to Figure 1, Figure 1 is a side view showing (c) 1 according to an embodiment of the present invention. As shown in Fig. 1, the wafer 1 has a first face 1 〇 and a = face 12 . The first side 1 〇 contains a functional area (not shown) that can be used to electrically contact the substrate or the board. The second surface 12 is formed with a heat dissipation structure 12A thereon by etching. In this embodiment, the primary function of the heat dissipation structure 12 is to increase the surface area to enhance heat dissipation. Referring to FIG. 2A to FIG. 2D, FIG. 2A and FIG. 2D are a top view of the heat dissipation structure (10) of the wafer 1 of the drawing, and FIG. 1C is a heat dissipation structure 12 of the wafer i of FIG. As shown in the figure, the appearance of the heat dissipation structure 120 is ^_, and the appearance of the heat dissipation structure 120 can be _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In addition, ς 3 f ΐ Ξ 2 Ξ 增 增 增 隹 之 之 之 之 之外 之外 之外 之外 之外 , , , , , , , , 之外 之外 之外 之外 于 之外 于 于 之外 之外 之外 于 于 于 之外 于 于 于 于 于 于 于 于 于Shape_式_process (four) lion (four) or laser processing process _ 8 200929462 tt t: according to a specific embodiment of the present invention ^ shown in the chip package structure 2
22上而成。於本具體實施例中，晶片2()包含^_2G 21面ΐϊ。含功能區(未顯示），可用以電性接觸基材 2並且，曰曰片20之苐一面200於封裝後密封於基材22上。另 -方面’晶片20之第二面202則暴露於外界空氣並且於 二面2G2上侧以形成散熱結構2G4 ★之 藉此，晶片20於操作時產生之熱量曰可有 界二軋中，以幫助晶月20散熱。此外，於本具體實施 芙 =2還包含絕緣層220、凸塊班、導線層故以及樹脂^ 神值ίί體實施例之晶片第二面以及周邊區域可進-效果電ΐ。由於導電膠本身的良好熱傳導 — ❹Made up on 22. In this embodiment, the wafer 2() comprises a ^2G 21 facet. A functional zone (not shown) is provided for electrically contacting the substrate 2 and a side 200 of the batt 20 is sealed to the substrate 22 after encapsulation. In another aspect, the second side 202 of the wafer 20 is exposed to the outside air and is formed on the upper side of the two sides 2G2 to form the heat dissipation structure 2G4. The heat generated by the wafer 20 during operation can be bounded by two Help Jingyue 20 to dissipate heat. In addition, in the present embodiment, the second surface of the wafer and the peripheral region of the insulating layer 220, the bumping layer, the wiring layer, and the resin layer can be further advanced. Good heat transfer due to the conductive paste itself - ❹
構3包含晶片3g以及基材32。圖三c雜4中日日片曰封H 上崎_，射，“ 3〇 bonding)封裝製程封裝至基材32上。如圖三B所示， :列:二晶片3〇包含第一面300以及第二面302，面 ==電性接觸基材32之功能區(未顯示)，第h 接觸區322，並且，接娜322接觸晶片30之 2面由餘刻巧成辅助結構324 ’當接觸區322與第 ~Z 才接觸時(如圖三C所示），散熱結構304 I&由梦笫餅 準裝程嵌合辅助結構324，並且，打線部分3H 〇 之功能區⑽基材32。齡散諸構觸 9 200929462 耐核地傳導至 結細之動也 辅助^ 324^^1 兩具體實施例中’散熱結構2G4、3〇4以及 t:l：4 4^4Tme(wet etchtag)' 形成。 製耘細r machining)或其它適當的製程而 晶片之ί 一面頁=的^^月之晶片散熱結構，亦可安置於 面。嘖夂者圖-η国散”、、、、，°構可與功能區位於晶片之同一表 施例:晶=構 例中，進-步對第—面3G。於本具體實施 一面300上之散熱結構3〇4 ;更由位於第 中，亦可只姓刻第一 ® 3〇〇 曰片散熱。當然，於實務 散熱結構3〇4。請注意，於實：用刻;:片：=== ::情況而被設置於一位置，而 製造發:ϊ:實施例之晶片 ί法ir=有良好散熱效果之么 ί第置功能區;接著’於步…， 狀外’於實際剌中，^進-i 個第一面進盯侧以減少晶月之厚度，加速逸散晶片表面之 200929462 此外散熱結構係藉由、屋式飿刻製程(wetetc油祕）、乾式餘 4 t程(dry etching)或者雷射加工製程(lasermachining)而形成。The structure 3 includes a wafer 3g and a substrate 32. Figure 3, C, 4, Japanese, Japanese, Japanese, Japanese, H, Saki, _, ", 3" bonding) package process package onto the substrate 32. As shown in Figure 3B, the column: the second wafer 3 〇 contains the first side 300 and the second side 302, the surface == electrically contacting the functional area of the substrate 32 (not shown), the hth contact area 322, and the two sides of the contact 322 contacting the wafer 30 are made up of the auxiliary structure 324 ' When the contact region 322 is in contact with the first ~Z (as shown in FIG. 3C), the heat dissipation structure 304 I& is assembled by the monk cake assembly auxiliary structure 324, and the functional portion (10) of the wire bonding portion 3H is used. 32. Age-dissipating structure 9 200929462 Resistance to nuclear conduction to the fine movement is also assisted ^ 324 ^ ^ 1 Two specific examples in the 'heat dissipation structure 2G4, 3 〇 4 and t: l: 4 4 ^ 4Tme (wet etchtag ) 'Form. 耘 r r machining) or other appropriate process and wafer 一面 one page = ^ ^ month of the chip heat dissipation structure, can also be placed in the surface. 啧夂 图 - η η η η η η η η η η η The structure can be located in the same table as the functional area of the wafer: crystal = configuration, step-to-surface 3G. In this embodiment, the heat dissipation structure on the side 300 is 3〇4; it is located in the middle, or it can be cooled only by the first ® 3〇〇 曰. Of course, in the practical heat dissipation structure 3〇4. Please note that in the real: use engraved;: slice: === :: the situation is set in a position, and the manufacturing hair: ϊ: the wafer of the embodiment ί ir = have a good heat dissipation effect ί the first functional area Then, 'in step..., outside' in the actual ,, ^in-i first side into the marking side to reduce the thickness of the crystal moon, accelerate the surface of the fugitive wafer 200929462, the heat dissipation structure is by the house It is formed by engraving process (wetetc oil secret), dry dry 4 t (dry etching) or laser machining process (lasermachining).
^參關五’圖五雜示根據本發明之另—具體實施例 ϋΓί的步驟流頻。如圖五所示’本具體實施例之晶片製 S30 Φ目上—具體實施例’進—步包含下列步驟：於步驟 觸.m製基材；於步驟S32巾’將功能區與基材電性接 t，，於步驟S34 *，以覆晶薄膜( J ίί 於基材上。因此，晶片之第二面以及散熱二Ϊ e ❹ 積、:/中’並且藉由散熱結構能增加與外界空氣之接觸面 助曰於ΐ作時產生之熱量可有效地傳導至空氣中，進而幫 二導二本整身體的=導咖 或軟負整f具有良好散熱率並且其重量不會造成軟性基板 片製繪示根據本發明之另—具體實施例之晶 方法進-本具體實施狀晶片製造 S42中，蝕刻美姑之一品卜驟S4()中，製備一基材；於步驟 構；於步驟S4：中，散熱結構相對應之輔助結 鼓合辅助m 狀接親，並域熱結構 辅助結構間且有較大的j二因此’晶片之散熱結構與基板之 地傳導至基材中，進的而面積’曰使曰曰^於操=乍時產生之熱量可有效 驟，係與上述具想實施其他步 11 200929462 兩具體實施例$，散熱結構以及辅助結構可 ί ί ίη界空氣或基材，因此該晶片具有良好的散熱效 ❺ ❹ 12 200929462 【圖式簡單說明】 圖-係繪和艮據本發明之一具體實施例之晶片的侧視圖。 圖二八係繚示圖一之晶片之散熱結構的上視圖。 圖二B係繪示圖一之晶片之散熱結構的上視圖。 圖C貝J係圖一 b之晶片之散熱結構沿著〇_〇先線的剖面[Parameters 5] Figure 5 shows the flow of steps in accordance with another embodiment of the present invention. As shown in FIG. 5, the wafer of the embodiment of the present invention has the following steps: the substrate is touched in the step; the substrate is electrically charged in the step S32. The connection is t, in step S34*, to form a flip chip (J ίί on the substrate. Therefore, the second side of the wafer and the heat dissipation Ϊ e ❹ , : / 中 ' and by the heat dissipation structure can increase the external The contact surface of the air helps the heat generated during the operation to be effectively transmitted to the air, thereby helping the two guides to have a good heat dissipation rate and the weight does not cause a soft substrate. The invention provides a substrate according to another embodiment of the present invention, and in the wafer manufacturing process S42 of the specific embodiment, a substrate is prepared by etching a film of S. s. In S4: the auxiliary structure of the heat dissipation structure is matched with the auxiliary m-shaped contact, and the auxiliary structure of the domain thermal structure is provided with a larger j. Therefore, the heat dissipation structure of the wafer and the ground of the substrate are conducted to the substrate. And the area '曰 曰 于 ^ in the operation = 乍 when the heat can have And the other embodiments of the above-mentioned steps 11 200929462, the heat dissipation structure and the auxiliary structure can be used to heat the air or the substrate, so the wafer has good heat dissipation effect ❹ 12 200929462 [Simplified illustration Figure 2 is a side view of a wafer according to an embodiment of the present invention. Figure 28 is a top view of the heat dissipation structure of the wafer of Figure 1. Figure 2B is a diagram showing the heat dissipation of the wafer of Figure 1. The top view of the structure. Figure C is a section of the heat dissipation structure of the wafer of Figure B along the 〇 〇 〇 line
圖二D係繪示圖一之晶片之散熱結構的上視圖。 示咅A騎示根據本㈣之—具體實補之晶片封I结構的 =B係♦示根據本發明之另—具體實施例之晶片封裝結構 的不思圖。 晶片封裝至紐上的示意圖。 处姓示根據根據本發明之另一具體實施例之晶片封裝 、、吉構的示意圖。 驟流S係繪示根據本發明之—具體實補之晶讀造方法的步 步驟、示根據本㈣之另—具體實補之晶片製造方法的 步驟示根據本發明之另-具體實施例之晶片製造方法的 【主要元件符號說明】 13 200929462 1、20、30:晶片 10、200、300 :第一面 12、202、302 :第二面 120、204、304 :散熱結構 2、3 :晶片封裝結構 22、32 :基材 .220 :絕緣層 222 :凸塊 224 :導線層 226 :樹脂層 320 :第三面 322 :接觸區 ❹ 324 :輔助結構 34 :打線部分 SI、S2 :步驟流程 S40〜S46 :步驟流程 S30〜S34 :步驟流程 S10、S12、S20、S22 :步驟流程 ❹ 14Figure 2D is a top view showing the heat dissipation structure of the wafer of Figure 1. The display of the wafer package structure according to another embodiment of the present invention is shown in Fig. A. Schematic diagram of the chip package onto the button. The name of the wafer package according to another embodiment of the present invention is shown. The flow S is a step of the crystal read method according to the present invention, and the steps of the wafer manufacturing method according to the fourth embodiment of the present invention are shown in accordance with another embodiment of the present invention. [Main component symbol description] of wafer manufacturing method 13 200929462 1, 20, 30: wafer 10, 200, 300: first surface 12, 202, 302: second surface 120, 204, 304: heat dissipation structure 2, 3: wafer Package structure 22, 32: substrate .220: insulating layer 222: bump 224: wire layer 226: resin layer 320: third surface 322: contact region 324 324: auxiliary structure 34: wire bonding portion SI, S2: step flow S40 ~S46: Steps S30 to S34: Steps S10, S12, S20, S22: Step Flow ❹ 14