TWI640051B - Semiconductor processing method, apparatus and control device thereof - Google Patents

Abstract

A semiconductor process includes: performing a first process step on a first wafer; and after completing the first process step, acquiring first uncorrectable error information according to actual surface topography information of the first wafer; Adjusting process parameters of the first process step according to the first uncorrectable error information. The disclosure further proposes a process apparatus and a control device suitable for use in the semiconductor process.

Description

Semiconductor process and its process equipment and control device

The present disclosure relates to a semiconductor process and its process equipment and control device, and more particularly to a semiconductor process and a process device and a control device thereof for adjusting process parameters by feedback of uncorrectable errors to improve process yield.

In semiconductor processes, wafer irregularities caused by various possible factors can cause defects in wafer surface topography. This problem is more serious at the edge of the wafer, and may be problematic in the steps of the Back End Of Line (BEOL) process. For example, under-polish or over-polish may occur in the Chemical-Mechanical Polishing (CMP) step, causing problems in defocusing of subsequent lithography processes. Therefore, monitoring and improving the surface topography of the wafer edge can improve the wafer yield. However, current detection techniques have problems such as insufficient coverage, low sensitivity and sampling rate, and excessive feedback time.

The present disclosure provides a semiconductor process, including: performing a first process step on a first wafer; and after completing the first process step, obtaining a first non-accuracy according to actual surface topography information of the first wafer Non-correctable error (NCE) information; and adjusting a recipe parameter of the first process step according to the first uncorrectable error information.

In an embodiment, the semiconductor process further includes: performing the first process step on the second wafer according to the adjusted process parameter.

In an embodiment, the semiconductor process further includes: performing a second process step on the first wafer; and after obtaining the second process step, obtaining the actual surface topography information according to the first wafer The second uncorrectable error information; and adjusting the process parameters of the second process step according to the second uncorrectable error information.

In an embodiment, the step of acquiring the first uncorrectable error information comprises: scanning the first wafer to obtain the actual surface topography information of the first wafer; and, according to the actual surface The first uncorrectable error information is obtained by the difference between the topographical information and the expected surface topography information.

In one embodiment, the expected surface topography information is derived from the process parameters of the first process step.

In one embodiment, the process parameters include a scan profile of the process device relative to the wafer.

The disclosure further provides a semiconductor process control device including an input/output unit, a storage unit, and a processor. The input/output unit is configured to receive actual surface topography information of the wafer acquired after the wafer completes the processing step. The storage unit is configured to store process parameters of the process step. Furthermore, the processor is coupled to the input/output unit and the storage unit. The processor is configured to obtain uncorrectable error information according to a difference between the actual surface topography information and expected surface topography information obtained from the process parameter, and adjust the according to the uncorrectable error information Process parameters for the process steps.

In one embodiment, the control device is coupled to the process device for performing the process step on the wafer, and the process parameters include scan setting parameters of the process device relative to the wafer.

The present disclosure further provides a semiconductor process apparatus including a process device, a detection device, and a control device. The process device is configured to perform a processing step on the wafer. The detecting device is configured to acquire actual surface topography information of the wafer after the process step is completed. The control device includes an input/output unit, a storage unit, and a processor. The input/output unit is configured to receive the actual surface topography information. The storage unit is configured to store process parameters of the process step. Furthermore, the processor is coupled to the input/output unit and the storage unit. The processor is configured to obtain uncorrectable error information according to a difference between the actual surface topography information and expected surface topography information obtained from the process parameter, and adjust the according to the uncorrectable error information Process parameters for the process steps.

In one embodiment, the process parameters include scan setting parameters of the process device relative to the wafer.

Based on the above, the present disclosure acquires uncorrectable error information by detecting the surface topography of the wafer formed by the process step, and feeds the uncorrectable error information to the detection process for instantly adjusting the process parameters of the process step. In this way, the uncorrectable error generated by the process step is reduced, the process error is instantaneously feedbacked, and the in-line monitoring of the semiconductor process is realized, and the process yield can be effectively improved. On the other hand, the uncorrectable error information obtained by detecting the surface topography of the wafer can cover most of the wafer surface, and has good detection coverage, sensitivity, and sampling efficiency.

The above described features and advantages of the invention will be apparent from the following description.

The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of the components and configurations described below are for the purpose of conveying the disclosure in a simplified manner. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming the second feature over the first feature or on the first feature may include an embodiment in which the second feature is formed in direct contact with the first feature, and may also include a second feature and Embodiments may be formed with a feature such that the second feature may not be in direct contact with the first feature. In addition, the present disclosure may use the same component symbols and/or letters in the various examples to refer to the same or similar components. The repeated use of the component symbols is for simplicity and clarity and does not represent a relationship between the various embodiments and/or configurations themselves to be discussed.

In addition, for ease of description, the relationship between one component or feature illustrated in the drawings and another component or feature may be used herein, for example, "under", "below", "lower". Spatial relative terms for "on", "above", "upper" and similar terms. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the elements in use or operation. The device can be otherwise oriented (rotated 90 degrees or at other orientations), while the spatially relative terms used herein can be interpreted accordingly.

In addition, the embodiments disclosed hereinafter do not necessarily describe all of the elements or features that are present in the structure. For example, a plural form of a single element may be omitted from the drawings, and a description of a single element will be sufficient to convey a dissimilarity in the various embodiments. Moreover, the method embodiments discussed herein can be performed in a particular order; however, other embodiments can be performed in any logical order.

1 is a block diagram of a semiconductor process device in accordance with an embodiment of the present disclosure. As shown in FIG. 1, the semiconductor process apparatus 100 includes a process device 110, a detection device 120, and a control device 130. The process device 110 is configured to perform a processing step on the wafer. The detecting device 120 is configured to acquire actual surface topography information of the wafer after the process step is completed. The control device 130 acquires the uncorrectable error information according to the actual surface topography information of the wafer, and adjusts the process parameters of the process step according to the acquired uncorrectable error information.

More specifically, the process device 110 of the present embodiment is, for example, at least one of a plurality of semiconductor processing steps, such as thin film deposition, chemical mechanical polishing, or lithography, for performing various semiconductor structure fabrication and lithography steps. Various processing or measuring devices including coating, calibration, exposure, baking, developing, patterning, polishing, and the like are included. In other words, the wafers mentioned herein are, for example, basic semiconductors (for example, germanium, polycrystalline germanium, amorphous germanium, germanium, and diamond), compound semiconductors (for example, tantalum carbide and gallium arsenide), and alloy semiconductors (for example, germanium). A semiconductor wafer (or wafer) of germanium, gallium arsenide, indium aluminum arsenide, aluminum gallium phosphide, and gallium indium phosphide, or any combination thereof. In addition, as the process steps progress, a complete or partial semiconductor device structure may have been formed on the wafer.

Moreover, the uncorrectable error information includes, for example, the location and extent of one or more uncorrectable errors on the wafer. For example, the degree of uncorrectable error is, for example, the difference between the actual surface topography information at the same location of the wafer and the expected surface topography information from the process parameters. For example, in the chemical mechanical polishing step or the exposure operation in the lithography step, the process parameters are, for example, scan setting parameters of the processing device relative to the wafer, for example, the stage carrying the wafer is translated relative to the grinding tool or the exposure light source, The movement parameters of the rotation or pitch motion.

In this embodiment, the wafer may be scanned by the detecting device 120 to obtain actual surface topography information of the wafer. The detection device 120 can include an imaging element, such as a laser source or other wavelength source, for projecting a beam of a particular wavelength above or below a different location on the surface of the wafer. Then, depending on the time or reflection characteristics of the beam reflected back from different locations on the wafer surface, such as the intensity of the reflected light, the height of the wafer at various locations can be determined.

Moreover, in some embodiments, the first beam can be emitted to a first location on the wafer to measure the height of the wafer at the first location, and the focus of the source is adjusted to focus the beam on the wafer. Two positions to measure the height of the wafer in the second position. This action can be continued until the height of enough locations on the wafer is determined. In some embodiments, the aforementioned actions may be performed on more than 20,000 locations to determine the height of each location. Thereby, the actual surface topography information of the wafer can be obtained. And, comparing the actual surface topography information of the wafer with the expected surface topography information obtained from the process parameters to obtain the uncorrectable error information of the entire wafer.

2 is a block diagram of the aforementioned control device 130 in accordance with an embodiment of the present disclosure. As shown in FIG. 2, the control device 130 includes an input/output unit 132, a storage unit 134, and a processor 136. The input/output unit 132 can receive the actual surface topography information from the detection device 120 via a bus 138. The storage unit 134 is coupled to the bus bar 138 and is configured to store process parameters 134a of the process steps, such as scan setting parameters of the process device relative to the wafer. In some embodiments, the storage unit 134 can also be configured to store the actual surface topography information 134b received by the input/output unit 132. In fact, the storage unit 134 can be of any possible type, such as computer readable media, including: floppy disk, floppy disk, hard disk, magnetic tape, any magnetic medium, CD-ROM, any optical medium, punch card (punch) Card), paper tape, any physical medium with holes, random access memory, programmable read-only memory, eraseable programmable read-only memory, flash erasable programmable read-only memory, Any memory chip or cassette, carrier, or any other medium that can be read by a computer.

The processor 136 is, for example, a microprocessor, a dedicated integrated circuit, or other suitable logic element, and is coupled to the input/output unit 132 and the storage unit 134 via the bus bar 138 to be based on the actual surface topography information. The uncorrectable error information is obtained from the difference of the expected surface topography information obtained from the process parameter, and the control signal is output to the process device 110 according to the uncorrectable error information to adjust the process parameters of the process step.

3 is a flow chart of a semiconductor process in accordance with an embodiment of the present disclosure, which illustrates several common steps in a wafer post-process to illustrate the method of implementing on-line real-time monitoring. Of course, the multiple steps may be performed in other sequences in other embodiments, or some of the steps may be omitted, or other steps may be inserted.

As shown in FIG. 3, the wafer post-stage process may perform steps such as thin film deposition 310 of copper metal or other materials, grinding 320 (eg, chemical mechanical polishing), lithography 330, etching 350, and cleaning 360. In addition, for example, after the lithography 330, the wafer can be inspected 340, wherein the actual surface topography information after the wafer completes the lithography 330 is measured, for example, by the aforementioned detecting device 120. And, the uncorrectable error information is obtained according to the actual surface topography information, so as to feed back the uncorrectable error information to a previous step such as grinding 320 or lithography 330, thereby adjusting the process parameters of the process step. At this time, the process device 110 shown in FIG. 1 is, for example, a device for performing steps such as polishing 320 or lithography 330, and the process parameters adjusted are, for example, scan setting parameters of the process device relative to the wafer, such as a carrier wafer. The movement parameters of the stage relative to the grinding tool or the exposure source for translational, rotational or pitching motion.

By the foregoing method, the process parameters of the process device can be optimized, so that the next wafer can obtain an actual surface topography closer to the expected surface topography after performing the process step, and reduce the uncorrectable error.

4 illustrates the steps of performing on-line instant monitoring and feedback in a semiconductor process such as that shown in FIG. 3 by, for example, semiconductor process device 100. First, as shown in step 410, a first process step is performed on the wafer. Here, the first process step is, for example, the steps of polishing 320 or lithography 330 shown in FIG. 3.

Then, after the first process step is completed, as shown in step 420, the first uncorrectable error information is obtained according to the actual surface topography information of the wafer. Figure 5 further illustrates the specific flow of this step. As shown in step 510, the wafer is scanned by the detecting device 120 as shown in FIG. 1 to obtain actual surface topography information of the wafer. At this time, the control device 130 shown in FIG. 2 can receive the actual surface topography information from the detecting device 120 by the input/output unit 132 and store it in the storage unit 134. Then, proceeding to step 520, the processor 136 as shown in FIG. 2 can obtain the first non-accuracy according to the difference between the actual surface topography information and the expected surface topography information obtained by pre-storing the process parameters of the storage unit. Correct the error information.

Thereafter, as shown in step 430 of FIG. 4, the process parameters of the first process step are adjusted according to the first uncorrectable error information. At this time, the processor 136 can output the control signal to the processing device 110 according to the first uncorrectable error information to adjust the process parameters of the first process step. For example, the scan setting parameters of the process device 110 relative to the wafer, such as the movement parameters of the stage carrying the wafer relative to the polishing tool or the exposure source, are translated, rotated, or tilted.

FIG. 6 illustrates steps of a semiconductor process in accordance with another embodiment of the present disclosure. As shown in FIG. 6, after the steps 410-430 of the online instant monitoring and feedback shown in FIG. 4 are completed, the process parameters of the first process step have been adjusted. Thereafter, as shown in step 610, a first process step is performed on another wafer that subsequently enters the process device 110 according to the adjusted process parameters. In this way, the other wafer can be made to obtain an actual surface topography closer to the expected surface topography after performing the process step, and reduce the uncorrectable error.

FIG. 7 illustrates steps of a semiconductor process in accordance with yet another embodiment of the present disclosure. As shown in FIG. 7, after the steps 410-430 of the online real-time monitoring and feedback shown in FIG. 4 are completed or at the same time, the subsequent second processing steps may be performed on the wafer as shown in step 710. Here, it is also possible to select online on-line monitoring and feedback of the second process step in the same way. That is, as shown in step 720, after the second process step is completed, the second uncorrectable error information is obtained according to the actual surface topography information of the wafer. And, as shown in step 730, the process parameters of the second process step are adjusted according to the second uncorrectable error information. For the specific implementation of steps 720 and 730, reference may be made to the foregoing descriptions of steps 420 and 430, and details are not described herein again.

In other words, the embodiments disclosed herein are illustrative of several of a series of semiconductor fabrication steps. In fact, the process steps applicable to the technical solution of the present disclosure are not limited thereto. Those skilled in the art, after considering the disclosure, may choose to apply the disclosed technical solution to specific or even all possible semiconductor processing steps to immediately feedback the process results and adjust the process parameters of the previous process steps to achieve Online real-time monitoring of the entire process or specific steps of the semiconductor process to improve process yield.

In summary, the present disclosure acquires uncorrectable error information by detecting the surface topography of the wafer formed by the process step, and feeds the uncorrectable error information to the detection process for instantly adjusting the process parameters of the process step. Since the detection of uncorrectable errors can cover most of the wafer surface and perform inspections of a larger area than known inspection tools, good detection coverage can be provided. In addition, the detection of uncorrectable errors is also more sensitive and efficient than the detection by known detection tools.

In addition, since the present disclosure provides immediate feedback and adjustment of process parameters by uncorrectable errors between semiconductor process steps, on-line monitoring of semiconductor processes can be achieved. Compared with the detection that is known to be carried out at the end of the process, it takes a month or more to feed back the process error to the process step. The technical solution of the present disclosure can quickly feedback the process error to the front-end process by means of real-time monitoring. And can effectively improve the process yield.

An embodiment of the present invention provides a semiconductor process including: performing a first process step on a first wafer; and after acquiring the first process step, obtaining a first image according to actual surface topography information of the first wafer Uncorrectable error information; and adjusting process parameters of the first process step according to the first uncorrectable error information.

Another embodiment of the present invention provides a semiconductor process control apparatus including an input/output unit, a storage unit, and a processor. The input/output unit is configured to receive actual surface topography information of the wafer acquired after the wafer completes the processing step. The storage unit is configured to store process parameters of the process step. Furthermore, the processor is coupled to the input/output unit and the storage unit. The processor is configured to obtain uncorrectable error information according to a difference between the actual surface topography information and expected surface topography information obtained from the process parameter, and adjust the according to the uncorrectable error information Process parameters for the process steps.

Another embodiment of the present invention provides a semiconductor process apparatus including a process device, a detection device, and a control device. The process device is configured to perform a processing step on the wafer. The detecting device is configured to acquire actual surface topography information of the wafer after the process step is completed. The control device includes an input/output unit, a storage unit, and a processor. The input/output unit is configured to receive the actual surface topography information. The storage unit is configured to store process parameters of the process step. Furthermore, the processor is coupled to the input/output unit and the storage unit. The processor is configured to obtain uncorrectable error information according to a difference between the actual surface topography information and expected surface topography information obtained from the process parameter, and adjust the according to the uncorrectable error information Process parameters for the process steps.

The features of several embodiments are summarized above, and those of ordinary skill in the art will be able to better understand the aspects of the disclosure. It should be understood by those of ordinary skill in the art that the present disclosure may be used as a basis for designing or modifying other processes and structures to achieve the same objectives and/or the same advantages of the embodiments described herein. It should be understood by those skilled in the art that this equivalent configuration is not to be construed as a departure from the spirit and scope of the disclosure, and Make various changes, substitutions, and changes.

100‧‧‧Semiconductor process equipment

110‧‧‧Processing device

120‧‧‧Detection device

130‧‧‧Control device

132‧‧‧Input/output unit

134‧‧‧ storage unit

134a‧‧‧Process parameters

134b‧‧‧ Actual surface topography information

136‧‧‧ processor

138‧‧‧ busbar

310~360, 410~430, 510~520, 610, 710~730‧‧‧ steps

1 is a block diagram of a semiconductor process device in accordance with an embodiment of the present disclosure. 2 is a block diagram of a control device in accordance with an embodiment of the present disclosure. 3 is a flow chart of a semiconductor process in accordance with an embodiment of the present disclosure. 4 illustrates steps of performing on-line monitoring and feedback in a semiconductor process in accordance with an embodiment of the present disclosure. FIG. 5 further illustrates a specific flow of step 420 of FIG. 4. FIG. 6 illustrates steps of a semiconductor process in accordance with another embodiment of the present disclosure. FIG. 7 illustrates steps of a semiconductor process in accordance with yet another embodiment of the present disclosure.

Claims (10)

A semiconductor process includes: performing a first process step on a first wafer; and after completing the first process step, obtaining a first uncorrectable error according to actual surface topography information of the first wafer (non- Corrective error) information; and adjusting a recipe parameter of the first process step according to the first uncorrectable error information. The semiconductor process of claim 1, further comprising: performing the first process step on the second wafer according to the adjusted process parameter. The semiconductor process of claim 1, further comprising: performing a second process step on the first wafer; after completing the second process step, obtaining the actual surface topography information according to the first wafer a second uncorrectable error information; and adjusting a process parameter of the second process step according to the second uncorrectable error information. The semiconductor process of claim 1, wherein the step of acquiring the first uncorrectable error information comprises: scanning the first wafer to obtain the actual surface topography information of the first wafer; The first uncorrectable error information is obtained by comparing the actual surface topography information with the expected surface topography information. The semiconductor process of claim 4, wherein the expected surface topography information is derived from the process parameter of the first process step. The semiconductor process of claim 5, wherein the process parameter comprises a scan profile of the process device relative to the wafer. A control device for a semiconductor process, comprising: an input/output unit configured to receive actual surface topography information of the wafer acquired after the wafer completes the processing step; and a storage unit configured to store the process of the process step And a processor coupled to the input/output unit and the storage unit, the processor being configured to obtain, according to the difference between the actual surface topography information and the expected surface topography information obtained from the process parameter The error information is corrected, and the process parameters of the process step are adjusted according to the uncorrectable error information. The control device of the semiconductor process of claim 7, wherein the control device is coupled to the process device for performing the process step on the wafer, and the process parameter includes the process device relative to the wafer Scan settings parameters. A semiconductor process device, comprising: a process device configured to perform a process step on a wafer; and a detection device configured to acquire an actual surface topography information of the wafer after the process step is completed; the control device includes: And an output unit configured to receive the actual surface topography information; a storage unit configured to store process parameters of the process step; and a processor coupled to the input/output unit and the storage unit, the processor being configured The uncorrectable error information is obtained according to the difference between the actual surface topography information and the expected surface topography information obtained from the process parameter, and the process parameters of the process step are adjusted according to the uncorrectable error information. The semiconductor process device of claim 9, wherein the process parameter comprises a scan setting parameter of the process device relative to the wafer.