TWI521521B - Semiconductor memory apparatus - Google Patents

Description

Semiconductor storage device

The present invention relates to a voltage generating circuit for a semiconductor memory device such as a (Not AND, NAND) type flash memory, and particularly relates to a generation of bit line clamp voltage (bit line). A voltage generating circuit of a voltage such as a clamp voltage.

In the read operation of the flash memory, after the bit line is precharged, the bit line is cut off from the sense amplifier, and the potential corresponding to the data state of the memory cell is generated on the bit line. The potential of the bit line is detected by a sense amplifier. Between the bit line and the sense amplifier, a charge transfer transistor is connected, and the charge transfer transistor is used to control precharge of the bit line and charge transfer of the bit line. The operation of the charge transfer transistor is controlled in accordance with the clamp voltage generated by the clamp voltage generating circuit.

In general, the clamp voltage generating circuit must generate a low voltage clamping voltage in order to determine the material "0" or "1". Therefore, a conventional clamp voltage generating circuit is constructed using an intrinsic type transistor having a low critical value. However, such a transistor has a disadvantage that the threshold value is not uniform. In order to avoid this problem, in the patent In Document 1, there is disclosed a clamp voltage generating circuit that provides a resistor divider circuit between an input section of a current mirror circuit and a ground potential, between an output of the resistor divider circuit and an output section of the current mirror circuit. A potential setting circuit is provided to generate a clamp voltage from an output section of the current mirror circuit.

Moreover, in order to prevent misdetection of the data stored in the storage unit, the patent Document 2 discloses a clamp voltage generating circuit shown in FIG. As shown in FIG. 1, one end of the charge transfer transistor 30 is connected to the bit line BL, and the other end is connected to the sense amplifier 20. The gate of the charge transfer transistor 30 is connected to the clamp voltage generating circuit 10. The clamp voltage generating circuit 10 includes a constant current source 14, an N-channel metal oxide semiconductor (NMOS) transistor 12 and an NMOS transistor 13 as switching elements, and has the same function as the charge transfer transistor 30. An NMOS transistor 15 having a threshold voltage and a variable resistor 16.

The sense amplifier 20 includes an NMOS transistor 21, a capacitor 22, and a latch circuit 23. The drain of the NMOS transistor 21 is connected to the power supply node VDD/VSS, the source is connected to the sensing node TDC, and the NMOS transistor 21 sets the sensing node TDC to any one of the power supply voltage VDD and the ground voltage VSS.

In the read operation, first, the bit line BL is charged to the precharge voltage VPRE by the clamp voltage generating circuit 10. Specifically, the transistor 12 is turned on and the transistor 13 is turned off. The resistance value of the variable resistor 16 is set such that the voltage drop of the variable resistor 16 reaches the precharge voltage VPRE. Thereby, "VPRE+Vth" is applied to the gate of the charge transfer transistor 30 as the BL clamp voltage BLCLAMP. At this time, the sensing node TDC is charged to the power supply voltage VDD. Electric charge The transfer transistor 30 is turned off when the bit line BL reaches the precharge voltage VPRE.

Next, the transistor 12 is turned off, the transistor 13 is turned on, 0 V is applied to the gate of the charge transfer transistor 30 as the clamp voltage BLCLAMP, the charge transfer transistor 30 is turned off, and the bit line BL is in a floating state. Next, a read voltage is applied to the selected word line, a read pass voltage is applied to the unselected word line, and the selection transistor ST1 and the selection transistor ST2 are turned on, and the source line CELSRC is, for example, 0V.

Then, the clamp voltage generating circuit 10 generates a voltage "Vsen+Vth" as the clamp voltage BLCLAMP. This is achieved by setting the voltage drop of the variable resistor 16 to the sensing voltage Vsen. When the selected memory cell is turned on, the bit line BL is discharged, and the voltage of the bit line BL becomes equal to or lower than the sensing voltage Vsen, and the charge transfer transistor 30 is turned on. When the charge transfer transistor 30 is turned on, the sensing node TDC charged to the power supply voltage VDD is discharged. The sense amplifier 20 determines that the stored data of the selected storage unit is "1", and holds the result of the determination in the latch circuit 23.

(previous technical literature)

Patent Document 1: Japanese Patent Laid-Open Publication No. 2007-164891

Patent Document 2: Japanese Patent Laid-Open Publication No. 2011-181157

Fig. 2 shows a conventional other clamp voltage generating circuit. The clamp voltage generating circuit 10A is formed in a peripheral circuit region of the flash memory, and includes a current setting circuit 40, current mirror circuits 50, 60, 70, a transistor 80 for simulating a charge transfer transistor, and a rail-to-rail amplifier. (Rail to Rail Amplifier) 90 and the like.

The current setting circuit 40 has a plurality of NMOS transistors connected in parallel (figure In the example, four transistors TR1 to TFT4) and a constant current source 41 to a constant current source 44 connected in series to the plurality of transistors TR1 to TR4. The ON/OFF of each of the transistors TR1 to TR4 is controlled in accordance with the clamp control signal CLMP1 to the clamp control signal CLMP4 that are input to the respective gates. Further, the constant current source 41 to the constant current source 44 are, for example, constant currents flowing through 1 μA, 2 μA, 4 μA, and 8 μA. By 16 combinations of the clamp control signal CLMP1 to the clamp control signal CLMP4, for example, 16 kinds of currents which are stepped at 1 μA from 1 μA to 16 μA can be generated at the node CSUM.

The current mirror circuit 50 includes a pair of P-channel Metal Oxide Semiconductor (PMOS) transistors connected to a VDD power supply (for example, 2.4 V), and a common gate connection current setting circuit 40 of a pair of PMOS transistors. Node CSUM. Thereby, a current equal to the current of the node CSUM flows through the node N1 of the current mirror circuit 50, so that a current of 1 μA level from 1 μA to 16 μA can flow through the node N1.

The current mirror circuit 60 includes a pair of NMOS transistors connected to a ground line, and a common gate of a pair of NMOS transistors is connected to the node N1. Thereby, a current equal to the current of the node N1 is generated at the node N2 of the current mirror circuit 60, so that a current of 1 μA stepping from 1 μA to 16 μA can flow through the node N2.

The current mirror circuit 70 includes a pair of PMOS transistors connected to a Vd power source (for example, 6V), and a common gate of a pair of PMOS transistors is connected to the node N2. Further, on a pair of PMOS transistors, a pair of PMOS transistors are connected in series, and a bias signal PBIAS is applied to the gates thereof. When the clamp voltage generating circuit 10A operates, The bias signal PBIAS becomes the L level and the PMOS transistor is turned on. Thereby, a current equal to the current of the node N2 is generated at the node N3 of the current mirror circuit 70, so that a current of 1 μA level from 1 μA to 16 μA can flow through the node N3.

An NMOS transistor 80 that simulates the charge transfer transistor TG and resistors R1 and R2 are connected in series to the node N3 of the output section of the current mirror circuit 70, respectively. The transistor 80 is a diode connection in which the gate is connected to the drain, and the threshold voltage Vth of the transistor 80, that is, the voltage drop is equal to the threshold voltage of the charge transfer transistor TG. By appropriately selecting the values of the power source Vd and the resistors R1 and R2, for example, a voltage of 0.1 V stepped from 0.1 V to 1.6 V corresponding to the current value of the node CSUM can be generated at the node N4. For example, when 0.8 μA is set by the current setting circuit 20, 0.8 V is generated, and when 1.2 μA is set, 1.2 V is generated. Therefore, the reference voltage VREF of 0.1 V stepping from 0.1 V + Vth to 1.6 V + Vth to which the threshold voltage Vth of the transistor 80 is applied can be generated at the node N3.

For the non-inverted input terminal of the rail-to-rail amplifier 90, the voltage of the input node N3 is used as the reference voltage VREF, and for the inverted input terminal, the rail-to-rail amplifier 90 is negatively fed back. Output. The rail-to-rail amplifier 90 functions as an analog output buffer that outputs a VCLMP (clamp) voltage that is approximately equal to the input reference voltage VREF, and the VCLMP voltage is applied to the page buffer/page buffer/ A gate of a plurality of charge transfer transistors connected by a plurality of bit lines within the sensing circuit.

Next, the operation of the clamp voltage generating circuit will be described. Figure 3 shows the reference voltage VREF (node N3), the VCLMP voltage, and the voltage of the bit line BL. Waveform. At time T1, pre-charging of the bit line is started. At this time, the VCLMP voltage is set to, for example, 1.2 V+Vth, and the VDD potential is supplied to the sensing node SNS. The charge transfer transistor TG is turned on by the VCLMP voltage, and VCLMP-Vth, that is, 1.2V, is precharged from the sense node SNS for the bit line BL.

Next, when the precharge is ended at time T2, for the selected word line, A voltage Vcg (for example, 0 V) is applied, and a Vpass voltage is applied to the non-selected word line, and the transistor is turned on by selecting the gate lines SGD and SGS. When the data "0" is stored in the storage unit MCn, the storage unit MCn is turned off, and the precharge potential of the bit line BL hardly changes, but when the data "1" is stored in the storage unit MCn, the storage unit MCn is turned on. The discharge of the bit line BL starts.

Next, sensing of the sensing node SNS is performed during the period from time T3 to time T4. The VCLMP voltage is set, for example, to 0.8V+Vth. As described above, for example, the VCLMP voltage can be selected in a range of 0.1V+Vth~1.6V+Vth with a rating of 0.1V, and the VCLMP voltage can be set by the current of the node CSUM of the current setting circuit 110 (1μA~16μA). And get. Thus, when the data is "0", the charge transfer transistor TG is not turned on, so the sensing node SNS is still VDD. When the data is "1", the charge transfer transistor TG is turned on, and the potential of the sensing node SNS is lowered.

If the voltage of the node N4 is equal to the voltage of the bit line BL, and the threshold voltage Vth of the transistor 80 is equal to the threshold voltage of the charge transfer transistor TG, the source/drain voltage of the charge transfer transistor TG will be correctly simulated. The VCLMP voltage can be the correct sensing level. However, in practice, the source/drain voltage of the simulated transistor 80 is node N3 and node N4, sometimes not necessarily with charge transfer transistor TG. The source/drain voltage is the same, which is inconsistent with the correct sensing level.

4 is a graph simulating a global bit line (GBL) and a VCLMP voltage (node N4), the horizontal axis represents the code, and the vertical axis represents the difference between the GBL (Global Bit Line) and the VCLMP voltage (node N4). Further, the code on the horizontal axis represents the simulation result of the 4-bit clamp control signal CLMP1 to the clamp control signal CLMP4. As is clear from the graph, the difference voltage deviates from the ideal target of 0 V by about 0.2 V to 0.3 V, and there is unevenness. In addition, the VCLMPMVT voltage of node N4 is used to determine or evaluate circuit characteristics.

In this manner, the condition of the source/drain voltage of the charge transfer transistor TG of the sensing level is determined on the page buffer side, and the charge transfer transistor TG is simulated in the clamp voltage generating circuit on the side of the peripheral circuit region. The conditions of the source/drain voltage of the analog transistor 80 are inconsistent, and thus the VCLMP voltage generated eventually deviates, and the voltage itself may be uneven. If the VCLMP voltage of the sensing level is determined to be uneven, it will directly cause the unevenness of the threshold voltage Vth of the storage unit, thereby adversely affecting the critical value distribution of the storage unit.

It is an object of the present invention to provide a semiconductor memory device having a voltage generating circuit that generates a correct clamping voltage.

The semiconductor memory device of the present invention includes a clamp voltage generating circuit that supplies a clamp voltage to a charge transfer transistor, the charge transfer transistor being coupled to a sense node of a bit line, wherein the clamp Bit voltage generation circuit The method includes a transistor, a drain is coupled to the first potential, a source is coupled to the node, a clamp voltage is coupled to the gate, and a current setting member is coupled between the node and the second potential, and flows from the node to the node The current of the second potential is set; and the constant voltage output means inputs a voltage fed back from the node and a reference voltage, and controls the output of the clamp voltage such that the voltage fed back matches the reference voltage.

According to an embodiment, the current setting member sets the transistor Bungee current. Preferably, the current setting member includes a plurality of current setting transistors connected in parallel, and a current source respectively connected in series to the plurality of current setting transistors, wherein the current setting member is Among the plurality of current setting transistors, the selected current setting transistor is turned on to set the current. Further, in another embodiment, the flash memory further stores in advance copy data of the current copied with the bit line, and the current setting means sets the current based on the copy data. Among them, the copy data is a fuse register stored in each semiconductor wafer. Further, the current setting means selects a current setting transistor to be turned on based on the copy data. In the above embodiment, the current setting means sets a relatively large drain current in a fixed period in which the bit line is precharged via the charge transfer transistor, and after the start period is over, the setting is made. A current that simulates the drain current of the charge transfer transistor. Among them, it is preferable that the relatively large drain current is stored in the memory in advance. Further, the first potential is equal to a potential supplied to the sensing node, and a drain current of the transistor is equal to a drain current of the charge transfer transistor. The constant voltage output member includes a regulator that inputs the reference voltage to the non-inverting input terminal, and the inverting input terminal The feedback voltage is input and the clamp voltage is output. Further, the constant voltage output means includes a current mirror circuit that generates the reference voltage based on the selected current value, the current mirror circuit being coupled to a third potential greater than the first potential.

According to the present invention, the current of the bit line can be reproduced by the current setting means, so that the condition of the analog transistor can be easily approximated to the condition of the charge transfer transistor. Thereby, the clamp voltage for reducing unevenness can be more accurately supplied to the charge transfer transistor.

10, 10A‧‧‧ clamp voltage generation circuit

12, 13, 15, 21‧‧‧ NMOS transistors

14‧‧‧Constant current source

16‧‧‧Variable Resistor

20‧‧‧Sense Amplifier

22‧‧‧ Capacitors

23‧‧‧Latch circuit

30, TG‧‧‧ charge transfer transistor

40‧‧‧ Current setting circuit

41~44‧‧‧Constant current source

50, 60, 70‧‧‧ current mirror circuit

80‧‧‧Analog transistor

90‧‧‧rail-to-rail amplifier

100‧‧‧flash memory

110‧‧‧Memory array

111~114, 231~234‧‧‧ current source

120‧‧‧Output/Input Buffer

130‧‧‧ address register

140‧‧‧data register

150‧‧‧ Controller

160‧‧‧Word line selection circuit

170‧‧‧Page Buffer/Sensor Circuit

180‧‧‧ column selection circuit

182‧‧‧ peripheral circuits

190‧‧‧Internal voltage generation circuit

200‧‧‧Clamp voltage generation circuit

210‧‧ ‧ constant voltage output circuit (regulator)

220‧‧‧Analog transistor

230‧‧‧2nd current setting circuit

Ax‧‧‧ row address information

Ay‧‧‧Address Information

BL, GBL0~GBLn‧‧‧ bit line

BLCLAMP‧‧‧BL clamp voltage

BLK(0)~BLK(m)‧‧‧ Block

C1, C2, C3‧‧‧ control signals

CELSRC‧‧‧ source line

CLMP1~CLMP8‧‧‧Clamp control signal

CSUM, N1~N5‧‧‧ nodes

Ids, I'ds‧‧‧汲polar current

MC0~MC31, MCn‧‧‧ storage unit

NU‧‧‧string unit

PBIAS‧‧‧ Bias signal

R1, R2‧‧‧ resistance

SGD, SGS‧‧‧ select gate line

SL‧‧‧Shared source line

SNS, TDC‧‧‧ sensing nodes

T1~T4‧‧‧ moments

TD‧‧‧ bit line selection transistor

TR1~TR8‧‧‧O crystal

TS‧‧‧Source line selection transistor

Vcg‧‧‧ voltage

VCLMP‧‧‧ voltage

VCLMPMVT‧‧‧ voltage

Vd‧‧‧ power supply

Vers‧‧‧Erasing voltage

VDD‧‧‧Power supply voltage

WL0~WL31‧‧‧ character line

VPRE‧‧‧Precharge voltage

Vpass‧‧‧ pass voltage

Vprog‧‧‧ stylized voltage

Vread‧‧‧ readout voltage

VREF‧‧‧ reference voltage

VSS‧‧‧ Grounding voltage

Vth‧‧‧ threshold

1 is a view showing a conventional clamp voltage generating circuit of a flash memory.

2 is a view showing a conventional clamp voltage generating circuit of a flash memory.

3 is a view showing voltage waveforms of a VCLMP voltage and a bit line.

4 is a graph for explaining a state of deviation of a clamp voltage output from the clamp voltage generating circuit shown in FIG. 2 when detecting a voltage of a sensing node.

Fig. 5 is a block diagram showing a configuration example of a flash memory according to an embodiment of the present invention.

Fig. 6 is a circuit diagram showing the configuration of a NAND string of an embodiment of the present invention.

Fig. 7 is a view showing an example of a voltage applied to each portion of the flash memory of the embodiment.

Fig. 8 is a view showing a clamp voltage generating circuit of an embodiment of the present invention.

Fig. 9 is a view for explaining an operation of a clamp voltage generating circuit according to an embodiment of the present invention.

FIG. 10 is a view showing an operation waveform of a clamp voltage generating circuit according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, it should be noted that in the drawings, the parts are emphasized to be understood for ease of understanding, and the ratio to the actual device is not the same.

(Example)

Fig. 5 is a block diagram showing the structure of a flash memory according to an embodiment of the present invention. However, the structure of the flash memory shown here is merely illustrative, and the present invention is not necessarily limited to such a structure.

The flash memory 100 of this embodiment includes a memory array 110 formed with a plurality of storage units arranged in a matrix, and an output/input buffer 120 connected to an external output/input terminal I/O to maintain output/input. Data; address register 130, receiving address data from output/input buffer 120; data register 140, holding output/input data; controller 150, supplying control signals C1, C2, C3, etc., The control signals C1, C2, C3, etc. are based on command data from the output/input buffer 120 and external control signals (wafer enable or address latch enable (not shown), etc.); word line selection The circuit 160 decodes the row address information Ax from the address register 130, and performs block selection and characters based on the decoding result. Line selection or the like; page buffer/sense circuit 170, holding data read from a page selected by word line selection circuit 160, or holding write data to the selected page; column selection circuit 180, pair The column address information Ay from the address register 130 is decoded, and the column data in the page buffer 170 is selected based on the decoding result; the peripheral circuit 182 is formed with a clamp voltage generating circuit and the like; and the internal voltage generating circuit 190. Generate a voltage (program voltage Vprog, pass voltage Vpass, read voltage Vread, erase voltage Vers, etc.) required for reading, programming, and erasing data.

The memory array 110 has a plurality of blocks BLK(0), BLK(1), ..., BLK(m) arranged in the column direction. At one end of the block, a page buffer/sense circuit 170 is disposed. However, the page buffer/sense circuit 170 can also be disposed at the other end of the block or at the ends on both sides.

In one memory block, as shown in FIG. 6, a plurality of NAND string units NU in which a plurality of memory cells are connected in series are formed, and n+ is arranged in a row direction in one memory block. 1 string unit NU. The string unit NU includes a plurality of memory cells MCi (i = 0, 1, ..., 31) connected in series, a selection transistor TD on the drain side of the memory cell MC31 connected to one end, and a memory connected to the other end The source transistor TS of the source side of the cell MC0 is connected to the drain of the selected transistor TD to the corresponding one bit line GBL, and the source of the selected transistor TS is connected to the common source line SL.

The control gate of the memory cell MCi is connected to the word line WLi, and the gates of the selection transistors TD and TS are connected to the selection gate line SGD parallel to the word line WL, SGS. When the word line selection circuit 160 selects the memory block based on the row address Ax, the selection transistor TD, TS is selectively driven via the selected gate signals SGS, SGD of the memory block.

The storage unit typically has a MOS structure including: The source/drain as the N-type diffusion region is formed in the P well; the tunnel oxide film is formed on the channel between the source and the drain; and the floating gate (charge accumulation layer) is formed on the tunnel oxide film; And controlling the gate formed on the floating gate via the dielectric film. When there is no charge accumulated in the floating gate, that is, when the data "1" is written, the critical value becomes a negative state, and the storage unit is normally connected. When electrons are accumulated in the floating gate, that is, when data "0" is written, the threshold shifts to positive and the memory cell is normally off.

Figure 7 is a diagram showing the bias voltage applied during each operation of the flash memory. A table of examples. In the read operation, a positive voltage is applied to the bit line, a certain voltage (for example, 0 V) is applied to the selected word line, and a pass voltage Vpass (for example, 4.5 V) is applied to the unselected word line to select the gate. A positive voltage (for example, 4.5 V) is applied to the lines SGD and SGS, and the bit line selection transistor TD and the source line selection transistor TS are turned on, and 0 V is applied to the common source line. In the stylized (write) operation, a high voltage stylized voltage Vprog (15V~20V) is applied to the selected word line, and an intermediate potential (for example, 10V) is applied to the unselected word line to make the bit line The transistor TD is turned on to turn off the source line selection transistor TS, and the potential corresponding to the material "0" or "1" is supplied to the bit line GBL. In the erase operation, 0V is applied to the selected word line in the block, a high voltage (for example, 20V) is applied to the P well, and the electrons of the floating gate are extracted to the substrate, thereby, in units of blocks. Erase data.

Next, Fig. 8 shows a clamp voltage generating circuit of an embodiment of the present invention. In the clamp voltage generating circuit 200 of the present embodiment, the same components as those of the clamp voltage generating circuit 10A shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will not be repeated.

The clamp voltage generating circuit 200 of the present embodiment is formed in the peripheral circuit 182 of the flash memory 100, and the VCLMP (clamp) voltage generated in the clamp voltage generating circuit 200 is supplied to the page buffer/sensor. The n+1 bit lines in the measurement circuit 170 are respectively connected to the gates of the charge transfer transistors TG.

The clamp voltage generating circuit 200 of the present embodiment removes the analog transistor 80 of the clamp voltage generating circuit 10A shown in FIG. 2, and instead, the analog transistor 220 is provided at the output end of the constant voltage output circuit 210. Preferably, the constant voltage output circuit 210 is configured to include a regulator that outputs a constant voltage. The non-inverting input terminal of the regulator 210 is input to the reference voltage VREF of the node N3, and the analog input power is fed back to the inverting input terminal. The source of the crystal 220, that is, the voltage of the node N5. The regulator 210 is controlled in accordance with the feedback to output a VCLMP voltage of VREF + Vth.

An analog NMOS transistor 220 is connected in series between the VDD power supply and the node N5. That is, the drain of the transistor 220 is connected to the VDD power supply, the source is connected to the node N5, and the VCLMP voltage of the regulator 210 is supplied to the gate of the transistor 220. When the transistor 220 is turned on, the node N5 starts charging, and this condition is fed back to the regulator 210. The regulator 210 controls the VCLMP voltage in such a manner that the voltage of the node N5 is equal to the reference voltage VREF. The voltage at node N5 is equivalent to VREF, so the VCLMP voltage is fed back to VREF+Vth.

A second current setting circuit 230 is connected in series to the analog transistor 220. The second current setting circuit 230 has a configuration similar to that of the current setting circuit 40, but the second current setting circuit 230 can set a finer current value than the current setting circuit 40. The second current setting circuit 230 includes a plurality of NMOS transistors (here, four transistors TR5 to TR8) connected in parallel, and four current sources 231 to 234 connected in series to the respective transistors. . The clamp control signal CLMP5 to the clamp control signal CLMP8 are input to the gates of the respective transistors TR5 to TR8, and the transistors TR5 to TR8 are turned on/off, respectively. Each of the constant current source 231 to the constant current source 234 is, for example, a constant current flowing through 0.125 μA, 0.25 μA, 0.5 μA, or 1.0 μA. By 16 combinations of the 4-bit clamp control signal CLMP4 to the clamp control signal CLMP8, for example, a current of 0.125 μA to 2 μA can be set in a step of 0.125 μA.

The second current setting circuit 230 can copy the current of the bit line BL in the page buffer/sense circuit at the time of reading. In a preferred embodiment, in order to prevent unevenness of each wafer in a wafer, a fuse register or a fuse read-only memory or the like is prepared for each wafer, the fuse register or The fuse ROM is used to store the binary data of the clamp control signal CLMP5~the clamp control signal CLMP8 as copy data. For example, at the semiconductor wafer stage, a current value or the like discharged from a bit line of the selected wafer or test element is measured, and the fuse is trimmed based on the measurement result and stored in a fuse register of each wafer. Copy the data. Further, the code of the clamp control signal CLMP1 to the clamp control signal CLMP4 of the first current setting circuit 40 can be similarly stored in the fuse register or the like. And, the controller 150 is When reading is performed, the clamp control signal CLMP1 to the clamp control signal CLMP4 or the clamp control signal CLMP5 to the clamp control signal CLMP8 can be read from the fuse register to set the first current setting circuit 40 and the second current. The current value of the circuit 230 is set. Moreover, in other embodiments, the binary data of the clamp control signal CLMP5~the clamp control signal CLMP8 may be stored in units of blocks of the flash memory rather than in units of chips, and read when read. The clamp control signal CLMP5 to clamp control signal CLMP8 of the block corresponding to the selected page is set to set the current value of the second current generation circuit 230. In a more preferred embodiment, the reference voltage VREF (node N3) input to the non-inverting input terminal of the constant voltage output circuit 210 can be output to the outside or measured to set the clamp control signal CLMP5~ clamp control signal. CLMP8.

Fig. 9 is a view for explaining the operation of the clamp voltage generating circuit of the embodiment. The regulator 210, that is, the constant voltage output circuit 210 outputs the VCLMP voltage of the reference voltage VREF+Vth in accordance with the feedback of the node N5. The VCLMP voltage is supplied to the gate of the analog transistor 220, and is supplied to the gates of the charge transfer transistors TG connected to the respective bit lines BL in the page buffer/sense circuit 170. The second current generating circuit 230 has a configuration in which the gate current I'ds of the analog transistor 220 can be adjusted to the drain current Ids of the charge transfer transistor TG, whereby the drain of the charge transfer transistor TG can be made/ The condition of the voltage between the sources is extremely close to the condition of the voltage between the drain and the source of the analog transistor 220. Thereby, it is possible to suppress the generated VCLMP voltage from deviating from the target voltage. Further, by the clamp control signal CLMP5 to the clamp control signal CLMP8 of the second current generation circuit 230, the analog transistor 220 is turned on. The pole current is consistent with the drain current of the charge transfer transistor, whereby the VCLMP voltage unevenness can be suppressed.

In a more preferred embodiment, the clamp voltage generating circuit 200 of the present embodiment controls the amount of current I'ds flowing through the transistor 220 during reading by the controller 150 to be variable, thereby, for example, At the start of precharging, the precharge time of the bit line BL that is overdriven by the relatively large drain current Imax can be shortened. The second current setting circuit 230 can set the drain current Imax based on the clamp control signal CLMP5 to the clamp control signal CLMP8 read from the fuse register, for example, Imax=I'ds×k:k is an arbitrary coefficient. ). Alternatively, the clamp control signal CLMP5 to the clamp control signal CLMP8 which is the drain current Imax may be stored in the fuse register.

FIG. 10 is a view showing a voltage waveform at the start of precharge. At time T1, pre-charging is started, and at time T2, the over-driving drain current reaches a peak. The reference voltage VREF rises from the time T1 toward the time T2, and in response to this, the VCLMP voltage is overdriven to 1.2V+Vth+α at the time T2. By this overdrive, a precharge voltage (1.2 V) is charged in the bit line BL at time T2 or a later time than the time T2. The curve shown by the broken line indicates the conventional precharge time when such overdrive is not performed. The second current setting circuit 230 controls so that the increased current Q+α μA flows so that the time T2 reaches a peak value, and then controls the analog current Q μA to flow.

By generating the precharge voltage of the correct bit line as in the present embodiment, the variation in the discharge time of the bit line will simply become the variation inherent in the memory cell (depending on the critical value Vth of the memory cell). Therefore, the sensing amplification can be correctly set The sensing time of the device makes it possible to shorten the reading time.

In the above embodiment, an example in which the clamp voltage generating circuit is used at the time of reading is shown, but the clamp voltage generating circuit may be used in the verification. Further, in the above-described embodiment, the example in which the first current setting circuit 40 and the second current setting circuit 230 include a 4-bit transistor is shown, but the transistor may include a plurality of bits. Further, in the embodiment, the reading of the storage unit storing the binary data is exemplified, but the present invention is also applicable to the flash memory having the storage unit storing the binary data. At this time, the clamp voltage generating circuit generates a VCLMP voltage for sensing (singing) the multi-ary data. Further, in the above embodiment, the clamp voltage generating circuit of the flash memory has been described, but the clamp voltage generating circuit can also be used in other semiconductor memories.

The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made without departing from the scope of the invention.

40‧‧‧ Current setting circuit

50, 60, 70‧‧‧ current mirror circuit

111~114, 231~234‧‧‧ current source

200‧‧‧Clamp voltage generation circuit

210‧‧ ‧ constant voltage output circuit (regulator)

220‧‧‧Analog transistor

230‧‧‧2nd current setting circuit

CLMP1~CLMP8‧‧‧Clamp control signal

CSUM, N1~N3, N5‧‧‧ nodes

PBIAS‧‧‧ Bias signal

R1, R2‧‧‧ resistance

TR1~TR8‧‧‧O crystal

VCLMP‧‧‧ voltage

Vd‧‧‧ power supply

VDD‧‧‧Power supply voltage

VREF‧‧‧ reference voltage

Claims (11)

A semiconductor memory device includes a clamp voltage generating circuit that supplies a clamp voltage to a charge transfer transistor coupled to a sense node of a bit line, wherein the clamp voltage generation circuit includes: a crystal, a drain is coupled to the first potential, a source is coupled to the node, a clamp voltage is directly coupled to the gate, and a current setting member is coupled between the node and the second potential, and flows from the node to the The current of the second potential is set; and the constant voltage output means inputs a voltage fed back from the node and a reference voltage, and controls the output of the clamp voltage such that the voltage of the return body coincides with the reference voltage . The semiconductor storage device of claim 1, wherein the current setting member sets a drain current of the transistor. The semiconductor storage device according to claim 1 or 2, wherein the current setting member includes a plurality of current setting transistors connected in parallel, and currents respectively connected in series to the plurality of current setting transistors The source, the current setting means sets the current by turning on the current setting transistor selected from the plurality of current setting transistors. The semiconductor storage device according to claim 1 or 2, wherein the flash memory further stores in advance copy data of a current in which the bit line is copied, and the current setting means sets the current based on the copy data. The semiconductor storage device of claim 4, wherein the replicated material is a fuse register stored in each semiconductor wafer. The semiconductor storage device according to claim 3, wherein the current setting means selects a current setting transistor to be turned on based on the replica data. The semiconductor storage device of claim 1, wherein the current setting member sets a relatively large drain current during a fixed period of starting to precharge the bit line via the charge transfer transistor. A current is set after the end of the start period, the current simulating the drain current of the charge transfer transistor. The semiconductor storage device of claim 7, wherein the relatively large drain current is pre-stored in the memory. The semiconductor storage device of claim 1, wherein the first potential is equal to a potential supplied to the sensing node, and a drain current of the transistor and a drain of the charge transfer transistor The currents are equal. The semiconductor storage device of claim 1, wherein the constant voltage output member includes a regulator that inputs the reference voltage to a non-inverting input terminal, and inputs the feedback to an inverting input terminal The voltage and output the clamp voltage. The semiconductor storage device of claim 1, wherein the constant voltage output member includes a current mirror circuit that generates the reference voltage based on the selected current value, the current mirror circuit being coupled to be greater than the first The third potential of 1 potential.