CN104810050B - Semiconductor memory device with a plurality of memory cells - Google Patents

Abstract

The present invention provides a semiconductor storage device. The semiconductor storage device includes a clamping voltage generating circuit (200) for generating a correct clamping voltage. The clamping voltage generating circuit includes: a simulation transistor (220), the drain of which is coupled to a VDD power supply, the source of which is coupled to a node (N5), and the clamping voltage of which is coupled to a gate; a current setting circuit (230), which is connected between the node (N5) and a ground potential, and sets the current flowing from the node (N5) to the ground potential; and a regulator (210), which inputs a voltage fed back from the node (N5) and a reference voltage (VREF), and outputs a VCLMP voltage. The current setting circuit (230) can replicate the current of a bit line (BL), and can make the simulation transistor (220) approximate a charge transfer transistor (TG).

Description

semiconductor storage device

technical field

The present invention relates to a voltage generation circuit for a semiconductor storage device such as a NAND (Not AND, NAND) type flash memory (flash memory), in particular to a voltage generation circuit that can be used for bit line clamp voltage (bit line clamp voltage) and the like voltage generating circuit.

Background technique

In the read operation of the flash memory, after the bit line is precharged, the bit line is disconnected from the sense amplifier (sense amplifier), and a potential corresponding to the data state of the memory cell is generated on the bit line, which is detected by the sense amplifier. potential of the bit line. Between the bit line and the sense amplifier, a charge transfer transistor is connected, and the charge transfer transistor is used for controlling precharging of the bit line and charge transfer of the bit line. The operation of the charge transfer transistor is controlled according to the clamp voltage generated by the clamp voltage generating circuit.

In general, a clamp voltage generation circuit must generate a low-voltage clamp voltage in order to determine data "0" or "1". Therefore, a certain conventional clamp voltage generating circuit is configured using intrinsic transistors with low thresholds, but such transistors have a disadvantage of large variation in thresholds. In order to avoid this problem, in Patent Document 1, a kind of clamp voltage generating circuit is disclosed. A potential setting circuit is provided between the output stages of the current mirror circuit, and a clamp voltage is generated from the output stage of the current mirror circuit.

Furthermore, in order to prevent erroneous reading of data stored in a memory cell, Patent Document 2 discloses a clamp voltage generation circuit shown in FIG. 1 . As shown in FIG. 1 , one end of the charge transfer transistor 30 is connected to the bit line BL, and the other end is connected to the sense amplifier 20 . The gate of the charge transfer transistor 30 is connected to the clamp voltage generating circuit 10 . The clamp voltage generating circuit 10 includes a constant current source 14, an N-channel metal oxide semiconductor (N-channel Metal Oxide Semiconductor, NMOS) transistor 12 and an NMOS transistor 13 as switching elements, and a transistor having the same threshold voltage as the charge transfer transistor 30. NMOS transistor 15, and variable resistor 16.

The sense amplifier 20 includes an NMOS transistor 21 , a capacitor 22 , and a latch circuit (latch circuit) 23 . The drain of the NMOS transistor 21 is connected to the power supply node VDD/VSS, and the source is connected to the read node TDC. The NMOS transistor 21 sets the read node TDC to either the power supply voltage VDD or the ground voltage VSS.

In the read operation, first, the bit line BL is charged to the precharge voltage VPRE by the clamp voltage generating circuit 10 . Specifically, transistor 12 is turned on and transistor 13 is turned off. The resistance value of the variable resistor 16 is set so that the voltage drop across the variable resistor 16 reaches the precharge voltage VPRE. Thus, “VPRE+Vth” is applied to the gate of the charge transfer transistor 30 as the BL clamp voltage BLCLAMP. At this time, the read node TDC is charged to the power supply voltage VDD. The charge transfer transistor 30 is turned off at the point when the bit line BL reaches the precharge voltage VPRE.

Then, the transistor 12 is turned off, the transistor 13 is turned on, 0 V is applied to the gate of the charge transfer transistor 30 as the clamp voltage BLCLAMP, the charge transfer transistor 30 is turned off, and the bit line BL is in a floating state. Next, a read voltage is applied to the selected word line, a read pass voltage is applied to the non-selected word line, the selection transistor ST1 and the selection transistor ST2 are turned on, and the source line CELSRC is, for example, 0V.

Then, the clamp voltage generation circuit 10 generates the voltage "Vsen+Vth" as the clamp voltage BLCLAMP. This is achieved by setting the voltage drop across the variable resistor 16 as the read voltage Vsen. When the selected memory cell is turned on, the bit line BL is discharged, the voltage of the bit line BL becomes lower than the read voltage Vsen, and the charge transfer transistor 30 is turned on. When the charge transfer transistor 30 is turned on, the sense node TDC charged to the power supply voltage VDD is discharged. The sense amplifier 20 judges that the storage data of the selected memory cell is “1”, and holds the judgment result in the latch circuit 23 .

prior art literature

patent documents

Patent Document 1: Japanese Patent Laid-Open No. 2007-164891

Patent Document 2: Japanese Patent Laid-Open No. 2011-181157

FIG. 2 shows another conventional clamp voltage generation circuit. The clamp voltage generation circuit 10A is formed in the peripheral circuit region of the flash memory, and includes a current setting circuit 40, current mirror circuits 50, 60, 70, a transistor 80 emulating a charge transfer transistor, and a rail-to-rail amplifier (Rail to Rail Amplifier) 90 and so on.

The current setting circuit 40 has a plurality of NMOS transistors connected in parallel (four transistors TR1 to TR4 in the illustration), and constant current sources 41 to 44 connected in series to the plurality of transistors TR1 to TR4 . On/off of each of the transistors TR1 - TR4 is controlled by clamp control signals CLMP1 - CLMP4 input to respective gates. Furthermore, the constant current sources 41 to 44 flow constant currents of, for example, 1 μA, 2 μA, 4 μA, and 8 μA. With the 16 combinations of the clamp control signals CLMP1 to CLMP4 , for example, 16 currents in steps of 1 μA from 1 μA to 16 μA can be generated at the node CSUM.

The current mirror circuit 50 includes a pair of P-channel metal oxide semiconductor (P-channel Metal Oxide Semiconductor, PMOS) transistors connected to the VDD power supply (for example, 2.4V), and the common gate of the pair of PMOS transistors is connected to the current setting circuit 40 The node CSUM of . Accordingly, a current equal to the current at the node CSUM flows through the node N1 of the current mirror circuit 50 , and a current in steps of 1 μA ranging from 1 μA to 16 μA can flow through the node N1 .

The current mirror circuit 60 includes a pair of NMOS transistors connected to the ground, and a common gate of the pair of NMOS transistors is connected to the node N1. Thereby, a current equal to the current at the node N1 is generated at the node N2 of the current mirror circuit 60 , and a current in steps of 1 μA from 1 μA to 16 μA can flow through the node N2 .

The current mirror circuit 70 includes a pair of PMOS transistors connected to a Vd power supply (for example, 6V), and a common gate of the pair of PMOS transistors is connected to a node N2 . Furthermore, a pair of PMOS transistors are connected in series to the pair of PMOS transistors, and a bias signal PBIAS is applied to the gates thereof. When the clamp voltage generating circuit 10A operates, the bias signal PBIAS becomes L level, and the PMOS transistor is turned on. Thus, a current equal to the current at the node N2 is generated at the node N3 of the current mirror circuit 70 , and a current in steps of 1 μA ranging from 1 μA to 16 μA can flow through the node N3 .

An NMOS transistor 80 dummy charge transfer transistor TG and resistors R1 and R2 are connected in series to a node N3 of the output stage of the current mirror circuit 70 . The transistor 80 is diode-connected in which the gate is connected to the drain, and the threshold voltage Vth, that is, the voltage drop of the transistor 80 is equal to the threshold voltage of the charge transfer transistor TG. By appropriately selecting the values of the power supply Vd and the resistors R1 and R2, for example, voltages in steps of 0.1V from 0.1V to 1.6V corresponding to the current value of the node CSUM can be generated at the node N4. For example, when 0.8 μA is set by the current setting circuit 20 , 0.8 V is generated, and when 1.2 μA is set, 1.2 V is generated. Accordingly, the reference voltage VREF in steps of 0.1V from 0.1V+Vth to 1.6V+Vth to which the threshold voltage Vth of the transistor 80 is added can be generated at the node N3.

For the non-inverted input terminal (non-inverted input terminal) of the rail-to-rail amplifier 90, the voltage of the input node N3 is used as the reference voltage VREF, and for the inverted input terminal (inverted input terminal), the negative feedback of the rail-to-rail amplifier 90 output. The rail-to-rail amplifier 90 functions as an analog output buffer that outputs a VCLMP (clamp) voltage substantially equal to the input reference voltage VREF, and the VCLMP voltage is applied to a page buffer (page buffer)/ The gates of the plurality of charge transfer transistors connected to the plurality of bit lines within the readout circuit.

Next, the operation of the clamp voltage generating circuit will be described. FIG. 3 shows reference voltage VREF (node N3 ), VCLMP voltage, and voltage waveforms of bit line BL. At time T1, precharging of the bit lines starts. At this time, the VCLMP voltage is set to, for example, 1.2V+Vth, and the VDD potential is supplied to the sense node SNS. The charge transfer transistor TG is turned on by the VCLMP voltage, and the bit line BL is precharged with VCLMP-Vth, that is, 1.2V, from the sense node SNS.

Next, when precharging ends at time T2, a voltage Vcg (for example, 0V) is applied to the selected word line, and a Vpass voltage is applied to the non-selected word line, and the selection transistor is turned on through the selection gate lines SGD and SGS. When data "0" is stored in memory cell MCn, memory cell MCn is turned off, and the precharge potential of bit line BL hardly changes, but when data "1" is stored in memory cell MCn, memory cell MCn is turned on, The discharge of the bit line BL starts.

Next, during the period from time T3 to time T4, the readout of the sense node SNS is performed. The VCLMP voltage is set to, for example, 0.8V+Vth. As described above, for example, the VCLMP voltage can be selected in steps of 0.1V within the range of 0.1V+Vth to 1.6V+Vth, and the VCLMP voltage can be selected by setting the current of node CSUM of the current setting circuit 110 (1 μA to 16 μA ) to obtain. Thus, when the data is "0", the charge transfer transistor TG is not turned on, so the sense node SNS is still at VDD, and when the data is "1", the charge transfer transistor TG is turned on, and the potential of the sense node SNS drops.

If the voltage of the node N4 is equal to the voltage of the bit line BL, and the threshold voltage Vth of the transistor 150 is equal to the threshold voltage of the charge transfer transistor TG, the source/drain voltage of the charge transfer transistor TG will be simulated correctly, and the VCLMP voltage can become correct readout level. However, in reality, the source/drain voltage of the simulated transistor 80 is node N3 and node N4, which may not necessarily coincide with the source/drain voltage of the charge transfer transistor TG, so that it is consistent with the correct readout level Inconsistent.

FIG. 4 is a graph of simulating Global Bit Line (GBL) and VCLMP voltage (node N4), the horizontal axis represents the code, and the vertical axis represents the difference between GBL (Global Bit Line) and VCLMP voltage (node N4). In addition, the codes on the horizontal axis represent the simulation results of the 4-bit clamp control signal CLMP1 to clamp control signal CLMP4 . It can be clearly seen from the graph that the difference voltage deviates from the ideal target 0V by about 0.2V to 0.3V, and there is unevenness. In addition, the VCLMPMVT voltage at the node N4 is used to measure or evaluate circuit characteristics.

In this way, the source/drain voltage condition of the charge transfer transistor TG that determines the read level on the page buffer side is different from the dummy transistor that simulates the charge transfer transistor TG in the clamp voltage generation circuit on the peripheral circuit area side. The condition of the source/drain voltage of the 80 is inconsistent, so the final generated VCLMP voltage may deviate, and the voltage itself may be uneven. If the VCLMP voltage that determines the read level varies, it will directly cause the threshold voltage Vth of the memory cells to vary, thereby adversely affecting the threshold distribution of the memory cells.

Contents of the invention

An object of the present invention is to provide a semiconductor memory device including a voltage generating circuit that generates a correct clamp voltage.

The semiconductor memory device of the present invention includes a clamp voltage generating circuit that supplies a clamp voltage to a charge transfer transistor coupled to a read node of a bit line, wherein the clamp voltage generates The circuit includes: a transistor, the drain is coupled to a first potential, the source is coupled to a node, and the clamping voltage is coupled to a gate; a current setting member is connected between the node and the second potential, and controls the flow from the node. setting the current to the second potential; and constant voltage output means inputting the voltage fed back from the node and a reference voltage, and controlling the clamping voltage so that the fed back voltage coincides with the reference voltage output.

According to an embodiment, the current setting means sets a drain current of the transistor. Preferably, the current setting means includes a plurality of current setting transistors connected in parallel, and current sources respectively connected in series to the plurality of current setting transistors, Among the plurality of current setting transistors, a selected current setting transistor is turned on to set the current. Furthermore, in another embodiment, the flash memory further stores in advance copy data in which the current of the bit line is copied, and the current setting means sets the current based on the copy data. Among them, the duplicate data is stored in a fuse register (fuse register) of each semiconductor chip. Also, the current setting means selects a current setting transistor to be turned on based on the replica data. In the above-described embodiment, the current setting means sets a relatively large drain current during a fixed period of starting to precharge the bit line via the charge transfer transistor, and sets a relatively large drain current after the start period ends. given to simulate the drain current of the charge transfer transistor. Wherein, it is preferable that the relatively large drain current is pre-stored in the memory. In addition, the first potential is equal to the potential supplied to the readout node, and the drain current of the transistor is equal to the drain current of the charge transfer transistor. The constant voltage output means includes a regulator that inputs the reference voltage to a non-inverting input terminal, inputs the fed-back voltage to an inverting input terminal, and outputs the clamp voltage. Furthermore, the constant voltage output means includes a current mirror circuit for generating the reference voltage based on the selected current value, the current mirror circuit being coupled to a third potential greater than the first potential.

(effect of invention)

According to the present invention, the current of the bit line can be replicated by the current setting means, and the condition of the dummy transistor can be easily approximated to the condition of the charge transfer transistor. Thereby, the clamping voltage with reduced unevenness can be more accurately supplied to the charge transfer transistor.

Description of drawings

FIG. 1 is a diagram showing a conventional clamp voltage generating circuit of a flash memory.

FIG. 2 is a diagram showing a conventional clamp voltage generating circuit of a flash memory.

FIG. 3 is a diagram showing VCLMP voltage and voltage waveforms of bit lines.

FIG. 4 is a graph illustrating a variation state of the clamp voltage output from the clamp voltage generating circuit shown in FIG. 2 when detecting the voltage of the sense node.

FIG. 5 is a block diagram showing a configuration example of a flash memory according to an embodiment of the present invention.

FIG. 6 is a circuit diagram showing the structure of a NAND string according to an embodiment of the present invention.

FIG. 7 is a diagram showing an example of voltages applied to various parts of the flash memory of this embodiment.

FIG. 8 is a diagram showing a clamp voltage generation circuit according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating the operation of the clamp voltage generation circuit according to the embodiment of the present invention.

FIG. 10 is a diagram showing operation waveforms of the clamp voltage generating circuit according to the embodiment of the present invention.

Wherein, the reference signs are explained as follows:

10, 10A: Clamping voltage generating circuit

12, 13, 15, 21: NMOS transistors

14: Constant current source

16: variable resistor

20: Sense amplifier

22: Capacitor

23: Latch circuit

30. TG: charge transfer transistor

40: Current setting circuit

41~44: constant current source

50, 60, 70: current mirror circuit

80: Transistor for simulation

90: Rail-to-Rail Amplifier

100: flash memory

110: memory array

111～114, 231～234: current source

120: output/input buffer

130: address register

140: data register

150: Controller

160: word line selection circuit

170: Page buffer/readout circuit

180: Column selection circuit

182: Peripheral circuit

190: Internal voltage generation circuit

200: clamp voltage generation circuit

210: Constant voltage output circuit (regulator)

220: Transistor for simulation

230: Second current setting circuit

Ax: row address information

Ay: column address information

BL, GBL0~GBLn: bit line

BLCLAMP: BL clamp voltage

BLK (0) ~ BLK (m): block

C1, C2, C3: control signal

CELSRC: source line

CLMP1～CLMP8: clamp control signal

CSUM, N1～N5: nodes

Ids, I'ds: drain current

MC0～MC31, MCn: storage unit

NU: string unit

PBIAS: bias signal

R1, R2: resistance

SGD, SGS: select gate line

SL: Shared source line

SNS, TDC: readout node

T1～T4: time

TD: bit line select transistor

TR1～TR8: Transistors

TS: Source Line Select Transistor

Vcg: voltage

VCLMP: Voltage

VCLMPMVT: Voltage

Vd: power supply

Vers: erase voltage

VDD: supply voltage

WL0～WL31: word line

VPRE: precharge voltage

Vprog: programming voltage

Vpass: pass voltage

Vread: read through the voltage

VREF: reference voltage

VSS: ground voltage

Vth: Threshold

Detailed ways

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, it should be noted that in the drawings, each part is emphasized for easy understanding, and the scale of the actual device is not the same.

[Example]

FIG. 5 is a block diagram showing the structure of a flash memory according to an embodiment of the present invention. However, the structure of the flash memory shown here is only an example, and the present invention is not necessarily limited to this structure.

The flash memory 100 of this embodiment includes: a memory array 110, formed with a plurality of memory cells arranged in rows and columns; an output/input buffer 120, connected to an external output/input terminal I/O, and maintaining output/input data; The address register 130 receives address data from the output/input buffer 120; the data register 140 maintains output/input data; the controller 150 supplies control signals C1, C2, C3, etc., the control signals C1, C2, C3, etc. Control each part based on the command data from the output/input buffer 120 and external control signals (not shown chip enable or address latch enable, etc.); The address information Ax is decoded, and block selection and word line selection are performed based on the decoding result; the page buffer/read circuit 170 holds the data read from the page selected by the word line selection circuit 160, or Keep the data written in the selected page; the column selection circuit 180 decodes the column address information Ay from the address register 130, and selects the column data in the page buffer 170 based on the decoding result; the peripheral circuit 182 forms There are clamping voltage generating circuits, etc.; and an internal voltage generating circuit 190 that generates voltages required for data reading, programming, and erasing (programming voltage Vprog, pass voltage Vpass, read pass voltage Vread, erase voltage Vers, etc. ).

The memory array 110 has a plurality of blocks BLK( 0 ), BLK( 1 ), . . . , BLK(m) arranged in the column direction. At one end of the block, a page buffer/read circuit 170 is arranged. However, the page buffer/readout circuit 170 may also be disposed at the other end or both ends of the block.

In one memory block, as shown in FIG. 6, a plurality of NAND string units NU formed by connecting a plurality of memory cells in series are formed, and in one memory block, n+1 units are arranged along the row direction. String unit NU. The string unit NU includes a plurality of memory cells MCi (i=0, 1, . In the selection transistor TS on the source side of MC0 , the drain of the selection transistor TD is connected to a corresponding one bit line GBL, and the source of the selection transistor TS is connected to a common source line SL.

The control gate of memory cell MCi is connected to word line WLi, and the gates of selection transistors TD, TS are connected to selection gate lines SGD, SGS parallel to word line WL. The word line selection circuit 160 selectively drives the selection transistors TD, TS through the selection gate signals SGS, SGD of the memory block when selecting the memory block based on the row address Ax.

The memory cell typically has a MOS structure, and the MOS structure includes: a source/drain as an N-type diffusion region formed in a P well; a tunnel oxide film formed on a channel between the source/drain; a floating gate (charge accumulating layer) formed on the tunnel oxide film; and the control gate formed on the floating gate via a dielectric film. When there is no charge accumulated in the floating gate, that is, when data "1" is written, the threshold value becomes a negative state, and the memory cell is normally on. When electrons are accumulated in the floating gate, that is, when data “0” is written, the threshold shift (shift) is positive, and the memory cell is normally off.

FIG. 7 is a table showing an example of bias voltages applied during each operation of the flash memory. In the read operation, a certain positive voltage is applied to the bit line, a certain voltage (for example, 0V) is applied to the selected word line, a pass voltage Vpass (for example, 4.5V) is applied to the non-selected word line, and a certain voltage (for example, 4.5V) is applied to the selected gate line SGD, SGS applies a positive voltage (for example, 4.5V), turns on the bit line selection transistor TD and the source line selection transistor TS, and applies 0V to the common source line. In the programming (writing) operation, a high-voltage programming voltage Vprog (15V to 20V) is applied to the selected word line, and an intermediate potential (such as 10V) is applied to the non-selected word line to turn on the bit line selection transistor TD , the source line selection transistor TS is turned off, and a potential corresponding to data "0" or "1" is supplied to the bit line GBL. In the erasing operation, 0V is applied to the selected word line in the block, a high voltage (such as 20V) is applied to the P well, and the electrons in the floating gate are extracted to the substrate, thereby erasing in blocks. Delete data.

Next, FIG. 8 shows a clamp voltage generation circuit according to an embodiment of the present invention. In the clamp voltage generating circuit 200 of the present embodiment, the same configurations as those of the clamp voltage generating circuit 10A shown in FIG. 2 are denoted by the same reference numerals, and redundant descriptions will be omitted.

The clamp voltage generation circuit 200 of this embodiment is formed in the peripheral circuit 182 of the flash memory 100, and the VCLMP (clamp) voltage generated in the clamp voltage generation circuit 200 is supplied to the page buffer/readout The n+1 bit lines in the circuit 170 are respectively connected to the gates of the charge transfer transistors TG.

In the clamp voltage generation circuit 200 of this embodiment, the simulation transistor 80 of the clamp voltage generation circuit 10A shown in FIG. Preferably, the constant voltage output circuit 210 is constituted by including a regulator that outputs a constant voltage, the reference voltage VREF of the input node N3 is input to the non-inverting input terminal of the regulator 210, and the feedback emulation transistor 220 is used for the inverting input terminal. The source of , that is, the voltage of node N5. Regulator 210 is controlled according to the feedback to output the VCLMP voltage of VREF+Vth.

An NMOS transistor 220 for dummy is connected in series between the VDD power supply and the node N5. That is, the drain of the transistor 220 is connected to the VDD power supply, the source is connected to the node N5, and the VCLMP voltage of the regulator 210 is supplied to the gate of the transistor 220 . When the transistor 220 is turned on, the node N5 starts charging, which is fed back to the regulator 210 . The regulator 210 controls the VCLMP voltage so that the voltage of the node N5 is equal to the reference voltage VREF. The voltage of the node N5 is equivalent to VREF, so the VCLMP voltage is feedback-controlled to be VREF+Vth.

The second current setting circuit 230 is connected in series with the transistor 220 for simulation. The second current setting circuit 230 has a configuration similar to that of the current setting circuit 40 , but the second current setting circuit 230 can set a finer current value than the current setting circuit 40 . The second current setting circuit 230 includes a plurality of parallel-connected NMOS transistors (here, four transistors TR5 to TR8 ) and four current sources 231 to 234 connected in series to each transistor. Clamp control signals CLMP5 to CLMP8 are input to the gates of the transistors TR5 to TR8, respectively, and the transistors TR5 to TR8 are turned on/off, respectively. Each of the constant current sources 231 to 234 flows constant currents of, for example, 0.125 μA, 0.25 μA, 0.5 μA, and 1.0 μA. With 16 combinations of 4-bit clamp control signals CLMP4 to CLMP8 , currents from 0.125 μA to 2 μA can be set in steps of 0.125 μA, for example.

The second current setting circuit 230 can replicate the current of the bit line BL in the page buffer/read circuit during read. In a preferred embodiment, in order to prevent unevenness of each chip in a semiconductor wafer (wafer), a fuse register or a fuse read-only memory is prepared for each chip, and the fuse register or fuse ROM is used to store The binary data of the clamp control signal CLMP5 to CLMP8 is used as the copy data. For example, in the semiconductor wafer stage, the current value discharged from the bit line of the selected chip or test device is measured, and the fuse is trimmed based on the measurement result, and the copy data is stored in the fuse register of each chip. Furthermore, the codes of the clamp control signal CLMP1 to CLMP4 of the first current setting circuit 40 may also be similarly stored in a fuse register or the like. In addition, when the controller 150 reads, it can read the clamp control signal CLMP1 to the clamp control signal CLMP4 or the clamp control signal CLMP5 to the clamp control signal CLMP8 from the fuse register to set the first current setting. The current value of the circuit 40 and the second current setting circuit 230 . Moreover, in other embodiments, it is also possible to store the binary data of the clamp control signal CLMP5 - CLMP8 in units of blocks of the flash memory rather than in units of chips. The clamp control signals CLMP5 - CLMP8 of the block corresponding to the selected page are used to set the current value of the second current generating circuit 230 . In a more preferred embodiment, the reference voltage VREF (node N3) input to the non-inverting input terminal of the constant voltage output circuit 210 can be output to the outside or measured in order to set the clamp control signal CLMP5 ~ clamp control signal CLMP8.

FIG. 9 is a diagram for explaining the operation of the clamp voltage generating circuit of the present embodiment. The regulator 210 , that is, the constant voltage output circuit 210 outputs the VCLMP voltage of the reference voltage VREF+Vth according to the feedback of the node N5 . The VCLMP voltage is supplied to the gate of the dummy transistor 220 and further supplied to the gates of the charge transfer transistors TG connected to the bit lines BL in the page buffer/read circuit 170 . The second current generation circuit 230 adopts a structure that can adjust the drain current I'ds of the dummy transistor 220 to the drain current Ids of the charge transfer transistor TG, thereby making the drain/source gap between the charge transfer transistor TG The condition of the voltage is very close to the condition of the voltage between the drain and the source of the transistor 220 for simulation. This suppresses the generated VCLMP voltage from deviating from the target voltage. Furthermore, the drain current of the dummy transistor 220 is made equal to the drain current of the charge transfer transistor by the clamp control signal CLMP5 to the clamp control signal CLMP8 of the second current generation circuit 230, thereby suppressing the unevenness of the VCLMP voltage. .

In a more preferred implementation manner, the clamp voltage generation circuit 200 of this embodiment is controlled by the controller 150 to make the current I'ds flowing through the transistor 220 variable during readout, thereby, for example, during precharging Initially, the precharge time of the bit line BL overdriven by a relatively large drain current Imax can be shortened. The second current setting circuit 230 can set the drain current Imax (Imax=I'ds×k: k is an arbitrary coefficient) based on the clamp control signal CLMP5 ~ clamp control signal CLMP8 read from the fuse register, for example. ). Alternatively, the clamp control signal CLMP5 to CLMP8 serving as the drain current Imax may be stored in the fuse register.

FIG. 10 is a diagram showing voltage waveforms at the start of precharge. At time T1, pre-charging starts, and at time T2, the drain current through the overdrive reaches a peak value. The reference voltage VREF rises from the time T1 toward the time T2, and in response to this, the VCLMP voltage is overdriven to 1.2V+Vth+α at the time T2. By this overdriving, the bit line BL is charged with the precharge voltage (1.2 V) at the time T2 or a time later than the time T2. The curve indicated by the dotted line represents the existing precharge time without such overdrive. The second current setting circuit 230 controls so that the increased current Q+αμA flows so as to reach the peak value at time T2, and then controls so that the simulated current QμA flows.

By generating an accurate precharge voltage of the bit line as in the present embodiment, the variation in the discharge time of the bit line is simply a variation specific to the memory cell (depending on the threshold value Vth of the memory cell). Therefore, the readout time of the sense amplifier can be set accurately, and the readout time can be shortened.

In the above-described embodiments, an example was shown in which the clamp voltage generation circuit is used for reading, but other than this, the clamp voltage generation circuit may also be used for verification. Furthermore, in the above-mentioned embodiment, an example was shown in which the first current setting circuit 40 and the second current setting circuit 230 include 4-bit transistors, but the transistors may include a plurality of bits. Furthermore, in the above-mentioned embodiments, the reading of memory cells storing binary data was exemplified, but the present invention is also applicable to a flash memory having memory cells storing binary data. At this time, the clamp voltage generating circuit generates a VCLMP voltage for sensing (sensing) multi-ary data. Furthermore, in the above-mentioned embodiments, the clamp voltage generation circuit of the flash memory has been described, but this clamp voltage generation circuit can also be used in other semiconductor memories.

Preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

Claims (11)

1. A semiconductor memory device comprising a clamp voltage generating circuit for supplying a clamp voltage to a charge transfer transistor coupled to a read node of a bit line, the semiconductor memory device being characterized in that, The clamp voltage generation circuit includes: A transistor for simulation, the drain is coupled to the first potential, the source is coupled to the node, and the clamping voltage is coupled to the gate; a current setting member connected between the node and a second potential, and sets a current flowing from the node to the second potential; and The constant voltage output means receives the voltage fed back from the node and a reference voltage, and controls the output of the clamp voltage so that the fed back voltage matches the reference voltage. 2. The semiconductor memory device according to claim 1, wherein: The current setting means sets a drain current of the transistor for simulation. 3. The semiconductor memory device according to claim 1 or 2, wherein: The current setting means includes a plurality of current setting transistors connected in parallel, and current sources respectively connected in series to the plurality of current setting transistors, and the current setting means is configured by making the plurality of current setting transistors The current setting transistor selected among the setting transistors is turned on to set the current. 4. The semiconductor memory device according to claim 1 or 2, wherein: The flash memory also pre-stores copy data copied with a current of the bit line, and the current setting means sets the current based on the copy data. 5. The semiconductor memory device according to claim 4, wherein: The duplicate data is stored in a fuse register of each semiconductor chip. 6. The semiconductor memory device according to claim 3, wherein: The flash memory also pre-stores the replica data replicating the current of the bit line, The current setting means selects a current setting transistor to be turned on based on the replica data. 7. The semiconductor memory device according to claim 1, wherein: The current setting means sets a relatively large drain current of the dummy transistor for a fixed period when precharging the bit line via the charge transfer transistor starts, and sets a drain current of the dummy transistor after the fixed period ends. A current flowing through the current setting means emulates a drain current of the charge transfer transistor. 8. The semiconductor memory device according to claim 7, wherein: The relatively large drain current is stored in memory in advance. 9. The semiconductor memory device according to claim 1, wherein: The first potential is equal to a potential supplied to the readout node, and a drain current of the dummy transistor is equal to a drain current of the charge transfer transistor. 10. The semiconductor memory device according to claim 1, wherein: The constant voltage output means includes a regulator that inputs the reference voltage to a non-inverting input terminal, inputs the fed-back voltage to an inverting input terminal, and outputs the clamp voltage. 11. The semiconductor memory device according to claim 1, wherein: The constant voltage output means includes a current mirror circuit for generating the reference voltage based on the selected current value, the current mirror circuit being coupled to a third potential greater than the first potential.