TWI514379B - Memory device for reducing leakage current - Google Patents

Description

Memory device for reducing leakage current

The present invention relates to memory devices, and more particularly to memory circuits for reducing leakage current.

FIG. 1A is a block diagram of a conventional memory device 10, and FIG. 1B is a timing chart of signals in the memory device 10. In FIG. 1A, the memory device 10 includes a word line WL, a first bit line BL, a second bit line BLB, a memory unit 11 and a bit line balance circuit 12, wherein the memory device 10 is a random access memory, and the memory unit 11 is a memory cell. The memory unit 11 is coupled to the word line WL, the first bit line BL, and the second bit line BLB. The bit line balancing circuit 12 is coupled to the first bit line BL and the second bit line BLB. The bit line balancing circuit 12 receives a balanced signal EQL for balancing the voltages on the first bit line BL and the second bit line BLB. (as shown in Figure 1B).

In FIG. 1A, when the memory device 10 is to read the stored data stored on the memory unit 11, the control terminal (not shown) of the memory device 10 turns on the word line WL (as shown in FIG. 1B). And, the output balance signal EQL is stopped to the bit line balance circuit 12 (or the balance signal EQL is set to a low voltage level as shown in FIG. 1B) to turn off the operation of the bit line balance circuit 12. When the word line WL is turned on, the memory unit 11 outputs the stored data therein to the first bit line BL and the second bit line BLB. Then, coupled to one of the first bit line BL and the second bit line BLB A sense amplifier (not shown) senses one of the differential voltages on the first bit line BL and the second bit line BLB. Therefore, the memory device 10 can know the content of the stored data (high voltage level or low voltage level) by sensing the sensing result of the amplifier.

The memory device 10 turns off the word line WL (as shown in FIG. 1B, the word line WL voltage returns to the low voltage), and outputs the balanced signal EQL to the bit line balance circuit 12 (or as shown in FIG. 1B, Set the balanced signal EQL to a high voltage level). The bit line balance circuit 12 is maintained in an on state according to the control of the balance signal EQL, and pulls the first bit line BL and the second bit line BLB to equal voltage levels.

When the logic of the balanced signal EQL is set to a high voltage level, the forward voltage of the output generates a leakage current between the gate of each transistor and the substrate in the bit line balancing circuit 12. The leakage current wastes the power of the memory circuit, and the higher the voltage level of the balanced signal EQL corresponds to a larger leakage current. Due to the evolution of the current integrated circuit process technology (process miniaturization), the component size of the integrated circuit device is getting smaller and smaller. As the thickness of the gate of the transistor becomes thinner, it causes a more serious leakage current on the gate of the transistor. Taking a dynamic memory of 38 nm process as an example, a voltage of 1.6 volts is applied to a metal oxide gate device, and the resulting leakage current reaches 1.6 nanoamperes per square micrometer. In the case of a 1G DRAM, the leakage current in its memory array region will exceed 50 microamperes. In view of this, the present invention proposes a new memory device to solve the above problems.

One embodiment of the present invention provides a memory device that reduces leakage current. The memory device for reducing leakage current comprises a word line, a first bit line, a second bit line, a memory unit, a bit line balance circuit and a flat Balance control circuit. The memory unit is coupled to the word line, the first and the second bit line. The bit line balancing circuit is coupled to the first and second bit lines. When the memory unit is not accessed, the bit line balancing circuit is turned on according to a control of the balance signal to balance voltage levels on the first and second bit lines. The balance control circuit outputs the balanced signal to the bit line balancing circuit, and the balanced signal is first maintained at a first voltage level and then decreased to a second voltage level.

10‧‧‧ memory device

11‧‧‧ memory unit

12‧‧‧ bit line balance circuit

20‧‧‧ memory device

21‧‧‧ memory unit

22‧‧‧ bit line balance circuit

23‧‧‧ Balance Control Circuit

221, 222, 223, 315, 333‧‧‧N type transistors

31‧‧‧Delay circuit

32‧‧‧Control logic

33‧‧‧Level control circuit

311, 312, 313‧‧ ‧ inverter

314, 331, 332‧‧‧P type transistor

WL‧‧‧ character line

BL‧‧‧first bit line

BLB‧‧‧ second bit line

SR‧‧‧ Self-refresh signal

ACT‧‧‧ start signal

EQL‧‧‧balance signal

S _A ‧‧‧First voltage level signal

S _B ‧‧‧second voltage level signal

S _C ‧‧‧ third voltage level signal

ACTD‧‧‧Delay start signal

R‧‧‧Resistors

V _A , V _B , VDD, VSS‧‧‧ supply voltage

Figure 1A is a block diagram of a conventional memory device 10.

FIG. 1B is a timing chart of signals in the memory device 10.

2A is a block diagram of a memory device 20 implemented in accordance with an embodiment of the present invention.

2B is a circuit diagram of the bit line balancing circuit 22 of FIG. 2A implemented in accordance with an embodiment of the present invention.

Figure 3A is a circuit diagram of the balance control circuit 23 of Figure 2A implemented in accordance with an embodiment of the present invention.

FIG. 3B is a circuit diagram and timing diagram of the delay circuit 31 of FIG. 3A implemented in accordance with an embodiment of the present invention.

Figure 3C is a circuit diagram of the level control circuit 33 of Figure 3A implemented in accordance with an embodiment of the present invention.

4 is a timing diagram for implementing an enable signal ACT, a balanced signal EQL, and a first bit line BL/second bit line BLB in the memory device 20 in accordance with an embodiment of the present invention.

Figure 5 is a diagram showing the balance in the memory device 20 in accordance with an embodiment of the present invention. Timing diagram of signal EQL and self-refresh signal SR.

Figure 6 is a timing diagram showing the signals in the balance control circuit 23 in accordance with an embodiment of the present invention.

Figure 7 is a timing diagram showing the signals in the balance control circuit 23 in accordance with an embodiment of the present invention.

2A is a block diagram of a memory device 20 implemented in accordance with an embodiment of the present invention. In FIG. 2A, the memory device 20 includes a word line WL, a first bit line BL, a second bit line BLB, a memory unit 21, a bit line balance circuit 22, and a balance control circuit. 23, wherein the memory device 20 is a random access memory, and the memory unit 21 is a dynamic memory cell; however, the invention is not limited thereto. The memory unit 21 is coupled to the word line WL, the first bit line BL, and the second bit line BLB. The bit line balancing circuit 22 is coupled to the first bit line BL and the second bit line BLB. When the memory device 20 is to periodically refresh its memory array, the control terminal (not shown) of the memory device 20 issues a self-refresh signal SR to the balance control circuit 23. When the memory device 20 accesses its memory array (including the memory unit 21), the control terminal of the memory device 20 issues a start signal ACT to the balance control circuit 23. The balance control circuit 23 receives the enable signal ACT and the self-refresh signal SR, and outputs a start signal ACT and a self-refresh signal SR according to the memory device 20 (for example, a control circuit or a command decoder not shown) to output a balanced signal. EQL balances circuit 22 with a control bit line.

In the embodiment of FIG. 2A, when the control terminal of the memory device 20 does not issue the enable signal ACT and the self-refresh signal SR to the balance control circuit 23 (or the low voltage level enable signal ACT and the low voltage level) When the self refresh signal SR is), the word line WL is turned off so that the memory unit 21 is not accessed. The balance control circuit 23 outputs a balanced signal EQL to turn on the bit line balancing circuit 22 to balance the voltage levels on the first and second bit lines BL, BLB. At this time, the balance control circuit 23 maintains the output balance signal EQL first at a first voltage level V ₁ and then down to a second voltage level V ₂ .

When the control terminal of the memory device 20 issues the self-refresh signal SR to the balance control circuit 23 (either the low voltage level enable signal ACT and the high voltage level self-refresh signal SR), the balance control circuit 23 responds to the self-refresh The signal SR reduces the balanced signal EQL from the first voltage level V ₁ to the second voltage level V ₂ . When the self refresh signal SR is not removed and the memory device 20 is accessing the memory unit 21 (at this time, both the enable signal ACT and the self refresh signal SR are high voltage levels), the balance control circuit 23 stops outputting the balance signal. EQL to turn off the operation of the bit line balancing circuit 22. Finally, when the memory unit 21 is accessed, the balance control circuit 23 outputs the balance signal EQL of the second voltage level V ₂ to the bit line balance circuit 22, and maintains the balance signal EQL at the second voltage level. V ₂ .

2B is a circuit diagram of the bit line balancing circuit 22 of FIG. 2A implemented in accordance with an embodiment of the present invention. In FIG. 2B, the bit line balancing circuit 22 includes a first bit line balancing transistor 221, a second bit line balancing transistor 222, and a third bit line balancing transistor 223. In FIG. 2B, the bit line balancing transistors 221, 222, and 223 are all an N-type metal oxide semiconductor field effect transistor (N-type MOSFET); however, the present invention is not limited thereto. One end of the bit line balancing transistor 221 is coupled to the first bit line BL, and the other end is coupled to one end of the bit line balancing transistor 222, and the other end of the bit line balancing transistor 222 It is coupled to the second bit line BLB. The two ends of the bit line balancing transistor 223 are coupled to the first bit line BL and the second bit line BLB, respectively. The gates of the bit line balancing transistors 221, 222, and 223 are all coupled to the same node for receiving the balanced signal EQL from the output of the balance control circuit 23. Due to process miniaturization (eg, a 38 nm process), the forward voltage of the balanced signal EQL output creates a leakage current between the gate of the bit line balancing transistors 221, 222, 223 and the substrate. At this time, if the balance signal EQL is reduced from the first voltage level V ₁ to the second voltage level V ₂ , the leakage current generated between the gate and the substrate by the equipotential line balancing transistors 221 223 223 It becomes smaller.

Figure 3A is a circuit diagram of the balance control circuit 23 of Figure 2A implemented in accordance with an embodiment of the present invention. In FIG. 3A, the balance control circuit 23 includes a delay circuit 31, a control logic circuit 32, and a level control circuit 33. The delay circuit 31 receives the start signal ACT and outputs a delayed start signal ACTD. The control logic circuit 32 receives the start signal ACT, the delayed start signal ACTD, and the self-refresh signal SR, and generates a first voltage level signal S _A , a second voltage level signal S _B and a third voltage level signal accordingly. S _C .

FIG. 3B is a circuit diagram and timing diagram of the delay circuit 31 of FIG. 3A implemented in accordance with an embodiment of the present invention. In this embodiment, the delay circuit 31 includes an inverter 311, an inverter 312, an inverter 313, a P-type transistor 314, an N-type transistor 315, and a resistor R. As shown in FIG. 3B, the power supply voltage VDD is a forward power supply voltage, and the power supply voltage VSS is a ground voltage (or a negative power supply voltage). As shown in FIG. 3B, the delayed start signal ACTD is lowered from the high voltage level to the low voltage level after a delay time as compared with the start signal ACT. In this embodiment, the delay circuit 31 can be balanced according to the bit line. The circuit 22 determines the delay time of the delayed start signal (ACTD) by pulling the first bit line BL and the second bit line BLB to the same voltage level; however, the present invention is not limited thereto.

Figure 3C is a circuit diagram of the level control circuit 33 of Figure 3A implemented in accordance with an embodiment of the present invention. In FIG. 3C, the level control circuit 33 includes a P-type transistor 331, a P-type transistor 332, and an N-type transistor 333. One end of the transistors 331, 332, 333 is coupled to the output of the balance control circuit 23 for outputting the balance signal EQL generated by the balance control circuit 23. Electric crystal 331, the other endpoint is respectively coupled to a first one of the voltage level V ₁ supply voltage V _A, having a second voltage level V of the supply voltage V _{B 2,} and a power source voltage VSS, The power supply voltage V _A and the power supply voltage V _B are both forward power supply voltages, and the power supply voltage VSS is a ground voltage (or a negative power supply voltage).

The first voltage level signal S _A , the second voltage level signal S _B and the third voltage level signal S _C are respectively output to the gates of the transistors 331, 332 and 333 for controlling the transistors 331, 332 and 333. Whether it is conductive. When only the transistor 331, when transistor 331 is turned on, level control circuit 33 outputs a first voltage level V ₁ of the balanced signal EQL. When only the transistor 332 is turned on among the transistors 331, 332, 333, the level control circuit 33 outputs the balance signal EQL of the second voltage level V ₂ . Finally, when the transistor 333 is turned on, the level control circuit 33 outputs a balance signal EQL of the ground voltage (or VSS) level.

4 is a timing diagram for implementing an enable signal ACT, a balanced signal EQL, and a first bit line BL/second bit line BLB in the memory device 20 in accordance with an embodiment of the present invention. In the present embodiment, it is worth noting that in the illustration of FIG. 4, the balance control circuit 23 does not receive the self-refresh signal SR (or the self-refresh signal SR issued by the control terminal of the memory device 20 is maintained at all times). Low voltage level). At time t _4a , the start signal ACT is raised from the low voltage level to the high voltage level (ie, the control terminal of the memory device 10 issues the enable signal ACT to the word line WL and the balance control circuit 23), so that the balance control circuit 23 stops. The balance signal EQL (or the balance signal EQL of the output ground voltage level) is output to the bit line balance circuit 22 to turn off the operation of the bit line balance circuit 22, and the memory device 20 starts to access the memory unit 21.

At time t _4b , the enable signal ACT begins to drop from the high voltage level to the low voltage level (ie, the control terminal of the memory device 10 stops outputting the enable signal ACT to the word line WL and the balance control circuit 23). The word line WL is then turned off. Thereafter, the balance control circuit 23 outputs the balanced signal EQL of the first voltage level V ₁ to the bit line balance circuit 22. The bit line balance circuit 22 is turned on in accordance with the control of the balance signal EQL to pull the first bit line BL and the second bit line BLB to equal voltage levels.

At time t _4c , the bit line balancing circuit 22 has pulled the first bit line BL and the second bit line BLB to equal voltage levels. At this time, the balance control circuit 23 adjusts the voltage level of the output balanced signal EQL from the first voltage level V ₁ to the second voltage level V ₂ .

Figure 5 is a timing diagram for implementing a balanced signal EQL and a self-refresh signal SR in the memory device 20 in accordance with an embodiment of the present invention. At time t _5a , the balanced signal EQL is maintained at the first voltage level V ₁ and the self-refresh signal SR is maintained at the low voltage level. At time t _5b , the self-refresh signal SR is boosted from a low voltage level to a high voltage level, and the memory device 20 begins a periodic self-refresh. The balance control circuit 23 adjusts the voltage level of the output balanced signal EQL from the first voltage level V ₁ to the second voltage level V ₂ . Next, the balance control circuit 23 reduces the output balance signal EQL to the ground voltage level to self-refresh the memory unit 21.

At time t _5c , the memory unit 21 has completed self-refresh, the word line WL is turned off (not shown), and the balance control circuit 23 only raises the voltage level of the output balanced signal EQL to the second voltage level V ₂ . Instead of the first voltage level V ₁ . This is because when the memory device 20 performs periodic self-refresh, the time interval between all the memory cells corresponding to the word line WL being refreshed and being refreshed next time is very long (microsecond level), and the long-time open bit is set. The line balance circuit 22 causes a large power consumption. Therefore, the balance control circuit 23 maintains only the output balance signal EQL at the second voltage level V ₂ , thereby saving power consumption of the memory device 20.

Figure 6 is a timing diagram showing the signals in the balance control circuit 23 in accordance with an embodiment of the present invention. In this embodiment, the self-refresh signal SR sent from the control terminal of the memory device 20 is at a low voltage level (or the self-refresh signal SR is not issued). At time t _6a , both the enable signal ACT and the delayed enable signal ACTD are raised from the low voltage level to the high voltage level. The first voltage level signal S _A is maintained at a high voltage level, and the second voltage level signal S _B and the third voltage level signal S _C are raised from a low voltage level to a high voltage level. At this time, the balance signal EQL outputted by the control level circuit 33 is lowered to the ground voltage level by the second voltage level V ₂ .

At time t _6b , the enable signal ACT is lowered from the high voltage level to the low voltage level, and the delayed enable signal ACTD is maintained at the high voltage level. The second voltage level signal S _B is maintained at a high voltage level, and the first voltage level signal S _A and the third voltage level signal S _C are reduced from a high voltage level to a low voltage level. This causes the balance signal EQL output from the control level circuit 33 to be boosted to the first voltage level V ₁ .

At time t _6c, delayed start signal ACTD by the high voltage level down to the low voltage level, such that the first voltage level signal S _A from the low voltage level to high voltage level to enhance voltage level and a second signal S _B From the high voltage level to the low voltage level. This causes the balanced signal EQL output by the control level circuit 33 to drop from the first voltage level V ₁ to the second voltage level V ₂ .

Figure 7 is a timing diagram showing the signals in the balance control circuit 23 in accordance with an embodiment of the present invention. At time t _7a , the enable signal ACT, the delayed enable signal ACTD, and the self-refresh signal SR are all maintained at a low voltage level. The first, second, and third voltage level signals S _A , S _{B ,} and S _C are respectively at a low voltage level, a high voltage level, and a low voltage level. This causes the control level circuit 33 to output a balanced signal of the first voltage level V ₁ .

At time t _7b , the self-refresh signal SR is boosted from a low voltage level to a high voltage level, and the enable signal ACT and the delayed enable signal ACTD (not shown) are maintained at a low voltage level. The first voltage level signal S _A is raised from a low voltage level to a high voltage level, the second voltage level signal S _B is lowered from a high voltage level to a low voltage level, and the third voltage level signal S _C is Maintain at a low voltage level. This causes the balanced signal EQL output by the control level circuit 33 to drop from the first voltage level V ₁ to the second voltage level V ₂ .

At time t _7c , the enable signal ACT and the delayed enable signal ACTD (not shown) are boosted from a low voltage level to a high voltage level. The first voltage level signal S _{A is} maintained at a high voltage level, and the second voltage level signal S _B and the third voltage level signal S _C are raised from a low voltage level to a high voltage level. This causes the balanced signal EQL output by the control level circuit 33 to be lowered from the second voltage level V ₂ to the ground voltage level.

At time t _7d , the enable signal ACT is lowered from the high voltage level to the low voltage level, and the self refresh signal SR and the delayed start signal ACTD (not shown) remain inconvenient. The first voltage level signal S _{A is} maintained at a high voltage level, and the second voltage level signal S _B and the third voltage level signal S _C are lowered from a high voltage level to a low voltage level. This causes the balance signal EQL output from the control level circuit 33 to be raised from the ground voltage level to the second voltage level V ₂ .

It should be noted that, for convenience of description, only one memory unit 21 is illustrated in the embodiment of the present invention; however, all embodiments of the present invention can be applied to any memory circuit having a memory array, and any self-refresh action is required. The memory circuit does not depart from the scope of the invention.

The present invention has been described above in terms of preferred embodiments, so that those skilled in the art can understand the present invention more clearly. However, those of ordinary skill in the art will appreciate that they can readily use the present invention as a basis for designing or modifying the processes and operating different memory devices for the same purpose and/or to achieve the same advantages of the embodiments described herein. Therefore, the scope of the invention is defined by the scope of the appended claims.

20‧‧‧ memory device

21‧‧‧ memory unit

22‧‧‧ bit line balance circuit

23‧‧‧ Balance Control Circuit

WL‧‧‧ character line

BL‧‧‧first bit line

BLB‧‧‧ second bit line

SR‧‧‧ Self-refresh signal

ACT‧‧‧ start signal

EQL‧‧‧balance signal

Claims (6)

A memory device for reducing leakage current, comprising: a word line; a first bit line; a second bit line; a memory unit coupled to the word line, the first and the second bit a first line and a second bit line coupled to the first and second bit lines, and when the memory unit is not accessed, is turned on according to a control of the balance signal to balance the first and the second a voltage level on the bit line; and a balance control circuit that outputs the balanced signal to the bit line balancing circuit, and causes the balanced signal to maintain a first voltage level and then drop to a second voltage level. The memory device for reducing leakage current according to claim 1, wherein when the memory device outputs a self-refresh signal, the balance control circuit returns a self-refresh signal, and the balance signal is used by the first voltage. The level falls to the second voltage level. The memory device for reducing leakage current according to claim 2, wherein the self-refresh signal is not removed and if the memory unit is accessed, the balance control circuit stops outputting the balance signal to turn off The bit line balance circuit. The memory device for reducing leakage current according to claim 3, wherein when the memory unit is accessed, the balance control circuit outputs the balance signal to the bit line balance circuit, and the balance is balanced The signal is maintained at the second voltage level. The memory device for reducing leakage current according to the first aspect of the invention, wherein the balance control circuit further comprises: a control logic circuit, receiving the start signal and the self-refresh signal, outputting a first voltage level signal, a second voltage level signal and a third voltage level signal; and a level control circuit coupled to the control logic circuit, wherein the level control circuit comprises: a first transistor having the first voltage received a gate of the level signal, wherein a first end of the first transistor is coupled to a first voltage source having the first voltage level, and a second end of the first transistor is coupled Connected to an output terminal of the level control circuit; a second transistor having a gate receiving the second voltage level signal, wherein a first end of the second transistor is coupled to the first transistor a second voltage source of the second voltage level, a second end of the first transistor is coupled to an output end of the level control circuit; and a third transistor having the third voltage bit received One of the quasi-signals, the third A first end of the transistor is coupled to an output end of the level control circuit, and a second end of the third transistor is coupled to a ground node. The memory device for reducing leakage current according to claim 5, wherein the control logic circuit further comprises a delay circuit for delaying the turn-on signal to generate the balance signal, so that the balance control circuit is at the first After the second bit line has equal voltage levels, the balance signal is reduced from the first voltage level to the second voltage level.