JP2013038518A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a DLL that can correct variation in a lock phase generated between samples with change in a temperature and the like to make the lock phase constant.SOLUTION: A semiconductor device has: a PD back gate potential changing circuit 106 for changing a back gate potential of a predetermined MOSFET among a plurality of MOSFETs configuring a phase detection circuit (PD) 105; a temperature sensor 107; and a fuse 108 for storing threshold voltage (Vt) information for each sample. Temperature information of the temperature sensor 107 and the threshold voltage (Vt) information for each sample stored in the fuse 108 are read out by the PD back gate potential changing circuit 106 to control a threshold voltage and correct variation in a lock phase.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a DLL (Delay Lock Loop).

  In the DLL, the phase of the input signal is compared with the signal obtained by feeding back the output signal of the delay time variable delay line (delay line) for inputting the input signal, and the delay of the delay line is adjusted based on the phase comparison result. Control is performed so that the phase of the output signal and the input signal becomes a desired value.

  An outline of a DRAM (Dynamic Random Access Memory) device will be described with reference to FIG. 1 as an example of a semiconductor device equipped with this DLL. Although not particularly limited, the DRAM device of FIG. 1 is an 8-bank DDR (Double Data Rate) SDRAM (Synchronous DRAM) that exchanges data in synchronization with both rising and falling edges of the clock. is there. In FIG. 1, a row decoder 1-4 decodes a row address and drives a selected word line (not shown). The sense amplifier 1-2 amplifies the data read to the bit line (not shown) of the memory cell array 1-1, and reads it to the bit line connected to the cell of the word line selected by the refresh address during the refresh operation. The amplified cell data is amplified and written back to the cell. The column decoder 1-3 decodes the column address, turns on the selected Y switch (not shown), selects the bit line, and connects it to the IO line (not shown). The command decoder 1-9 receives a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, etc., and decodes the command (note that the signal name / is Low). Indicates active). The column address buffer and burst counter 1-7 generates an address corresponding to the burst length from the input column address under the control of the control logic 1-10 that receives a control signal from the command decoder 1-9. This is supplied to the decoder 1-3. The mode register 1-5 receives the address signal and bank selection signals BA0, BA1, and BA2 (select one of the eight banks) and outputs a control signal to the control logic 1-10. The row address buffer of the row address buffer and refresh counter 1-6 receives the input row address and outputs it to the row decoder 1-4. When the refresh counter is input, for example, the command decoder 1- On the basis of the decoding result in 9, the count-up operation is performed in response to the control signal from the control logic 1-10, and the count output is output as the refresh address. In the self-refresh mode at the time of low power operation, for example, the refresh counter is incremented in a refresh cycle defined by an internal timer (not shown) to obtain a refresh address. The row address from the row address buffer and the refresh address from the refresh counter are input to a multiplexer (not shown). At the time of refresh, the refresh address is selected. Otherwise, the row address from the row address buffer is selected, and the row decoder 1-4.

  The clock generator 1-14 receives complementary external clocks CK and / CK supplied to the DRAM device. When the clock enable signal CKE is High, the clock generator 1-14 outputs an internal clock signal, and when the clock enable signal CKE becomes Low, The supply of the internal clock signal is stopped. The data control circuit 1-8 performs input / output of write data and read data. The latch circuit 1-11 latches write data and read data. The input / output buffer 1-13 inputs and outputs data from the data terminal DQ.

  The DLL 1-12 generates a signal delayed and synchronized with the external clock signals CK and / CK and supplies the signal to the input / output buffer 1-13. Read data from the memory cell array 1-1 is supplied from the latch circuit 1-11 to the input / output buffer 1-13, and the input / output buffer 1-13 rises and falls on the clock signal synchronized with the external clock CK in the DLL 1-12. Using the falling edge, read data is output from the data terminal DQ at a double data rate.

  DQS is a data strobe signal that defines the timing of data write (write) and read (read), and is an input signal input from a controller (not shown) outside the DRAM during a write operation, and during a read operation. , An output signal (IO signal) output from the DRAM to the controller side. In synchronization with the external clocks CK and / CK, the DDR SDRAM inputs and outputs data (DQ) with reference to both rising and falling edges of DQS. The DQS is output from the DRAM in synchronization with the rising edge of the clock signal CK during the read operation, and is delayed from the controller (not shown) by a predetermined phase from the rising edge of the clock signal CK to the DRAM side during the write operation. Entered. At the time of writing, the DRAM latch circuit 1-11 receives data from the input / output buffer 1-13 (the DQ terminal is connected to the input buffer of the input / output buffer 1-13) at the timing of the edge of the DQS input from the controller (not shown). (Write data input from). At the time of reading, a receiver such as a controller (not shown) takes in read data output from the DQ terminal of the DRAM at the timing of both edges (rising edge and falling edge) of DQS.

  In the DLL 1-12, a signal obtained by delaying the input external clock signal (CK) by the delay line is further delayed by a replica (Replica) (not shown) of the output buffer (output circuit) of the input / output buffer 1-13. The phase of the replica clock signal (Repclk) and the external clock signal CK are compared, and the delay time of the delay line is varied so that these phases match. When reading data, if the data strobe signal DQS having the same phase as the replica clock signal (Repclk) can be output to the outside (controller or the like) as an output signal, the DQS has the same phase as the external clock signal CK.

  FIG. 2 shows an example of a typical configuration of the DLL and its peripheral circuits (output circuit and replica circuit). As shown in FIG. 2, a delay line 100 that inputs a DRAM input signal, and a replica circuit 104 that receives a DLL output signal that is an output of the delay line 100 and has a delay T ′ imitating the delay time T of the output circuit 103. A phase detection circuit (PD: Phase Detector) 105 that receives a replica clock signal Repclk, which is an output signal of the replica circuit 104, and a DLL input signal (DRAM input signal) and compares the phases of the two, and a phase detection circuit 105 Are provided as a delay line increase / decrease signal and a decoder circuit 101 for decoding the count value of the counter circuit 102 and setting the delay time of the delay line 100. In the delay line 100, unit delay circuits are connected in a plurality of stages, and the number of stages from which an output signal is extracted is determined based on the output of the decoder circuit 101 (if the number of unit delay circuits increases, the delay of the DLL output signal is increased). The time increases, and if the number of unit delay circuits decreases, the delay time of the DLL output signal decreases). The phase detection circuit (PD) compares the phases of two input signals (Repclk and DLL input signal) and detects which edge is advanced (delayed) in time. Or it is also called a phase comparator. When the phase of the replica clock signal Repclk is delayed with respect to the DRAM input signal as a result of the comparison in the phase detection circuit 105, the counter circuit 102 counts down, for example, and the decoder circuit 101 reduces the delay time of the delay line 100. When the phase of the replica clock signal Repclk is shorter than that of the DRAM input signal, the counter circuit 102 counts up, for example, and the decoder circuit 101 increases the delay time of the delay line 100.

  Here, the concept of the phase in the DLL will be described with reference to FIG. In FIG. 3, an input signal is an input signal to the DLL (external clock signal CK), and an output signal is an output signal of the DLL. FIG. 3 schematically shows the phase difference between the input and output signals in the unlocked DLL. The DLL adjusts the delay time of the delay line to match the edge A of the DLL input signal (external clock signal CK in FIG. 1) with the edge B of the DLL output signal (replica clock signal Repclk in FIG. 2). That is, the input signal edge A and the output signal edge B are set to A = B (c = 0) by delaying the input signal by the delay line 100 for a time corresponding to c = ba in FIG. A state where c = 0 is referred to as a “lock state” (or also referred to as a “phase matching state”).

  In FIG. 2, the delay (T ′) of the replica circuit 104 imitates the inherent delay (T) of the output circuit 103, and thus a circuit having the same configuration as the output circuit 103 is generally mounted as the replica circuit 104. . The output circuit 103 receives the DLL output signal and outputs a DRAM output signal (data signal) in response to the edge of the DLL output signal. Since the output circuit 103 and the replica circuit 104 are provided in the same chip, variations in the threshold voltage (Vt) of MOSFETs (MOS field effect transistors) at the time of semiconductor manufacture are the same. Therefore, with the same structure, the output circuit 103 and the replica circuit 104 can be expected to have the same delay time. In addition, since the temperature characteristics of the threshold voltage (Vt) are the same in the output circuit 103 and the replica circuit 104, even when the threshold voltage (Vt) of the MOSFET changes due to a temperature change during operation or the like, The replica circuit 104 changes in the same manner. Therefore, the delays T and T ′ of the output circuit 103 and the replica circuit 104 may be considered equal.

  In FIG. 2, a phase detection circuit (PD) 105 compares the phase of a DLL input signal (DRAM input signal) and a replica clock signal (Repclk) before and after. The phase comparison result of the phase detection circuit (PD) 105 may be referred to as “Rep phase information”. The phase comparison result obtained by the phase detection circuit (PD) is sent to the counter circuit 102 as a delay line increase / decrease signal. When the edge of the replica clock signal (Repclk) is earlier than the edge of the DRAM input signal (CK) (when the replica clock signal (Repclk) reaches the phase detection circuit (PD) 105 earlier than the DRAM input signal (CK) ), The counter value of the counter circuit 102 is increased, the number of delay stages of the delay line 100 is increased via the decoder circuit 101, the delay time is increased, and the replica clock signal (Repclk) is further delayed. The counter circuit 102 is configured as an up / down counter that counts up / down based on an initial value (for example, zero), and the delay time is longer than the reference (initial setting value) delay according to the positive / negative of the count value. / Select the output of the unit delay circuit located in the short number of stages. When the number of bits and the sign (code) of the count value of the counter circuit 102 are configured as a code that can select one of the unit delay outputs corresponding to the plurality of stages of the delay line, the decoder circuit It is considered unnecessary.

  When the edge of the replica clock signal (Repclk) is later than the edge of the DLL input signal (DRAM input signal CK) (therefore, when Repclk reaches PD later than CK), the counter value of the counter circuit 102 is decreased. The number of delay stages of the delay line is decreased, and the edge of Repclk is advanced.

  By continuing the above series of operations, finally, the edge A of the replica clock signal (Repclk) output from the replica circuit 104 in FIG. 2 continues to cross the phase of the DRAM input signal (CK). To reach. That is, in FIG. 3, c = 0 and the state in which edge B is advanced or delayed in phase from edge A is repeated. This is the locked state, in which the delay of the delay rain 100 in FIG. 2 is adjusted so that the phase of Repclk matches the phase of CK.

  When the DLL is locked, the phase difference generated between the replica clock signal (Repclk) output from the replica circuit 104 and the DRAM input signal (CK) is referred to as “lock phase” (or “lock phase difference”). The lock phase is desirably 0 in nature, but a certain amount of shift occurs depending on conditions such as the circuit type and the use voltage. For this reason, in general, in the DLL lock, the lock phase is taken into consideration, and the lock is performed by considering a certain amount of shift in advance from the value that originally obtains the lock phase 0.

  Patent Document 1 discloses a DLL including a phase detection circuit (see FIG. 2 of Patent Document 1).

JP 2010-62937 A

  The following is an analysis of related technology.

  In the phase detection circuit (PD), when the threshold voltage (Vt) of the MOSFET constituting the phase detection circuit (PD) changes, the operation of the phase detection circuit (PD) changes. The change in the phase detection circuit (PD) operation appears as a change in the phase comparison operation between the external clock signal CK and the replica clock signal (Repclk). That is, the threshold voltage (Vt) variation (manufacturing variation) that exists between samples (chips), and even in the same sample (within the same chip), the threshold voltage (Vt) varies due to changes in operating temperature, etc. The lock phase (the phase difference generated between Repclk and CK when locked) changes. A change in the lock phase accompanying a change in the threshold voltage (Vt) will be described below.

  The threshold voltage (Vt) differs between different samples (chips). In this case, the lock phase differs between samples.

  Although the same sample (within the same chip), the threshold voltage (Vt) differs depending on the operating temperature. In this case, although it is the same sample, the lock phase changes depending on the operating temperature.

  FIG. 4 is a diagram showing the lock phase in the DRAM device. In FIG. 4, the left Y-axis represents the lock phase. The white square (□) is the phase comparison result ↑ (up) of the phase detection circuit (PD), the black diamond (♦) is the phase comparison result ↓ (down) of the phase detection circuit (PD), and the right Y axis = The current value, the white triangle (Δ), represents the current.

  The first line of the X axis is the temperature, and is −5, 110, 25 (partial conditions only) ° C.

  The second row of the X axis is the operating voltage of the phase detection circuit (PD) (1.1V only in this example).

  The third row on the X axis is an input signal reference level (assuming complementary inputs (complementary clocks CK / CKB) such as DRAM).

When the input VDD is 1.3, 1.5, 1.7 V and the input swing is 0.25 V, the following classification is made. As a clock waveform cross point (point where the rising and falling edges of complementary clocks (CK, / CK) cross)
“Low” means cross point between CK and /CKB=47.5 [%]
“Pen” is the cross point of CK and /CKB=50.0 [%] (high and low center, Duty = 50% symmetrical waveform),
“High” is the cross point between CK and /CKB=52.5 [%].

The fourth line on the X axis shows the power supply voltage (VDD),
The fifth line on the X-axis shows the threshold voltage (Vt) at the time of manufacture.
It is.

  When attention is paid to temperature / threshold voltage (Vt) fluctuations in the above classification, the lock phase difference between the circled 1 and 2 that is the worst case in FIG. 3 is 50 ps. It can be seen that the lock phase difference exists uniformly in other situations. Thus, it can be seen that the lock phase varies depending on the process-threshold voltage (Vt) condition (P), the operating voltage condition (V), and the temperature condition (T).

  According to FIG. 4, the Lock phase can vary by, for example, about 50 ps with the PVT condition variation. As described above, the continuity of the lock phase is not maintained. Therefore, there is a need for a system that corrects and responds to fluctuations in the lock phase that occur with sample / temperature displacement.

  In addition, with the recent trend of lowering the voltage, the above fluctuation range is considered to expand.

  In order to solve at least one of the above problems, the present invention is generally configured as follows (but not limited to the following).

  According to the present invention, there is provided a semiconductor device including a correction circuit that corrects a threshold voltage of a predetermined transistor among a plurality of transistors constituting a DLL phase detection circuit.

  According to the present invention, it is possible to correct the fluctuation of the lock phase that occurs due to the displacement between samples, temperature, etc., and make the lock phase constant.

It is a figure which shows an example of the semiconductor device provided with DLL. It is a figure which shows an example of a structure of DLL. It is a figure explaining the phase difference in DLL of an unlocked state. It is the figure which illustrated the displacement of the lock phase according to PVT conditions. It is a figure which shows the structure of one Embodiment of this invention. It is a figure which shows the structure of a phase detection circuit (PD). It is a figure which shows an example of a structure of PD back gate electric potential change circuit.

  A typical example of a technical idea (concept) for solving the problems of the present invention is shown below. However, it goes without saying that the claimed content of the present application is not limited to this technical idea, but is the content described in the claims of the present application. According to some preferred embodiments, a phase detection circuit (105) that compares the phases of the first signal and the second signal, and a predetermined transistor among a plurality of transistors that constitute the phase detection circuit (105). A correction circuit (for example, the PD back gate potential changing circuit 106 in FIG. 5) for correcting the threshold voltage is provided. The phase detection circuit (105) compares the phases of the DLL input signal and output signal, and outputs a signal for increasing or decreasing the delay time of the DLL delay line.

  According to a preferred embodiment, the sensor further includes a sensor (107 in FIG. 5) for detecting the temperature inside the semiconductor device, and the correction circuit includes the phase detection circuit based on the temperature information detected by the sensor (107). The threshold voltage of the predetermined transistor to be configured is corrected. Alternatively, a storage unit (108) for storing threshold voltage information of transistors in units of semiconductor devices or in units of semiconductor device groups (for example, in units of wafers or lots) is provided, and the correction circuit is stored in the storage unit. The threshold voltage of the predetermined transistor constituting the phase detection circuit is corrected based on the threshold voltage information of the transistor for each semiconductor device or for each semiconductor device group.

  According to a preferred embodiment, the correction circuit includes a voltage source circuit (1064 in FIG. 7) that generates a voltage to be applied to a back gate of the predetermined transistor that constitutes the phase detection circuit (105). The back gate voltage is variably set based on the temperature information and / or threshold voltage information of the transistor stored in the storage unit.

  A replica circuit (104) simulating a delay of an output buffer circuit (103) that outputs a data signal to an output terminal in response to the signal output from the delay line (100) of the DLL is provided, and the delay line (100 ) Is delayed by the replica circuit (104) and input to the phase detection circuit (105).

  According to the present invention, the threshold voltage Vt of the transistor of the phase detection circuit is dynamically corrected according to the temperature and sample conditions. According to some preferred modes (Preferred Modes), a change in the threshold voltage (Vt) of the MOS transistor constituting the phase detection circuit (PD) is corrected, and the lock phase generated for each sample or each operating temperature is corrected. This eliminates the variation in phase difference that occurs between Repclk and CK during locking.

  The DLL has a circuit configuration in which a phase comparison with an external clock is performed using a replica clock signal (Repclk), and the delay time of the delay line is feedback-controlled. The replica circuit delay simulates the delay time of the output circuit (delay time T = T ′ in FIG. 2), so that the lock phase is read during the lock operation, and the phase detection circuit (PD) The phase of the replica clock signal (Repclk) is determined before and after (which edge is positioned before the time).

  As described above, the phase detection circuit (PD) is affected by the threshold voltage (Vt) of the MOSFET constituting the phase detection circuit (PD) and has a problem that the lock phase changes. This can be corrected.

<Embodiment>
FIG. 5 is a diagram for explaining an embodiment of the present invention. 2, a PD back gate potential changing circuit 106 that changes the back gate potential of a predetermined MOSFET among a plurality of MOSFETs constituting the phase detection circuit (PD) 105, and a temperature sensor (ATCSR (Auto Temperature Compensated). Self Refresh (automatic temperature compensation self-refresh) 107 and a fuse 108 that stores threshold voltage (Vt) information for each sample are provided, temperature information of the temperature sensor 107, and a sample stored in the fuse 108. The different threshold voltage (Vt) information is read to the PD back gate potential changing circuit 106.

  In FIG. 5, a delay line 100, a decoder circuit 101, a counter circuit 102, an output circuit 103, and a replica circuit 104 are the same as those in FIG. That is, the configuration shown in FIGS. 1 and 2 further includes the temperature sensor 107 in FIG. 5, a fuse 108 for storing threshold voltage (Vt) information for each sample, and a PD back gate potential changing circuit 106. However, this is an example of the semiconductor device according to this embodiment. Note that the fuse 108 shown in FIG. 5 may be any other nonvolatile storage device such as a ROM (Read Only Memory). Note that threshold voltage (Vt) information for each sample is set in the fuse 108 and the like at the time of device manufacture (for example, at the time of wafer test or product shipment). In the following, in the present embodiment, overlapping description of common parts with respect to FIG. 1 is avoided.

Although not particularly limited, in the present embodiment, ATCSR is used as the temperature sensor 107. The ATCSR is a type of temperature sensor mounted on a DRAM product, and automatically changes the refresh interval according to ambient temperature information detected by a temperature sensor incorporated in the DRAM device. In the case of DRAM, for example, mounting of the ATCSR function is becoming common in low voltage operation products such as mobile use and high speed operation products after DDR3. In addition, when the present invention is applied to a low-voltage operation product and a high-speed operation product equipped with an ATCSR, it is not necessary to newly install a thermometer, and the temperature information output from the ATCSR built-in temperature sensor can be used. That's fine. Although not particularly limited, information read by the ATCSR function is set as digital information in a temperature register or the like. As the temperature sensor 107 in FIG. 5, a diode element or the like (PN junction element) is incorporated in the semiconductor device, a constant current is passed through the diode element, and the voltage between terminals is converted into temperature information by analog-digital conversion, for example, by an AD converter. It is good also as composition to do. Between the current (forward current) I flowing through the diode element, the anode-cathode voltage V, and the absolute temperature T,
I≈I _s exp (qV / kT) (1)
There are relationships (however, I _s saturation current (reverse saturation current), q is the unit charge, k is Boltzmann's constant), taking the logarithm of both sides of the above equation,
V = (kT / q) ln (I / I _s ) (2)
And the voltage V is proportional to the absolute temperature T.

  The threshold voltage (Vt) of the MOS transistor (MOSFET) utilizes a substrate bias effect that changes depending on the back gate potential (substrate potential) of the MOSFET, and the PD back gate potential changing circuit 106 is configured to output temperature information from the temperature sensor 107, Further, the back gate potential of the MOSFET is controlled based on the threshold voltage (Vt) information 108 for each sample by a fuse or the like. The threshold voltage (Vt) of the MOSFET has a negative temperature characteristic, and the threshold voltage (Vt) decreases as the temperature rises.

ただし、
Ｖ_ｔ０はＮｃｈ−ＭＯＳＦＥＴの場合、界面がｐ基板と同程度にｎ型に反転したときのゲート電圧であり、γは基板バイアス効果係数（典型的には、０．３〜０．４Ｖ^１/2）、φＦは（ｋＴ／ｑ）ｌｎ（Ｎ_ｓｕｂ／ｎ_ｉ）（ただし、ｑは単位電荷、ｋはボルツマン定数、Ｎ_ｓｕｂは基板の不純物濃度、ｎ_ｉは真性半導体内のキャリア（電子）濃度）、Ｖ_ｓｂはソース・基板間電圧（又は、ソース・ウェル間電圧）である。 The threshold voltage (Vt) of the MOSFET is given by the following equation (3).

However,
In the case of an Nch-MOSFET, V _t0 is a gate voltage when the interface is inverted to the n-type as much as the p substrate, and γ is a substrate bias effect coefficient (typically 0.3 to 0.4 V ^{1 / 2),} .phi.F is _{(kT / q) ln (n} sub / n i) ( although, q is the unit charge, k is Boltzmann's _{constant, n sub} is the impurity concentration of the substrate, _{n i} is the carrier in the intrinsic semiconductor (electronic) Concentration), V _sb is a source-substrate voltage (or source-well voltage).

In the case of an Nch-MOSFET, when the back gate potential (substrate potential or the potential of the P-well where the Nch-MOSFET is formed) is lowered below the source potential (for example, VSS) (set to a negative potential), V _sb becomes a positive value. From Equation (3), Vt increases from the value V _t0 when the back gate potential = VSS. On the other hand, when the back gate potential is raised above the source potential (for example, VSS), Vt decreases from the value V _t0 when the back gate potential = VSS. On the other hand, in the case of the Pch-MOSFET, when the back gate potential is raised above the power supply VDD, the absolute value | Vt | of the threshold voltage (Vt) increases from the absolute value | V _t0 | When the back gate potential is lowered below the power supply VDD, the absolute value Vt of the threshold voltage (Vt) is smaller than the absolute value | V _t0 | when the back gate potential = VDD.

  For example, as shown in FIG. 7, the PD back gate potential changing circuit 106 reads the temperature information of the temperature sensor 107 and the threshold voltage (Vt) information for each sample stored in the fuse 108, respectively. Based on read information of the input circuits 1061 and 1062 and the first and second input circuits 1061 and 1062, a back for determining a back gate potential of a predetermined MOSFET among a plurality of MOSFETs constituting the phase detection circuit (PD) 105. A gate potential determining circuit 1063, a voltage source circuit 1064 for outputting the back gate potential determined by the back gate potential determining circuit 1063 to the back gate of the MOSFET, and a control circuit 1065 are provided. The control circuit 1065 controls the control signal (instruction signal / timing signal) for controlling the start / stop of reading of the first and second input circuits 1061 and 1062 and the start / stop of the operation of the back gate potential determination circuit 1063. A control signal (instruction signal, timing signal) for controlling the voltage source circuit 1064 and a control signal for controlling the voltage source circuit 1064 are supplied. Although not particularly limited, the back gate potential determination circuit 1063 includes a ROM (Read Only Memory) that stores correspondence between measured ambient temperature information and the back gate voltage of the Pch-MOSFET or the Nch-MOSFET in a table format. For example, an address corresponding to the ambient temperature may be input to the ROM and the back gate potential read out. Further, ROM gate address information is generated from information obtained by combining the threshold voltage information (Vt) for each sample read by the second input circuit 1062 and the temperature information read by the first input circuit 1061 to generate back gate voltage information. May be obtained. In this case, the threshold voltage of the PD MOSFET can be controlled in a sample-dependent and temperature-dependent manner. The voltage source circuit 1064 is composed of a programmable constant voltage source whose output voltage can be variably set, and a back gate voltage VBB is applied to a well contact in which a predetermined MOSFET of the phase detection circuit (PD) 105 is formed. Supply. When there is no instruction from the control circuit 1065, the control circuit 1065 outputs VSS (VDD potential as the back gate potential of the Pch-MOSFET), for example, as the back gate potential VBB of the Nch-MOSFET, and the back gate potential determination circuit When new back gate potential information is determined from 1063, a new back gate potential VBB may be output to the back gate of, for example, a MOSFET of the phase detection circuit (PD) based on an instruction from the control circuit 1065. . In the case of the Nch-MOSFET, the threshold voltage (Vt) is set to VBB <VSS to be higher than that of VBB = VSS, and VBB> VSS to be lower. The threshold voltage (Vt) information for each sample is a set of chips (chip group) such as for each chip, a wafer unit on which the chip is formed, or a lot unit (for example, one lot is 12 or 25 wafers). ) The threshold voltage information may be set in units.

  In the present embodiment, the timing for acquiring the temperature information is not particularly limited in the PD back gate potential changing circuit 106. However, for example, the temperature information may be acquired in response to self-refresh in a DRAM device. . Alternatively, the temperature information may be acquired from the CPU outside the DRAM device according to the contents of a command or the like set in the DRAM via the controller. Although not particularly limited, the threshold voltage (Vt) information for each sample may be set and stored in the second input circuit 1062 from the fuse 108 at the time of initial setting such as when the DRAM device is powered on. The self-refresh mode is started by setting the clock enable signal CKE (see FIG. 1) from High to Low when a self-refresh start command (SRE command) is input. During the self-refresh, the clock enable signal CLK is held low. The internal clock is stopped when the clock enable signal CLK is set to Low. The refresh cycle of self refresh is controlled by an internal timer or the like. When the clock enable signal CKE is changed from Low to High, the self-refresh mode ends. The DLL is once reset at the start of self-refresh, and can be operated at the end of self-refresh. Therefore, when the PD back gate potential changing circuit 106 acquires temperature information from the temperature sensor 107 in synchronization with the start of self-refresh, etc., the temperature information from the temperature sensor 107 is stored in the register of the first input circuit 1061 or the like. The timing signal for setting is, for example, a pulse (one-shot or multi-shot pulse) generated in the control circuit 1065 in response to the transition of the clock enable signal CKE from High to Low, the occurrence of a timeout of the internal timer, or the like. You may make it perform.

  An operation example of threshold voltage control in the Nch-MOSFET of the phase detection circuit (PD) 105 will be described.

(1) In the case of a wafer having a high threshold voltage (Vt) of the Nch-MOSFET, based on the threshold voltage (Vt) information for each sample stored in the fuse (Fuse) 108, the PD back gate potential change circuit 106 -Raise the back gate potential of the MOSFET (P well potential where the Nch-MOSFET is formed) and lower the threshold voltage (Vt). In the Nch-MOSFET, an N + diffusion layer (source / drain) and a gate therebetween are formed in a P well provided on a silicon substrate, and a back gate is a P well. The well potential of the P well in which the Nch-MOSFET is formed is raised.

  In the case of a wafer having a lower threshold voltage (Vt), the PD back gate potential changing circuit 106 lowers the back gate potential of the Nch-MOSFET (P well potential in which the Nch-MOSFET is formed) to reduce the threshold voltage (Vt). Raise.

(2) The threshold voltage (Vt) is lowered at a low temperature when the threshold voltage (Vt) increases. That is, the PD back gate potential changing circuit 106 increases the well potential of the P well in which the Nch-MOSFET is formed.

  At a high temperature at which the threshold voltage (Vt) decreases, the threshold voltage (Vt) is increased. The PD back gate potential changing circuit 106 lowers the well potential of the P well in which the Nch-MOSFET is formed.

  The above optimum values (temperature, Nch-MOSFET back gate potential, Vt information for each sample and Nch-MOSFET back gate potential) are obtained in advance by simulation or the like, and ATCSR information, threshold voltage (Vt) information (fuse 108, etc.) In this case, the PD back gate potential changing circuit 106 may change the frequency dynamically.

Next, an operation example of threshold voltage control in the Pch-MOSFET of the phase detection circuit (PD) 105 will be described.
(1) In the case of a wafer having a high threshold voltage (Vt), the threshold voltage (Vt) is lowered. In the Pch-MOSFET, a P + diffusion layer (source / drain) and a gate therebetween are formed in an N well provided on a silicon substrate, and a back gate is an N well. The PD back gate potential changing circuit 106 lowers the well potential of the N well in which the Pch-MOSFET is formed.

  In the case of a wafer having a low threshold voltage (Vt), the threshold voltage (Vt) is increased (the substrate potential is increased). The PD back gate potential changing circuit 106 raises the well potential of the N well in which the Pch-MOSFET is formed.

(2) The threshold voltage (Vt) is lowered at a low temperature when the threshold voltage (Vt) increases. The PD back gate potential changing circuit 106 lowers the well potential of the N well in which the Pch-MOSFET is formed.

  At a high temperature at which the threshold voltage (Vt) decreases, the threshold voltage (Vt) is increased. The PD back gate potential changing circuit 106 raises the well potential of the N well in which the Pch-MOSFET is formed.

  The above optimum values (temperature, back gate potential of Pch-MOSFET, Vt information by sample and Pch-MOSFET back gate potential) are obtained in advance by simulation or the like, and ATCSR information, threshold voltage (Vt) information (Fuse etc.) Change dynamically according to (hold). Note that the substrate potential (well potential) is reversed between the Nch-MOSFET and the Pch-MOSFET.

  Along with the operations (1) and (2), the threshold voltage (Vt) of the MOSFET constituting the phase detection circuit (PD) 105 is always kept constant. Therefore, the change of Rep phase information which has been generated for each sample and for the same sample operating temperature is suppressed. Therefore, the continuity of the lock phase is maintained.

  Note that when the back gate potentials of the Nch-MOSFET and the Pch-MOSET are controlled independently, a twin well CMOS process having a P well and an N well on a silicon substrate may be used.

  In contrast to the trend of reduced current consumption and low voltage operation, recently, the trend of semiconductor products has been aimed at reducing current consumption and low voltage operation. In order to reduce current consumption, it is effective to increase the threshold voltage (Vt) of the MOSFET and reduce leakage current and the like. However, as the threshold voltage (Vt) rises, the gate overdrive (= Vgs (gate-source voltage) −threshold voltage (Vt)) in the MOSFET operation decreases, raising the minimum operating voltage of the MOSFET. It can be said that the increase in the threshold voltage (Vt) goes against the trend of low voltage operation. For this reason, currently, only a part of MOSFETs in the same chip (by making different during design / manufacturing etc.) is dealt with by adopting a low threshold voltage (Vt) -MOSFET.

  Although there is an example in which a low threshold voltage (Vt) -MOSFET is adopted in the phase detection circuit (PD), the threshold voltage (Vt) of the MOSFET constituting the phase detection circuit (PD) can be applied by applying the present invention. Can be changed dynamically. That is, the phase detection circuit (PD) is manufactured using the same (or higher) threshold voltage (Vt) as the other elements, and uses the substrate potential changing circuit 106 of the phase detection circuit (PD) during operation. It is possible to take measures such as reducing only the threshold voltage (Vt) of 105.

  According to the present embodiment, by dynamically changing the threshold voltage (Vt) of the MOSFET, the current consumption can be reduced and the low voltage operation can be performed without using the low threshold voltage (Vt) -MOSFET for the phase detection circuit (PD). It can be said that an effective response to the trend is possible.

  Since the phase detection circuit (PD) can be dynamically reduced in threshold voltage (Vt), the entire semiconductor product is manufactured with a higher threshold voltage (Vt), and efforts are being made to reduce the leakage current of the entire product. However, by changing the threshold voltage (Vt) of the MOSFET of the phase detection circuit (PD), it is possible to apply the same lock phase as that of the normal product.

  According to this embodiment, the manufacturing cost can be reduced. That is, when each element other than the phase detection circuit (PD) can be designed with the normal threshold voltage (Vt), the low threshold voltage (Vt) -MOSFET must be introduced only for the phase detection circuit (PD). This led to an increase in manufacturing costs. When the present invention is applied and each element other than the phase detection circuit (PD) can be manufactured with the normal threshold voltage (Vt) -MOSFET, the low threshold voltage (Vt) -MOSFET manufacturing process itself can be eliminated. A case can be assumed. For this reason, it goes without saying that a reduction in manufacturing process leads to a cost reduction.

  According to the present embodiment, it is possible to cope with high-frequency operation. That is, as described above, according to the present invention, the variation in the lock phase between samples and the variation in operating temperature are reduced. Therefore, it is effective in satisfying a strict timing margin during high-frequency operation. High-frequency operation semiconductors inevitably have strict timing specifications, but if the phase detection circuit (PD) has the same format, the variation distribution of the lock phase does not change and the influence on the timing specifications becomes relatively large. Go. As described above, the lock phase changes depending on the temperature, the threshold voltage (Vt), etc. As described above, by applying the present invention, the constant lock phase can be maintained, thereby adversely affecting the timing specifications. It is possible to suppress.

  As described above, the phase detection circuit (PD) of this embodiment also has an advantage for high-frequency operation.

  Furthermore, the flexibility of the circuit format and the use for a phase detection circuit (PD) with an amplifier circuit become possible. According to the present invention, the purpose is to make the threshold voltage (Vt) of a MOS transistor constant. Therefore, if there is a phase detection circuit (PD) of a type that has been conventionally not used, fluctuations in the threshold voltage (Vt) have a great influence on the lock phase, and this can be realized by applying the present invention. It becomes easy.

  The circuit example shown in FIG. 6 is an example of a phase detection circuit (PD) that uses a dynamic amplifier that is sensitive to threshold voltage (Vt) fluctuations. In the dynamic amplifier, when a clock signal is activated (for example, a high pulse), a current source that drives the amplifier is activated and an amplification operation is performed.

  The phase comparison circuit of FIG. 6 latches differentially the differential output (DLSAT, DLSAB) of the Nch differential pair (201, 202) that constitutes a voltage comparator that compares the voltages of CK and CKB. Differential flip-flops (203, 204, 205, 206), circuits (211 to 213) for precharging and equalizing the differential outputs (DLSAT, DLSAB), and a differential pair (201 202), circuits (210, 208) for controlling the activation of the current source (207).

  When the rising edge of the replica clock signal Repclk arrives, the state of the complementary clock signals CK and CKB is grasped. The state of the clock signals CK and CKB at the time when the replica clock signal Repclk changes from Low to High is sampled. If CK is High, a Low pulse is output to the normal terminal COT that outputs the comparison result. If CKB is High, a Low pulse is output to the inverting terminal COB that outputs the comparison result. When the replica clock signal Repclk changes from High to Low, both COT and COB are set to High, and both are held at High until the next comparison operation (input of a High pulse of the replica clock signal Repclk). Note that / CK (a complementary signal of the clock signal CK) in FIGS. 1 and 5 is input to the CKB in FIG.

  More specifically, as shown in FIG. 6, Nch-MOSFETs 201 and 202 in which commonly connected sources are connected to VSS via Nch-MOSFETs 207 and 208 and CK and CKB (/ CK) are input to the gates, Pch-MOSFETs 204 and 206 whose sources are connected to the power source VPERI, drains are connected to the drains of the Pch-MOSFETs 204 and 206, respectively, and Nch-MOSFETs 203 and 205 whose commonly connected sources are connected to the drain of the Nch-MOSFET 209 , Pch-MOSFETs 212 and 213 whose sources are connected to the power supply VPERI, and Pch-MOSFETs 211 connected between the drains of the Pch-MOSFETs 212 and 213. The drain of the Pch-MOSFET 212 is connected to the drain of the Nch-MOSFET 201 at the DLSAB node, and further connected to the connection point of the drains of the Pch-MOSFET 204 and the Nch-MOSFET 203. The DLSAB node is connected to the input of the inverter 214. The drain of the MOSFET 213 is connected to the drain of the Nch-MOSFET 202 at the DLSAT node, and further connected to the connection point of the drains of the Pch-MOSFET 206 and the Nch-MOSFET 205, and the DLSAT node is connected to the input of the inverter 217. The Nch-MOSFET 203, the common drain, and the common gate are shared with the common gate of the Pch-MOSFET 206 and the Nch-MOSFET 205. They are cross-connected to the drain. Output signals of the inverters 217 and 214 are inverted by inverters (inverted output buffers) 218 and 216, respectively, and output to terminals COT and COB. The Pch-MOSFETs 211, 212, and 213 and the Nch-MOSFETs 207 and 209 are connected to the replica clock signal Repclk, and the signal Repclk2 obtained by inverting the replica clock signal Repclk by the inverter 210 is input to the gate of the Nch-MOSFET 208. When the replica clock signal Repclk changes from Low to High, Repclk2 changes from High to Low after the propagation delay time of the inverter 210 has elapsed. Therefore, the Nch-MOSFETs 207 and 208 are turned on during a period from when Repclk changes from Low to High to when Repclk2 changes from High to Low, and a constant current is supplied to the common source of the differential pair transistors 201 and 202. Although not particularly limited, the Nch-MOSFET 207 is configured as a constant current source transistor, and the Nch-MOSFET 208 is configured as a switch transistor that controls activation of the constant current source transistor 207 based on Repclk2. Nch-MOSFETs 207, 208, and 209 are Repclk input discharge circuits, Nch-MOSFETs 201 and 202 are CK and CKB input discharge circuits, MOSFETs 203, 204, 205, and 206 are dynamic buffers, 211 is an equalizer, and Pch-MOSFETs 212 and 113 are precharged. The circuit is configured. The power supply VPERI is a power supply for driving the peripheral circuit of the DRAM of FIG. In FIG. 6, the internal power supply voltage VDD or the like may be used instead of VPERI. Of course, the output of the phase detection circuit may be a single-ended output instead of the differential outputs COT and COB.

  As shown in FIG. 6, in this embodiment, the back gates of the Nch-MOSFETs 201, 202, 207, 208, etc. are connected to the back gate bias voltage VBB output from the PD back gate potential changing circuit 106 instead of VSS. Has been.

  The potential polarity of CK and CKB when the rising edge of the replica clock (Repclk) arrives is output as information after the inverters 214 and 217. That is, when CK = Low and CKB = High at the timing of the rising edge of Repclk, COT = High and COB = Low. That is, the phase of Repclk is ahead of CK (Repclk is insufficiently delayed), and the delay value of the delay line 100 (see FIG. 5) is increased by increasing the counter value of the DLL counter circuit 102 (see FIG. 5). Let

  When CK = High and CKB = Low at the timing of the rising edge of Repclk, COT = Low and COB = High. The phase of Repclk is delayed from CK (the delay of Repclk is excessive), and the counter value of DLL counter circuit 102 (see FIG. 5) is decreased to reduce the delay of delay line 100 (see FIG. 5). .

  During the Low period from the falling edge of the replica clock signal Repclk to the arrival of the rising edge, the precharge Pch-MOSFETs 212 and 213 and the equalizing Pch-MOSFET 211 are on (conducting state). Further, the Nch-MOSFETs 208 and 209 of the replica input discharge 220 are turned off (non-conductive state), and the output nodes DLSAT and DLSAB of the differential pair (201 and 202) are both set to the high potential (VPERI) (precharge state). , COT, and COB are set to a high potential. Even in this precharge state, CK and CKB are input from the outside. Although the Nch-MOSFETs 210 and 202 have a certain level of analog gate level, the replica / input discharge circuit 220 is inactivated, and the potential of the common source of the Nch-MOSFETs 210 and 202 is kept almost constant.

  At the rising edge of the replica clock signal Repclk, the potentials of the sources of DLSAB and Nch-MOSFETs 210 and 202 are lowered. At this time, since the gate potentials of the Nch-MOSFETs 210 and 202 are in a complementary relationship, a potential difference occurs between the two (one is higher than the other). Therefore, a difference occurs in the potential between the nodes DLSAB and DLSAT. Since a state in which a potential difference is generated between DLSAB and DLSAT occurs in a dynamic amplifier (two CMOS inverters (consisting of (203, 204) and (205, 206)) whose inputs and outputs are cross-connected, the potential difference is generated. The differentially amplified potential difference between the DLSAT and DLSAB nodes propagates from the output terminals COT and COB to the outside (counter circuit 102 in FIG. 5) through the inverters 217 and 218 and the inverters 214 and 216. To do.

  The amplification operation by the dynamic amplifier is incorporated in the phase detection circuit (PD) because the semiconductor product external input (CK, CKB) is a differential near the reference level Vef set to 1/2 of the power supply level or the like. This is because the signal has a small amplitude. That is, assuming that the common voltage is Vref, Vref ± ΔV (amplitude = 2ΔV, Vref = VDD / 2, Vref + ΔV <VDD). Although differential transmission with a small amplitude is highly effective in suppressing power consumption during signal propagation, amplification by a receiver (for example, a phase detection circuit (PD)) that receives the differential signal is necessary.

  In a circuit that handles such a small amplitude differential signal, the influence of the threshold voltage (Vt) that affects the characteristics is relatively large. In order to suppress the influence of the threshold voltage (Vt) for each sample and each operating temperature, conventionally, for example, the following measures have been taken.

(A) The input / discharge transistors (201, 202, 207-209) are set to a low threshold voltage (Vt).

(B) Increase the size of the input / discharge transistor.

  These measures are aimed at increasing the initial differential potential of the dynamic amplifier by increasing the current of the input / discharge transistor when the rising edge of the replica clock signal Repclk arrives. Although essential sample and operating temperature variations cannot be suppressed, the operation of the dynamic amplifier is ensured even under conditions where the initial differential potential is small, which contributes to relative leveling of the operation. it can. However, as the current of the input discharge transistor increases, the current consumption of the entire phase detection circuit (PD) increases, and there are many problems such as not being an essential measure for reducing variation.

  On the other hand, the equalization of the threshold voltage (Vt) according to the present embodiment is applied to a type having an amplifier circuit such as the phase detection circuit (PD) shown in FIG.

  According to this embodiment, the back gate of the Nch-MOSFT (201, 202, 207-209) is connected to the back gate bias voltage VBB from the PD back gate potential changing circuit 106, for example, by setting VBB> VSS. Achieving low threshold voltage. In addition, the conventional variation by sample and temperature can be essentially eliminated, and an increase in current of the input / discharge transistor can be suppressed.

  Furthermore, according to this embodiment, there exist the following effects.

  The substrate potential of the phase detection circuit (PD) is changed on the basis of threshold voltage (Vt) information for each sample by ATCSR (for example, a thermometer provided in a DRAM or the like as a standard), Fuse or the like. With the change of the substrate potential, the lock phase derived from the operation of the phase detection circuit (PD) is corrected and leveled.

  In application to the DLL, the change of the substrate potential has only to be applied to the phase detection circuit (PD), and the degree of increase in complexity is small.

  It can respond to the trend of reduced current consumption and low voltage operation.

  The manufacturing cost can be reduced.

  It is possible to cope with high frequency operation.

  By applying it to a circuit that is sensitive to changes in the threshold voltage (Vt), it is possible to further increase the practicality of the phase detection circuit (PD).

As described above, in the embodiment, the present invention is applied to the phase detection circuit (PD) with an amplifier circuit (dynamic amplifier).
・ Stabilization of lock phase,
-Reduction of power consumption of the phase detection circuit (PD) itself,
• The operation of reducing the size of the MOS transistor constituting the phase detection circuit (PD) has been described.

  The technical idea of the present invention can be applied to various semiconductor devices. For example, a CPU (Central Processing Unit), an MCU (Micro Control Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), and an ASP (Amplified Semiconductor). The present invention can be applied. Examples of the product form of the semiconductor device to which the present invention is applied include SOC (system on chip), MCP (multichip package), POP (package on package), and the like. The present invention can be applied to a semiconductor device having any of these product forms and package forms. Further, the transistor may be a field effect transistor (FET), and besides MOS (Metal Oxide Semiconductor), MIS (Metal-Insulator Semiconductor), TFT (Thin Film Transistor), etc. it can. It can be applied to various FETs such as transistors. Furthermore, some bipolar transistors may be included in the device. Further, the PMOSFET (P-type channel MOSFET) is a second conductivity type transistor, and the Nch-MOSFET (N-type channel MOSFET) is a typical example of the first conductivity type transistor.

  Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1-1 Memory Cell Array 1-2 Sense Amplifier 1-3 Column Decoder 1-4 Row Decoder 1-5 Mode Register 1-6 Row Address Buffer and Refresh Counter 1-7 Column Address Buffer and Burst Counter 1-8 Data Control Circuit 1 -9 Command decoder 1-10 Control logic 1-11 Latch circuit 1-12 DLL
1-13 Input / Output Buffer 1-14 Clock Generator 100 Delay Line 101 Decoder Circuit 102 Counter Circuit 103 Output Circuit 104 Replica Circuit 105 Phase Detection Circuit (PD)
106 PD back gate potential change circuit (power supply circuit)
107 ATCSR (thermometer)
108 Vt information by sample using fuse, 204, 206, 211-213 Pch-MOSFET
201-203, 205, 207-209 Nch-MOSFET
210, 214, 217 Inverter 216, 218 Output buffer (inverter)
219 Dynamic amplifier 220 Replica clock input discharge 1061, 1062 Input circuit 1063 Back gate potential determination circuit 1064 Voltage source circuit 1065 Control circuit

Claims (9)

A phase detection circuit for comparing the phases of the first signal and the second signal;
A correction circuit for correcting a threshold voltage of a predetermined transistor among a plurality of transistors constituting the phase detection circuit;
A semiconductor device comprising: A sensor for detecting the temperature inside the semiconductor device is provided.
The semiconductor device according to claim 1, wherein the correction circuit corrects a threshold voltage of the predetermined transistor constituting the phase detection circuit based on temperature information detected by the sensor. A storage unit that stores threshold voltage information of transistors for each semiconductor device or for each semiconductor device group,
The correction circuit corrects a threshold voltage of the predetermined transistor constituting the phase detection circuit based on threshold voltage information of the transistor for each semiconductor device or for each semiconductor device group stored in the storage unit. 3. The semiconductor device according to 1 or 2. The correction circuit comprises:
A voltage source circuit for generating a voltage to be applied to a back gate of the predetermined transistor constituting the phase detection circuit, the temperature information from the sensor, and / or a threshold voltage of the transistor stored in the storage unit; 4. The semiconductor device according to claim 3, wherein the back gate voltage is variably set based on information. A DLL (Delay Lock Loop) including a delay line for delaying an input signal input from a semiconductor device external signal, the phase detection circuit, and a counter circuit is provided. The phase detection circuit is output from the delay line. A feedback input of a signal, the feedback input signal and the input signal input from an external signal of the semiconductor device are input as the first and second signals to compare the phases;
5. The counter circuit according to claim 1, wherein the counter circuit varies a count value based on a phase comparison result in the phase detection circuit, and varies a delay time of the delay line based on the count value. 6. Semiconductor device. A replica circuit that mimics the delay of an output buffer circuit that outputs a data signal to an output terminal in response to the signal output from the delay line;
6. The semiconductor device according to claim 5, wherein a signal output from the delay line is input to the replica circuit, and a signal output from the replica circuit is fed back to the phase detection circuit. The phase detection circuit is
A first conductive type differential transistor pair for differentially inputting one of the first and second signals;
A current source transistor of a first conductivity type that supplies a drive current to the differential pair for a predetermined period from the activation timing of the other of the first and second signals;
A precharge / equalize circuit of a second conductivity type for receiving a differential output of the differential circuit at a predetermined potential based on the other signal of the first and second signals;
First and second inverters, each having an input and an output cross-connected and connected to a differential output of the differential circuit;
A first conductivity type transistor switch that is inserted into a power path of the first and second inverters and is controlled to be conductive / non-conductive based on the other signal of the first and second signals;
First and second output buffer circuits respectively receiving differential outputs of the differential circuits;
With
The semiconductor according to claim 6, wherein a back gate of the first conductivity type differential transistor pair, the first conductivity type transistor switch, and the first conductivity type current source transistor is connected to an output of the correction circuit. apparatus. The first signal is a complementary external clock signal input from a semiconductor device external signal;
The second signal is a signal output from the replica circuit;
The activation and deactivation of the second conductivity type precharge / equalization circuit, the first conductivity type transistor switch, and the first conductivity type current source transistor are controlled based on the second signal. The semiconductor device according to claim 7.   3. The semiconductor device according to claim 2, wherein a temperature sensor having an automatic temperature compensation self-refresh function incorporated in the semiconductor device is used as the sensor for detecting temperature.

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