TWI513001B - Thin film transistor substrate, display panel using the same and manufacturing method thereof - Google Patents

Description

Thin film transistor substrate, display panel using same and manufacturing method thereof

The present invention relates to a semiconductor device substrate and a method of fabricating the same, and more particularly to a thin film transistor substrate and a method of fabricating the same.

The flat panel display (FPD) technology has been greatly developed, and the planar display device has gradually replaced the traditional cathode ray tube (CRT) display due to its superior characteristics such as thinness, low power consumption and no radiation. Devices and applications to a wide range of electronic products.

The active matrix type flat display device mainly uses a thin film transistor (TFT) as an electronic switch to charge each pixel. Therefore, the role of thin film transistors in display devices is quite important, and their performance is also a key factor in image display. Under the fixed material process conditions, the charging effect of the thin film transistor is proportional to the channel width/channel length. The larger the channel width or the smaller the channel length, the better the charging effect per unit time.

However, the larger the channel width design, the larger the area occupied by the thin film transistor, and the pixel aperture ratio decreases. The channel length size design is related to the actual process capability and yield considerations, and has its design limitations. As shown in a conventional thin film transistor substrate of FIG. 1, it has a substrate 11, a source 12, an active region 13, a drain 14, a gate insulating layer 15, and a gate 16. The channel length is generally designed to be about 5 microns, so its charging effect is not good.

In addition, the material used in the active region of the conventional thin film transistor is amorphous germanium (a-Si), and its carrier mobility is about 0.5 cm 2 /V*s, which cannot meet the requirements of high frequency driving or high charging capability. .

Therefore, how to provide a thin film transistor substrate and a manufacturing method thereof can overcome the process and material limitation, and achieve excellent charging effect and carrier mobility of the thin film transistor, which is one of the current important topics.

In view of the above problems, an object of the present invention is to provide a thin film transistor substrate and a method for fabricating the same, which can overcome the process and material limitations, and achieve excellent charging effect and carrier mobility of the thin film transistor.

To achieve the above objective, a method for fabricating a thin film transistor substrate according to an embodiment of the invention includes: depositing a source layer on a substrate; depositing an active layer directly on the source layer, the active layer including a metal oxide semiconductor a material or an organic semiconductor material; a drain layer is directly deposited on the active layer, wherein the active layer contacts the source layer and the drain layer; and a source and an active region are respectively defined from the source layer, the active layer and the drain layer And a drain electrode; a gate insulating layer and a gate layer are sequentially deposited on the drain to cover the source, the active region and the drain; and a gate is defined from the gate layer.

To achieve the above objective, a thin film transistor substrate according to an embodiment of the invention includes a substrate, a source, an active region, a drain, a gate insulating layer, and a gate. The source is disposed on the substrate. The active region is directly disposed on the source, and the active region includes a metal oxide semiconductor material or an organic semiconductor material. The drain is directly disposed on the active area, and the active area contacts the source and the drain. The gate insulating layer is disposed beside the source, the active region, and the side of the drain. The gate is disposed beside the gate insulating layer with respect to the sides of the source, the active region, and the drain.

To achieve the above objective, a display device according to an embodiment of the invention includes a thin film transistor substrate, a pair of substrates, a light modulation layer, and a backlight module. The opposite substrate and the thin film transistor substrate are disposed opposite to each other, and the light modulation layer is disposed between the thin film transistor substrate and the opposite substrate, and the light emitted by the backlight module passes through the thin film transistor substrate, the light modulation layer and the opposite substrate. .

As described above, since the active region of the present invention uses a metal oxide semiconductor material or an organic semiconductor material, such as indium gallium zinc oxide, the carrier mobility is extremely high, about 5 to 20 cm 2 /V*s, thereby The charging performance is greatly improved, and the process is simple, the film can be formed at room temperature and is suitable for a flexible substrate, and can be applied to mass production of a large substrate.

In addition, the source, the active region and the drain of the present invention are formed in a continuous film formation manner, so that the process conditions have the least influence on the materials of the semiconductor layers, contributing to the stability of the device characteristics and the best performance.

In addition, since the source, active region and the drain of the present invention are stacked in a direction perpendicular to the substrate, and the gate is located on the side of the active region, the thickness of the active region is the thickness of the thin film transistor of the present invention. About equal to the channel length, the length of the control channel can be controlled from 300~1000 in the process. Compared with the conventional 5 micrometers, the charging effect of the thin film transistor of the invention is greatly improved, thereby meeting the development requirements of, for example, a liquid crystal display panel or an organic light emitting diode (OLED) panel, and reducing the thin film transistor component. The design area increases the aperture ratio of the pixels to meet the high brightness requirements of the display. In other words, the thin film transistor of the present invention can be designed in a small area to meet the charging capacity of the product, and can be applied to a large-sized panel product or a high aperture ratio product design.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a thin film transistor substrate and a method of manufacturing the same according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein the same elements will be described with the same reference numerals.

2 is a flow chart showing a method of manufacturing a thin film transistor substrate according to a preferred embodiment of the present invention, the method of manufacturing comprising the following steps.

Step S01: depositing a source layer on a substrate.

Step S02: depositing an active layer on the source layer, the active layer comprising a metal oxide semiconductor material or an organic semiconductor material.

Step S03: depositing a drain layer directly on the active layer, wherein the active layer contacts the source layer and the drain layer.

Step S04: defining a source, an active region and a drain from the source layer, the active layer and the drain layer, respectively.

Step S05: depositing a gate insulating layer on the source, the active region and the drain.

Step S06: depositing a gate layer on the gate insulating layer on the source, the active region and the drain, and the gate insulating layer and the gate layer cover the source, the active region and the drain.

Step S07: patterning the gate layer to define a gate.

Step S08: depositing a passivation layer on the gate, the gate insulating layer, the source and the drain.

Step S09: patterning the passivation layer and the gate insulating layer to form a first opening.

Step S10: depositing a transparent conductive layer on the drain and the passivation layer, wherein the transparent conductive layer is in contact with the drain through the first opening.

Step S11: patterning the transparent conductive layer.

After steps S01-S03 deposit the source layer, the active layer and the drain layer in a continuous film formation manner, step S04 may define a source, an active region and a drain by a development etching process. In addition, step S04 may also be performed after step S01 and step S03, that is, after the source layer is deposited in step S01, the source is first defined by a development etching process, and then step S02 and step S03 are performed by continuous film formation. The active layer and the drain layer are deposited, and then the development etching process is used to define the active region and the drain.

The active layer includes a metal oxide semiconductor material such as indium gallium zinc oxide (IGZO), and an organic semiconductor material such as PXX (Peri-Xanthenoxanthen) derivative or Fused thiophene. derivative. Indium gallium zinc oxide has a very high carrier mobility of about 5 to 20 cm 2 /V*s, and its process is simple, can be formed at room temperature and is suitable for flexible substrates, and can be applied to mass production of large substrates.

In addition, step S04 can simultaneously define a first wire from the source layer, and the passivation layer and the gate insulating layer are also formed on the first wire.

Step S07 can simultaneously define a gate, a storage electrode and a second wire by patterning the gate layer.

In step S09, in addition to forming a first opening above the drain, patterning is performed over the first conductive line and the second conductive line to form a second opening and a first opening in the passivation layer and the gate insulating layer. After the three openings, then, in step S10, the transparent conductive layer contacts the first wire through the second opening and contacts the second wire through the third opening.

Step S11: patterning the transparent conductive layer to define a first portion and a second portion, the first portion serving as a pixel electrode connected to the drain, the pixel electrode and the storage electrode forming a storage capacitor, and second Part of the wiring is used as the first wire and the second wire.

A vertical thin film transistor can be fabricated through steps S01 to S07, and the active layer includes a metal oxide semiconductor material or an organic semiconductor material. Since the active layer material is susceptible to the interface caused by the material of the adjacent layer, it is also susceptible to damage caused by the chemical process of the process or contact. In order to improve the problem, in step S02 and step S03, the active layer and the drain layer are deposited in a continuous film formation manner, so that the interface between the active layer and the drain layer is less susceptible to process conditions, thereby producing characteristics. A more stable thin film transistor.

In addition, the source, the active region and the drain of the vertical thin film transistor are vertically arranged, and the gate is located at the side of the active region, and the film thickness of the active region is approximately equal to the length of the transistor channel region, and the channel region The length is thus shortened, thereby greatly increasing the channel width/channel length and thereby improving the conduction effect of the thin film transistor. When the thin film transistor is used as a charging switch, it will produce a better charging effect. The active layer where the active area is located is about 300~1000 after the film is produced. The length of the channel region of the conventional thin film transistor is about 5 micrometers, and the length of the channel region of the vertical thin film transistor is greatly shortened compared with the conventional one.

Since the vertical thin film transistor has a better conduction effect, it only needs a lower layout area to achieve the effect of the conventional thin film transistor, that is, the thin film transistor of the present invention can be designed in a small area. It meets the requirements of product charging capability and can be applied to display panels of various sizes or high aperture ratios, and is particularly suitable for display panels of liquid crystal display panels or organic light emitting diodes (OLEDs).

In addition, the source layer and the drain layer may be the same material, for example, a metal; in addition, the source layer and the drain layer may be different materials, for example, the source layer is a metal material, and the drain layer is indium tin oxide (ITO). ) such as a light-transmitting metal oxide. If the materials of the active layer and the drain layer are indium gallium zinc oxide and indium tin oxide, the active layer and the drain layer can etch the active region and the drain with the same etching solution.

The active layer and the drain layer can be simultaneously patterned. For example, the two layers are defined by the same pattern and etched at the same time, which makes the active region and the sidewall of the drain pole, and the electrons attracted by the gate in the active region. You can follow the shorter path to reach the bungee.

Detailed production processes and variations are illustrated in the following examples.

Hereinafter, a method of manufacturing a thin film transistor substrate according to a preferred embodiment of the present invention will be described with reference to FIGS. 3A to 3S. As shown in FIG. 3A, a source layer 202 is deposited on a substrate 201, and then an active layer 203 is directly deposited on the source layer 202. The active layer 203 comprises a metal oxide semiconductor material or an organic semiconductor material; A drain layer 204 is deposited directly on the active layer 203. The source layer 202, the active layer 203 and the drain layer 204 are deposited in the same cavity in a continuous film formation manner, and the active layer 203 directly contacts the source layer 202 and the drain layer 204, and does not change the cavity during the process. The patterning operation is performed, so that the process conditions have less influence on the material of the semiconductor layer, and the element characteristics of the produced thin film transistor are more stable and can have better performance.

Referring to FIG. 3B to FIG. 3G, the source, active region and drain of the thin film transistor are defined by means of development etching. In FIGS. 3B through 3D, the active layer 203 and the drain layer 204 are simultaneously patterned to define the active region 303 and the drain 304. The patterning process is as follows: a photoresist PR is applied to the drain layer 204, and the photoresist PR is exposed and developed, and the residual photoresist PR represents the active region 303 and the region of the drain 304 (Fig. 3B), and then the photoresist PR The active layer 203 and the drain layer are etched as a mask to define the active region 303 and the drain 304 (Fig. 3C), followed by removal of the photoresist (Fig. 3D).

In FIG. 3C, the active layer 203 and the drain layer 204 are simultaneously etched, so that the active region 303 is aligned with the sidewalls of the drain 304, whereby the current path can be shortened.

After the active layer 203 and the drain layer 204 are patterned at the same time, as shown in FIGS. 3E to 3G, the source layer 202 is patterned to define the source 302 and a first wire 309. The patterning process is as follows: a photoresist PR is applied to the source layer 202 and the drain 304, and the photoresist PR is exposed and developed, and the residual photoresist PR represents a region of the source 302 (FIG. 3E), and then the photoresist is PR. The source layer 202 is etched as a mask, thereby defining the source 302 and the first wire 309 (Fig. 3F), and then removing the photoresist (Fig. 3G).

Next, referring to FIGS. 3H to 3K, the gate insulating layer 205 and the gate layer 206 are sequentially deposited on the drain 304. In FIG. 3H, a gate insulating layer 205 is deposited on source 302, active region 303 and drain 304, and is deposited on first conductor 309. Then, a gate layer 206 is deposited on the surface of the gate insulating layer 205. The gate insulating layer 205 and the gate layer 206 cover the source 302, the active region 303, and the drain 304.

In FIGS. 3I-3K, the gate layer 206 is patterned to define a gate 306, a storage electrode 310, and a second wire 311 on the sides of the active region 303 and the drain 304. The patterning process is as follows: a photoresist PR is applied to the gate layer 206, and the photoresist PR is exposed and developed, and the residual photoresist PR represents a region of the gate 306, the storage electrode 310, and the second wire 311 (FIG. 3I). The gate layer 206 is then etched with the photoresist PR as a mask, thereby defining the gate 306, the storage electrode 310, and the second wire 311 (FIG. 3J), and then removing the photoresist (FIG. 3K).

Referring to FIG. 3L to FIG. 3O, in FIG. 3L, a passivation layer 207 is deposited on the gate 306, the storage electrode 310, the second wire 311, the gate insulating layer 205, the source 302 and the drain 304. In FIG. 3M to FIG. 3O, the passivation layer 207 and the gate insulating layer 205 are patterned to form a first opening 314 exposing the drain 304, and a second opening 315 exposing the first wire 309 and the third opening 316 to be exposed. The second wire 311, the first opening 314 and the second opening 315 pass through the passivation layer 207 and the gate insulating layer 205, and the third opening 316 passes through the passivation layer 207. The three openings are respectively located at the drain 304 and the first wire. 309 is above the second wire 311. The patterning process is as follows: a photoresist PR is applied to the passivation layer 207, and the photoresist PR is exposed and developed. The portion where the photoresist PR is removed represents a region to be electrically connected (FIG. 3M), and then the photoresist PR is used as a mask. A cover is used to etch the passivation layer 207 and the gate insulating layer 205 (Fig. 3N), and then the photoresist is removed (Fig. 3O).

Referring to FIG. 3P to FIG. 3S, in FIG. 3P, a transparent conductive layer 208 is deposited on the patterned passivation layer 207 and filled into the first opening 314, the second opening 315, and the third opening 316. In FIGS. 3Q to 3S, the transparent conductive layer 208 is patterned to define a pixel electrode 312 and a wiring 313. The patterning process is as follows: a photoresist PR is applied to the transparent conductive layer 208, and the photoresist PR is exposed and developed. The residual photoresist PR represents the area of the other electrode of the wiring 313 and the storage capacitor (Fig. 3Q), and then The photoresist PR is used as a mask to etch the transparent conductive layer 208 (Fig. 3R), and then the photoresist is removed (Fig. 3S). It should be noted that, as shown in FIG. 3N, during the etching of the passivation layer 207, a portion of the gate insulating layer 205 is also etched to expose the drain 304 and the first conductive line 309 so that the subsequent transparent conductive layer 208 can be deposited after deposition. The drain 304 is contacted with the first wire 309. After patterning, the pixel electrode 312 contacts the drain 304 through the first opening 314 and forms a storage capacitor with the storage electrode 310. The wire 313 is in contact with the first wire 309 through the second opening 315 and is in contact with the second wire 311 through the third opening 316. The first wire 309 and the second wire 311 are electrically connected to each other through the wire 313.

FIG. 3S shows a thin film transistor substrate according to a preferred embodiment of the present invention. The middle portion is a thin film transistor, and the two sides are respectively a storage capacitor and a wire contact portion, and the thin film transistor substrate can be applied to an active matrix display panel. For example, a liquid crystal display panel. In the application of the liquid crystal display panel, the thin film transistor substrate is assembled with another opposite substrate, and a liquid crystal material is filled in between the two substrates, and a transparent conductive layer of the storage capacitor of the thin film transistor substrate is used as a pixel electrode, and a pixel The potential of the electrode affects the flipping of the liquid crystal material, thereby controlling the transmittance of light through the liquid crystal material.

In addition, an organic light-emitting diode can be further formed on the thin film transistor substrate, and the organic light-emitting diodes can be arranged in an array and can be used for display.

Further, as shown in FIG. 3S, in the thin film transistor of the present embodiment, the gate 306 is shielded from the channel, so that the area covered by the conventional black matrix (BM) can be reduced, and the aperture ratio can be increased upward. Further, in the thin film transistor of this embodiment, the thickness of the active region is approximately equal to the length of the channel.

Further, the method of manufacturing the thin film transistor of the present invention can be carried out in the same chamber, for example, by chemical vapor deposition (CVD) and wet etching, without using dry etching to form a thin film transistor. In other words, the manufacturing method of the present invention eliminates the need to replace the chamber, thereby improving process efficiency, shortening process time, and reducing production costs. In addition, the above manufacturing method was completed using five masks.

The above manufacturing method is merely illustrative and is not intended to limit the present invention. For example, the manufacturing method can be adjusted according to product requirements or process conditions, which are described in the following two embodiments.

As shown in FIGS. 4A-4C, the source layer 202 is patterned to define the source 302 prior to direct deposition of the active layer 203. In FIG. 4A, the source layer 202 is deposited on the substrate 201, and then the photoresist layer PR is applied to the source layer 202, and the photoresist PR is exposed and developed. The portion where the photoresist PR is removed represents the source region (Fig. 4A), then the source layer 202 is etched with the photoresist PR as a mask (Fig. 4B), and then the photoresist is removed (Fig. 4C).

As shown in FIG. 4D to FIG. 4F, in FIG. 4D, an active layer 203 is directly deposited on the source layer 202, and then a drain layer 204 is directly deposited on the active layer 203. The active layer 203 and the drain layer 204 are deposited in the same cavity in a continuous film formation manner, and the active layer 203 and the drain layer 204 are simultaneously patterned to define the active region 303 and the drain 304. The patterning process is as follows: a photoresist PR is applied to the drain layer 204, and the photoresist PR is exposed and developed, and the residual photoresist PR represents the active region 303 and the region of the drain 304 (Fig. 4D), and then the photoresist PR The active layer 203 and the drain layer are etched as a mask to define the active region 303 and the drain 304 (FIG. 4E), and then the photoresist is removed (FIG. 4F).

The manufacturing method of this embodiment first patterns the source layer 202 before depositing the active layer 203 and the drain layer 204, thereby reducing the process of the continuous plating on the active layer 203, the drain layer 204 and the source layer. Negative problems caused by 202, such as stress effects.

After the process of FIGS. 4A to 4F is completed, the manufacturing method shown in FIGS. 3H to 3S can be continued. The manufacturing method of the embodiment requires the use of five masks. In addition, the manner in which the first wire 309 is fabricated is similar to that of the previous embodiment, and will not be described herein.

In addition, in order to reduce the number of reticle used, the defined pattern required for the active region, the drain and the source of the transistor can be fabricated using the same reticle and matching the haze of the halftone pattern.

As shown in FIGS. 5A to 5C, unlike the foregoing embodiment, the manufacturing method utilizes a halftone pattern to pattern the active layer 203, the drain layer 204, and the source layer 202 to define the source 302, and then The height of the halftone pattern is thinned to expose a portion of the drain layer 204, and the active layer 203 and the drain layer 204 are etched to define the active region 303 and the drain 304.

In FIG. 5A, the source layer 202, the active layer 203, and the drain layer 204 are deposited in a continuous film formation manner as in FIG. 3A, and then the photoresist layer PR1 is applied to the drain layer 204, and the photoresist PR1 has a halftone ( The halftone) pattern, then exposing and developing the photoresist PR1, the residual photoresist PR1 representing the region of the source 302 (FIG. 5A), and then etching the active layer 203 and the drain layer 204 with the photoresist PR1 as a mask (FIG. 5B) And etching the source layer 202 to define the source 302 (Fig. 5C).

As shown in FIGS. 5D to 5F, in order to define the active region 303 and the drain 304 using a halftone pattern, the manufacturing method is to thin the height of the halftone pattern and simultaneously pattern the active layer 203 using the thinned halftone pattern. The drain layer 204 is defined to define the active region 303 drain 304. In FIG. 5D, the photoresist PR1 is thinned by the photoresist solvent-dissolving portion, and the remaining photoresist PR1 serves as a mask for the active layer 203 and the drain layer 204. Then, in FIG. 5E, the active layer 203 and the drain layer 204 are simultaneously etched to define the active region 303 drain 304, and finally the photoresist PR1 is removed as shown in FIG. 5F.

The manufacturing method of this embodiment utilizes a halftone etching technique to reduce a mask process and thus reduce costs. After the process of FIGS. 5A to 5F is completed, the manufacturing method shown in FIGS. 3H to 3S can be continued. The manufacturing method of the embodiment requires only four masks. In addition, the manner in which the first wire 309 is fabricated is similar to that of the previous embodiment, and will not be described herein.

In the above embodiments, the current manufacturing process of the conventional thin film transistor can be used to fabricate the above-mentioned thin film transistor, and the thin film transistor substrate can also be used with related extension technologies currently used for various active matrix display panels, for example, in-plane switching. (In Panel Switching, IPS) or Multi-domain Vertical Alignment (MVA) and so on.

3S and FIG. 6, FIG. 3S is a side cross-sectional view of the thin film transistor substrate viewed from a first direction, and FIG. 6 is a partial side cross-sectional view of the thin film transistor substrate viewed from a second direction, a thin film The crystal substrate 2 includes a substrate 201, a source 302, an active region 303, a drain 304, a gate insulating layer 205, and a gate 306. The source 302 is disposed on the substrate 201. The active region 303 is directly disposed on the source 302, and the active region 303 includes a metal oxide semiconductor material or an organic semiconductor material. The metal oxide semiconductor material is, for example, indium gallium zinc oxide. The drain 304 is disposed directly on the active region 303, and the active region 303 contacts the source 302 and the drain 304. The gate insulating layer 205 is disposed on the source 302, the active region 303, and the drain 304. The gate 306 is disposed beside the gate insulating layer 205 with respect to the sides of the source 302, the active region 303, and the drain 304.

The active region 303 is aligned with the sidewalls of the drain 304, and the electrons attracted by the gate in the active region can follow the shorter path to the drain, thereby shortening the current path.

The thin film transistor substrate further includes a passivation layer 207 and a transparent conductive layer 208 (FIG. 3S shows the pixel electrode 312 and the wiring 313 defined from the transparent conductive layer 208). A passivation layer 207 is disposed on the gate 306. The transparent conductive layer 208 is disposed on the passivation layer 207 and the drain 304, and is isolated from the gate 306 by the passivation layer 207.

Since the characteristics of the thin film transistor substrate have been described in detail in the embodiments of the foregoing manufacturing method, the details will not be described again.

Referring to FIG. 7 , a display device 4 includes a thin film transistor substrate 42 , a pair of substrates 41 , a light modulation layer 43 , and a backlight module 44 . The opposite substrate 41 is disposed opposite to the thin film transistor substrate 42. The light modulation layer 43 is disposed between the thin film transistor substrate 42 and the opposite substrate 41. The light emitted by the backlight module 44 passes through the thin film transistor substrate 42 and the light. The modulation layer 43 and the opposite substrate 41, the thin film transistor substrate 42 have the elements as described in the foregoing embodiments.

For example, the display device 4 may be a liquid crystal display device, and the light modulation layer 43 is, for example, a liquid crystal layer that is controlled by an electric field such that light passing therethrough has a change in polarization direction. In addition, the backlight module 44 has a light emitting diode or a cold cathode ray tube as a light source, and the backlight module 44 can be a direct type or an edge type backlight module. The counter substrate 41 has a pair of electrodes, and the electric field formed by the counter electrode and the pixel electrode controls the liquid crystal layer.

In summary, since the active region of the present invention uses a metal oxide semiconductor material or an organic semiconductor material, such as indium gallium zinc oxide, the carrier mobility is extremely high, about 5-20 cm ² /V*s, and thus The charging performance is greatly improved, and the process is simple, the film can be formed at room temperature and is suitable for a flexible substrate, and can be applied to mass production of a large substrate.

In addition, the active region and the drain of the present invention are formed in a continuous film formation manner, so that the process conditions have the least influence on the materials of the semiconductor layers, contributing to the stability of the device characteristics and the best performance.

In addition, since the source, the active region and the drain are stacked in a direction perpendicular to the substrate, and the gate is located on the side of the active region, the active film of the embodiment of the present invention is active. The thickness of the zone is approximately equal to the length of the channel. In the process, the length of the channel can be controlled to be about 300~1000. Compared with the conventional 5 micrometers, the charging effect of the thin film transistor of the invention is greatly improved, thereby meeting the development requirements of, for example, a liquid crystal display panel or an organic light emitting diode (OLED) panel, and reducing the thin film transistor component. The design area increases the aperture ratio of the pixels to meet the high brightness requirements of the display. In other words, the thin film transistor of the present invention can be designed in a small area to meet the charging capacity of the product, and can be applied to a large-sized panel product or a high aperture ratio product design.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

11. . . Substrate

12. . . Source

13. . . Active zone

14. . . Bungee

15. . . Gate insulation

16. . . Gate

201. . . Substrate

202. . . Source layer

203. . . Active layer

204. . . Bungee layer

205. . . Gate insulation

206. . . Gate layer

207. . . Passivation layer

208. . . Transparent conductive layer

302. . . Source

303. . . Active zone

304. . . Bungee

306. . . Gate

309. . . First wire

310. . . Storage electrode

311. . . Second wire

312. . . Pixel electrode

313. . . wiring

314. . . First opening

315. . . Second opening

316. . . Third opening

4. . . Display device

41. . . Thin film transistor substrate

42. . . Counter substrate

43. . . Light modulation layer

44. . . Backlight module

PR. . . Photoresist

PR1. . . Photoresist

S01～S11. . . Steps of a method of manufacturing a thin film transistor substrate

Figure 1 is a schematic view of a conventional thin film transistor;

2 is a flow chart showing a method of manufacturing a thin film transistor substrate according to a preferred embodiment of the present invention;

3A to 3S are schematic views showing a method of manufacturing a thin film transistor substrate according to a preferred embodiment of the present invention;

4A to 4F show another method of manufacturing a thin film transistor substrate;

5A to 5F show still another method of manufacturing a thin film transistor substrate;

Figure 6 is a partial side cross-sectional view of a thin film transistor substrate;

Figure 7 is a schematic illustration of one of the display devices.

S01～S11. . . Steps of a method of manufacturing a thin film transistor substrate

Claims (17)

A method for fabricating a thin film transistor substrate includes: depositing a source layer on a substrate; depositing an active layer directly on the source layer, the active layer comprising a metal oxide semiconductor material or an organic semiconductor material; Depositing a drain layer directly on the layer, wherein the active layer contacts the source layer and the drain layer; and a source, an active region and a source are respectively defined from the source layer, the active layer and the drain layer a drain electrode; a gate insulating layer and a gate layer are sequentially deposited on the drain to cover the source, the active region and the drain; and a gate is defined from the gate layer. The manufacturing method of claim 1, wherein the step of defining a source, an active region and a drain from the source layer, the active layer and the drain layer respectively comprises: simultaneously patterning the After the active layer and the drain layer define the active region and the drain; and simultaneously pattern the active layer and the drain layer, the source layer is patterned to define the source. The manufacturing method of claim 1, wherein the step of defining a source, an active region and a drain from the source layer, the active layer and the drain layer respectively comprises: directly depositing the active Before the layer, the source layer is patterned to define the source; and the active layer and the drain layer are simultaneously patterned to define the active region and the drain. The manufacturing method of claim 2, wherein the simultaneously patterning the active layer and the drain layer comprises simultaneously etching the active layer and the drain layer. The manufacturing method of claim 1, wherein the step of defining a source, an active region and a drain from the source layer, the active layer and the drain layer respectively comprises: using a halftone pattern Patterning the active layer, the drain layer and the source layer; thinning the height of the halftone pattern to expose a portion of the drain layer; and etching the active layer and the drain layer to define the active District and the bungee. The manufacturing method of claim 1, further comprising: depositing a passivation layer on the gate, the gate insulating layer, the source and the drain; patterning the passivation layer and the gate insulating layer Forming a first opening to expose the drain; depositing a transparent conductive layer on the drain and the passivation layer, wherein the transparent conductive layer contacts the drain through the first opening; and patterning the transparent conductive Floor. The manufacturing method of claim 6, further comprising: defining a storage electrode from the gate layer, wherein the step of patterning the transparent conductive layer defines a pixel electrode, the storage electrode and the drawing The element electrode forms a storage capacitor. The manufacturing method of claim 6, further comprising: defining a first wire from the source layer, wherein the passivation layer and the gate insulating layer are formed on the first wire; from the gate Forming a second wire; and patterning the passivation layer and the gate insulating layer to form a second opening exposing the first wire and a third opening exposing the second wire, wherein the transparent pattern is patterned The step of conducting a layer defines a wire that is in contact with the first wire through the second opening and is in contact with the second wire through the third opening. The manufacturing method of claim 1, wherein the active layer comprises a metal oxide semiconductor material. The manufacturing method of claim 9, wherein the active layer comprises indium gallium zinc oxide. A thin film transistor substrate comprises: a substrate; a source disposed on the substrate; an active region disposed directly on the source, the active region comprising a metal oxide semiconductor material or an organic semiconductor material; Directly disposed on the active region, the active region contacts the source and the drain; a gate insulating layer covering the source, the active region and the drain; and a gate located in the active region and The side of the drain is disposed on the gate insulating layer. The thin film transistor substrate of claim 11, wherein the active region is aligned with a sidewall of the drain. The thin film transistor substrate of claim 11, further comprising: a passivation layer disposed on the gate, the gate insulating layer, the source and the drain; a first opening located at the gate a passivation layer and a gate insulating layer; and a pixel electrode disposed on the passivation layer and the drain, and the pixel electrode is in contact with the drain through the first opening. The thin film transistor substrate of claim 13, further comprising: a storage electrode disposed on the gate insulating layer, the storage electrode and the pixel electrode forming a storage capacitor. The thin film transistor substrate of claim 13, further comprising: a first wire disposed on the substrate; a second opening above the first wire, passing through the passivation layer and the gate An insulating layer to expose the first wire; a second wire disposed on the gate insulating layer; a third opening above the second wire, passing through the passivation layer and the gate insulating layer to Exposing the second wire; and a wire contacting the first wire through the second opening and contacting the second wire through the third opening. The thin film transistor substrate of claim 11, wherein the metal oxide semiconductor material is indium gallium zinc oxide. A display device comprising: a thin film transistor substrate according to any one of claims 11 to 16; a pair of substrates disposed opposite to the thin film transistor substrate; a light modulation layer disposed on the Between the thin film transistor substrate and the opposite substrate; and a backlight module, the light emitted by the backlight module passes through the thin film transistor substrate, the light modulation layer and the opposite substrate.