201113952 六、發明說明： 【發明所屬之技術領域】 本發明關於一種顯示裝置、顯示面板、主動元件基 板，特別關於一種顯示裝置、顯示面板、主動元件基板及 其製造方法。 【先前技術】 顯示裝置可依據驅動方式而區分為被動矩陣式 (Passive-Matrix, PM )及主動矩陣式（Active-Matrix, AM )，由於主動矩陣式較被動矩陣式可提供更優良的性能 而成為主流。主動矩陣式顯示裝置藉由薄膜電晶體等主動 元件來進行驅動，然而薄膜電晶體的通道長度卻受到曝光 機的解析度（resolution)的限制，而無法進一步提升驅動 的效能。 圖1A至圖1E為習知例如液晶顯示裝置所使用的薄膜 電晶體的製造流程圖。首先，如圖1A所示，在一玻璃載 板11上形成一閘極12。當然，閘極12的形成包含薄膜沉 積製程、黃光微影（photolithography )製程和姓刻製程而 使其圖案化，其中黃光微影製程可包含上光阻、曝光、顯 影及蝕刻製程後的去光阻等步驟，於此就不再贅述。然 後，如圖1B所示，依序形成一絕緣層13及一通道層14 於閘極12及玻璃載板11之上；其中，通道層14包含一 非晶石夕（amorphous Si，a-Si:H)層 141 及一摻雜層（n+ a-Si) 142。再來，如圖1C所示，形成一汲極15及一源極16於 201113952 通這層14的兩端。在圖1D中，以汲極15及源極16的圖 案作為遮罩（mask)進行摻雜層142的餘刻，使通道層14 具有一凹槽143。然後如圖1E所示，可形成一鈍化 (passivation)層17覆蓋汲極15、源極以及通道層14, 並藉由黃光微影製程和蝕刻製程形成接觸孔（contact hole) Η。接著，如圖ip·所示，沉積一圖案化之畫素電極 層PE於鈍化層17上，且畫素電極層pE經由接觸孔Η而 與汲極15接觸。 藝 在上述製程中，汲極15及源極16的形成亦包含黃光 W影製程，使得及極15與源極μ圖案化。然而，由於黃 光微影製程所使用的曝光機，其解析度有極限，使得汲極 15與源極16的間距D1亦有一定的長度，造成通道層的通 道長度（channel length)(可視為間距Dl)受到限制而無 法再縮短，因而限制元件效能。 因此’如何提供一種顯示裝置、顯示面板、主動元件 癱基板及其製造方法，能夠縮短通道，進而提升元件效能， 只為重要課題之'〇 【發明内容】 有鑑於上述課題，本發明之目的為提供--種能夠縮短 通道，進而提升元件效能的顯示裝置、顯系面板、主動元 件基板及其製造方法。 為達上述目的，依本發明之_種主動元件基板的製造 方法包含以下步驟：形成一通道層於一載板之上；形成一 201113952 汲極及一源極於通道層的兩端；形成一覆蓋層覆蓋通道 層，並覆蓋汲極及源極之至少一部分，且覆蓋層對應通道 層具有一凹部；部分去除覆蓋層，使通道層對應凹部而部 分外露；以及部分去除通道層，使通道層於汲極與源極之 間具有一凹槽。 為達上述目的，依本發明之一種主動元件基板包含一 載板、一通道層、一汲·極、一源極以及一覆蓋層。通道層 設置於載板之上。汲極及源極設置於通道層的兩端，通道 層於汲極與源極之間具有一凹槽。覆蓋層設置於通道層 上，並位於凹槽的外周緣與汲極及源極之間。 為達上述目的，依本發明之一種顯示面板包含一基板 以及一主動元件基板。主動元件基板與基板相對而設，並 包含一載板、一通道層、一汲·極、一源極及一覆蓋層。通 道層設置於載板之上。汲極及源極設置於通道層的兩端， 通道層於汲極與源極之間具有一凹槽。覆蓋層設置於通道 層上，並位於凹槽的外周緣與汲極及源極之間。 為達上述目的，依本發明之一種顯示裝置包含一顯示 面板以及一背光模組，背光模組鄰設於顯示面板。顯示面 板包含一基板及一主動元件基板。主動元件基板與基板相 對而設，並包含一載板、一通道層、一汲極、一源極及一 覆蓋層。通道層設置於載板之上。汲極及源極設置於通道 層的兩端，通道層於汲極與源極之間具有一凹槽。覆蓋層 設置於通道層上，並位於凹槽的外周緣與汲極及源極之 201113952 承上所述’本發明之一種顯示裝置、顯系面板、主動 元件基板及其製造方法在形成汲極及源極之後，並不直接 進4亍通道層的餘刻’而是先形成一覆蓋層覆蓋通道層，以 及汲極與源極之至少一部分，且覆蓋層對應通道層具有一 凹部。然後部分去除（例如蝕刻）覆蓋層，使得通道層對 應四部而部分外露。此時，通道層外露的部分的長度必定 小於汲極與源極的間距，然後再部分去除通道層，即去除 通道層露出的部分，使通道層於汲極與源極之間具有一凹 • 槽’此凹槽可視為一主動元件的通道。如此，本發明能夠 突破傳統曝光機解析度的極限，更縮短通道的長度，進而 促進電場分佈並提升元件效能。此外，在去除製程中’覆 蓋層亦可保護通道層不需去除的部分免受離子的作用’因 而避免產生漏電流（leakage current)。 【實施方式】 • 以下將參照相關圖式，說明依本發明較佳實施例之顯 示裝置、顯示面板、主動元件基板及其製造方法，其中相 同的元件將以相同的參照符號加以說明。 本發明較佳實施例之一種主動元件基板20的製造方 法的流程如圖2A至圖2G所示。在本實施例中，主動元件 是以薄膜電晶體（Thin Film Transistor, TFT )為例。 首先，如圖2A所示，在一載板21上形成一閘極22。 其中’載板21的材質可選自玻璃、塑膠、藍寶石、高分 子及其組合所構成的群組，於此載板21是以坡璃板為例；> 201113952 閘極22藉由薄膜沉積製 微 圖案化並形成於載板2】上，其中黃二二細 光阻、曝光、顯影賴”程後的去絲等㈣， 積可使用濺鍍（sputtering )，蝕刻可使用濕蝕刻（Wd etching)或乾钱刻（~ etching)。另外，閘極22的材質 可包含鉻、鋁、銅或鉬等金屬或合金。 、 如圖2B所示，形成一絕緣層23於閘極22上，並形 成一通道層24於絕緣層23上。絕緣層23與通道層24 ^ 藉由化學氣相沉積（CVD)而形成。絕緣層23的胃材質可 包含氮矽化合物（SiNx)。通道層24具有一半導體層241 及一摻雜層242依序形成於絕緣層23上，半導體^ 241 的材質包含非晶矽（a-Si:H ) ’摻雜層242於此以N ^摻雜 (n+a-Si)為例，例如包含高濃度磷的矽，摻雜層2仏可 降低界面電位差，並形成歐姆接觸（〇hmicc〇mact)。 如圖2C所示，形成一汲極25及一源極26於通道層 24的兩端。汲極25及源極26可藉由黃光微影製程而圖案 化，其中形成汲極25及源極26的步驟包含濺鍍及濕蝕 刻。汲極25及源極26的材質可包含鉻、鋁、銅或鉬等金 屬或合金。 如圖2D所示，形成一覆蓋層28覆蓋通道層24，並覆 蓋汲極25及源極26之至少一部分，於此是以全覆蓋為 例此外，覆盍層28對應通道層24具有一凹部281。覆 蓋層28可藉由化學氣相沉積、旋轉式塗佈（spinc〇ating) 或狹缝式塗佈（slit coating)而形成。在本實施例中，覆 201113952 蓋層28可使用具有較佳似型性（c〇nformity )的材質’例 如矽酸四乙酯（tetraethyl orthosilicate，TEOS)，使得覆蓋 層28在形成後能夠形成明顯的凹部281。 如圖2E所示，部分去除覆蓋層28，使通道層24對應 ,凹部281而部分外露。於此，去除例如以蝕刻方式進行非 等向性（anisotropic)蝕刻，非等向性蝕刻例如為乾蝕刻 (dry etching)。蝕刻後，在汲極25與源極26之間，以及 凹部281的兩侧會有部分的覆蓋層28留下來，且作為通 籲 道層24餘刻的遮罩。 如圖2F所示’部分去除通道層24，使通道層24在汲 極25與源極26之間具有一凹槽243。在本實施例中，蝕 刻方式為非等向性餘刻，例如乾银刻，且部分钱刻通道層 24主要是蝕刻摻雜層242。在蝕刻後，部分覆蓋層28位 於凹槽243的外周緣、汲極25與源極26之間。 在本實施例中’通道層24的通道可視為凹槽243的 • 寬度1)2 ’由於部分覆蓋層28位於汲極25與源極26之間， 且作為通道層24蝕刻的遮罩，故本發明可獲得較習知技 術，短的通道。一般而言，習知的通道由於曝光機的解析 度可達到5微米（μιη)，而本實施例可小於5微米，例如 可達到2微米。 ^如圖2G所示’本實施例可更包含形成—純化層27以 覆疏j道層24、部分源極26及部分汲極25。鈍化層27 的材貝：包含氮矽化合物，並可藉由化學氣相沉積而形 成’並藉由黃光微影製程和㈣製程形成接觸孔（c〇ntact 201113952 hole) Η。接著，如圖2H所示，沉積一圖案化之晝素電極 層ΡΕ於鈍化層27上，且晝素電極層ΡΕ經由接觸孔Η而 與汲極25接觸。 不贫咧急芏動兀仵基板可 • 呀 >卜叫败〇 _ j娜 示本發明較佳實蘭之-種―岐6G。在本實施例中， 顯示面板60是以液晶顯示面板為例作說明， 基 板40、-主動元件基板30以及一液晶層％。基板4〇與 主動元件基板30相對而設，且液晶層5〇設置於基板4〇 與主動元件基板30之間。 本實施例之基板40可視為_彩色渡光基板，並包含 一載板41、一遮光層42、一渡光層43、-純化層44、— 共通電極層45、-配向層46以及—偏光層47。遮光 慮先層43、鈍化層44、共通電極層45及配向層46曰化皮 設置於載板41的青而偏光層〇設置於載板= 一側。由於上述構件料通用技術，故不在此贅述。的另 液晶層50包含液晶分子及複數個間隔物。 主動元件基板3G包含一载板31、—閘極％、 層33、一通道層34、一汲極35、一 、、、邑緣 一覆芸声38 舍主+ 源極36、一鈍化層37、 方。由於上述構件的以 t :徵已於上述實施例詳述，故於此不再贅辻 付“的是，上述構件的製 其他構件的製程整合。例如 :、主動凡件基板30 报士、—妙—士 在形成閘極32時，可回口士 /成儲存笔極39a;在形成沒極^ 问日守 形成另一儲存電極39b，兩儲存電，、… 同時可 柿存t極39a及39b係形成〜 201113952 儲存電容；在形成汲極35與源極36之後，可形成一晝素 電極層3a，且畫素電極層3a與儲存電極39b接觸；在形 成晝素電極層3a之後，可形成另一配向層3b，使得液晶 分子51介於兩配向層46、3b之間。此外，主動元件基板 30更具有一偏光層3c設置於載板31遠離液晶層50之一 側。 此外，本發明之主動元件基板亦可應用於一顯示裝 置。圖4顯示本發明較佳實施例之一種顯示裝置7。在本 • 實施例中，顯示裝置7是以液晶顯示裝置為例作說明，其 包含一顯示面板60以及一背光模組70。由於顯示面板60 已於上述實施例敘明，故於此不再贅述。 背光模組70鄰設於顯示面板60。背光模組70可為側 光式背光模組或直下式背光模組，於此是以侧光式背光模 組為例。背光模組7 0可包含一導光板71、一光源7 2、一 反射罩73、一反射片74以及一光學膜組75。光源72鄰 ^ 設於導光板71的一侧，反射罩73設置於光源72的周緣， 反射片74與光學膜組75設置於導光板71的相對側。由 於上述構件皆為通用技術，故不在此贅述。 綜上所述，本發明之一種顯示裝置、顯示面板、主動 元件基板及其製造方法在形成汲極及源極之後，並不直接 進行通道層的餘刻，而是先形成一覆蓋層覆蓋通道層，以 及汲極與源極之至少一部分，且覆蓋層對應通道層具有一 凹部。然後部分去除（例如钱刻）覆蓋層，使得通道層對 應凹部而部分外露。此時，通道層外露的部分的長度必定 Γ 11 201113952 小於汲極與源極的間距，然後再部分去除通道層，即去除 通道層露出的部分，使通道層於汲極與源極之間具有一凹 槽，此凹槽可視為一主動元件的通道。如此，本發明能夠 突破傳統曝光機解析度的極限，更縮短通道的長度，進而 促進電場分佈並提升元件效能。此外，在去除製程中，覆 蓋層亦可保護通道層不需去除的部分免受離子的作用，因 而避免產生漏電流。 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範疇，而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 【圖式簡單說明】 圖1A至圖1F為一種習知薄膜電晶體的製造流程圖； 圖2A至圖2H為本發明較佳實施例之一種主動元件基 板的製造流程圖； 圖3為本發明較佳實施例之一種顯示面板的示意圖； 以及 圖4為本發明較佳實施例之一種顯示裝置的示意圖。 【主要元件符號說明】 11 :玻璃載板 12、 22、32 :閘極 13、 23、33 :絕緣層 14 ' 24、34 :通道層 12 201113952 141 :非晶矽層 142、 242 :摻雑層 143、 243 :凹槽 15、 25、35 :汲極 16、 26、36 :源極 17、 27、37、44 :純4匕層 20、 30 :主動元件基板 21、 31、41 :載板 # 241 :半導體層 28、38 :覆蓋層 281 :凹部 39a、39b :儲存電極 3a、PE :晝素電極層 40 :基板 42 :遮光層 • 43 :濾光層 45 :共通電極層 46、 3b :配向層 47、 3c :偏光層 50 :液晶層 51 :液晶分子 60 :顯示面板 7 :顯示裝置 70 :背光模組 201113952 71 :導光板 72 :光源 73 :反射罩 74 :反射片 75 :光學膜組 D1 :間距 D2 :寬度 Η :接觸孔BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, a display panel, and an active device substrate, and more particularly to a display device, a display panel, an active device substrate, and a method of fabricating the same. [Prior Art] The display device can be classified into Passive-Matrix (PM) and Active-Matrix (AM) according to the driving method, and the active matrix type can provide better performance than the passive matrix type. Become the mainstream. Active matrix display devices are driven by active components such as thin film transistors. However, the channel length of the thin film transistor is limited by the resolution of the exposure machine, and the driving efficiency cannot be further improved. 1A to 1E are flowcharts showing the manufacture of a thin film transistor used in, for example, a liquid crystal display device. First, as shown in Fig. 1A, a gate 12 is formed on a glass carrier 11. Of course, the formation of the gate 12 includes a thin film deposition process, a yellow photolithography process, and a patterning process, wherein the yellow light lithography process may include photoresist, exposure, development, and photoresist removal process. The steps are not repeated here. Then, as shown in FIG. 1B, an insulating layer 13 and a channel layer 14 are sequentially formed on the gate 12 and the glass carrier 11; wherein the channel layer 14 comprises an amorphous Si (a-Si) : H) layer 141 and a doped layer (n+ a-Si) 142. Further, as shown in Fig. 1C, a drain 15 and a source 16 are formed at the ends of the layer 14 at 201113952. In Fig. 1D, the pattern of the doping layer 142 is performed with the pattern of the drain 15 and the source 16 as a mask, so that the channel layer 14 has a recess 143. Then, as shown in Fig. 1E, a passivation layer 17 is formed to cover the drain 15, the source and the channel layer 14, and a contact hole is formed by a yellow photolithography process and an etching process. Next, as shown in Fig. ip., a patterned pixel electrode layer PE is deposited on the passivation layer 17, and the pixel electrode layer pE is in contact with the drain electrode 15 via the contact hole. In the above process, the formation of the drain 15 and the source 16 also includes a yellow-light process, so that the gate 15 and the source μ are patterned. However, due to the exposure machine used in the yellow lithography process, the resolution is limited, so that the distance D1 between the drain 15 and the source 16 also has a certain length, resulting in the channel length of the channel layer (which can be regarded as the spacing Dl). ) is limited and can no longer be shortened, thus limiting component performance. Therefore, how to provide a display device, a display panel, an active device, a substrate, and a method of manufacturing the same, which can shorten the channel and improve the performance of the device, is only an important issue. [Invention] In view of the above problems, the object of the present invention is Provided is a display device, a display panel, an active device substrate, and a method of manufacturing the same capable of shortening a channel and thereby improving component performance. In order to achieve the above object, a method for manufacturing an active device substrate according to the present invention comprises the steps of: forming a channel layer on a carrier; forming a 201113952 drain and a source at both ends of the channel layer; forming a The cover layer covers the channel layer and covers at least a portion of the drain and the source, and the cover layer has a recess corresponding to the channel layer; the cover layer is partially removed, the channel layer is partially exposed corresponding to the recess; and the channel layer is partially removed to make the channel layer There is a groove between the drain and the source. To achieve the above object, an active device substrate according to the present invention comprises a carrier, a channel layer, a cathode, a source, and a cover layer. The channel layer is placed on the carrier. The drain and the source are disposed at both ends of the channel layer, and the channel layer has a groove between the drain and the source. The cover layer is disposed on the channel layer and is located between the outer periphery of the groove and the drain and the source. To achieve the above object, a display panel according to the present invention comprises a substrate and an active device substrate. The active device substrate is disposed opposite to the substrate and includes a carrier, a channel layer, a cathode, a source, and a cover layer. The channel layer is disposed on the carrier. The drain and the source are disposed at both ends of the channel layer, and the channel layer has a groove between the drain and the source. The cover layer is disposed on the channel layer and is located between the outer periphery of the groove and the drain and the source. To achieve the above objective, a display device according to the present invention includes a display panel and a backlight module, and the backlight module is adjacent to the display panel. The display panel includes a substrate and an active component substrate. The active device substrate is opposite to the substrate and includes a carrier, a channel layer, a drain, a source and a cover layer. The channel layer is disposed above the carrier. The drain and the source are disposed at both ends of the channel layer, and the channel layer has a groove between the drain and the source. The cover layer is disposed on the channel layer and is located at the outer periphery of the groove and the drain and the source of the 201113952. The display device of the present invention, the display panel, the active device substrate and the manufacturing method thereof are formed in the bungee After the source and the source, the cover layer of the channel layer is not directly formed, but a cover layer is formed to cover the channel layer, and at least a part of the drain and the source, and the cover layer has a recess corresponding to the channel layer. The cover layer is then partially removed (e.g., etched) such that the channel layers are partially exposed and partially exposed. At this time, the length of the exposed portion of the channel layer must be smaller than the distance between the drain and the source, and then the channel layer is partially removed, that is, the exposed portion of the channel layer is removed, so that the channel layer has a concave between the drain and the source. Slot 'This groove can be seen as a channel for an active component. Thus, the present invention can break the limit of the resolution of the conventional exposure machine, shorten the length of the channel, thereby promoting the electric field distribution and improving the performance of the component. In addition, the 'cover layer can also protect the portion of the channel layer that is not to be removed from ions during the removal process', thereby avoiding leakage current. [Embodiment] Hereinafter, a display device, a display panel, an active device substrate, and a method of manufacturing the same according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein the same elements will be described with the same reference numerals. A flow of a method of manufacturing the active device substrate 20 of the preferred embodiment of the present invention is shown in Figs. 2A to 2G. In this embodiment, the active device is exemplified by a Thin Film Transistor (TFT). First, as shown in FIG. 2A, a gate 22 is formed on a carrier 21. The material of the carrier 21 may be selected from the group consisting of glass, plastic, sapphire, polymer, and combinations thereof. The carrier 21 is exemplified by a slab; > 201113952 The gate 22 is deposited by thin film. Micro-patterning and forming on the carrier 2], wherein the yellow two-second photoresist, the exposure, the development of the wire after the process, etc. (4), the product can be sputtered, the etching can be wet etching (Wd In addition, the material of the gate 22 may include a metal or an alloy such as chromium, aluminum, copper or molybdenum. As shown in FIG. 2B, an insulating layer 23 is formed on the gate 22, And forming a channel layer 24 on the insulating layer 23. The insulating layer 23 and the channel layer 24 are formed by chemical vapor deposition (CVD). The stomach material of the insulating layer 23 may comprise a nitrogen cerium compound (SiNx). A semiconductor layer 241 and a doped layer 242 are sequentially formed on the insulating layer 23. The material of the semiconductor 241 includes an amorphous germanium (a-Si:H). The doped layer 242 is doped with N^. For example, +a-Si), for example, germanium containing a high concentration of phosphorus, the doped layer 2仏 can reduce the interface potential difference and form an ohmic junction (〇hmicc〇mact) As shown in Fig. 2C, a drain 25 and a source 26 are formed at both ends of the channel layer 24. The drain 25 and the source 26 can be patterned by a yellow lithography process, in which a pattern is formed. The steps of the drain 25 and the source 26 include sputtering and wet etching. The material of the drain 25 and the source 26 may include a metal or an alloy such as chromium, aluminum, copper or molybdenum. As shown in FIG. 2D, a cover layer 28 is formed. The channel layer 24 is covered and covers at least a portion of the drain 25 and the source 26, as exemplified by full coverage. Further, the cover layer 28 has a recess 281 corresponding to the channel layer 24. The cover layer 28 can be chemically vaporized. Formed by spin coating, spin coating, or slit coating. In this embodiment, the cover layer 201111952 can be made of a material having better shape (c〇nformity). For example, tetraethyl orthosilicate (TEOS) enables the cover layer 28 to form a distinct recess 281 after formation. As shown in Fig. 2E, the cover layer 28 is partially removed so that the channel layer 24 corresponds to the recess 281 and partially Exposed. Here, removal of anisotropy, for example, by etching Anisotropic) etching, non-isotropic etching, for example, dry etching. After etching, a portion of the cap layer 28 is left between the drain 25 and the source 26, and on both sides of the recess 281, and The mask is passed through for 24 seconds. As shown in Fig. 2F, the channel layer 24 is partially removed such that the channel layer 24 has a recess 243 between the drain 25 and the source 26. In this embodiment, the etching mode is an anisotropic residue, such as dry silver etching, and the portion of the channel layer 24 is mainly an etch doped layer 242. After etching, a portion of the cap layer 28 is located between the outer periphery of the recess 243, the drain 25 and the source 26. In the present embodiment, the channel of the channel layer 24 can be regarded as the width 1 of the groove 243. 2 ' Since the partial cover layer 28 is located between the drain 25 and the source 26 and is a mask etched by the channel layer 24, The present invention can obtain a shorter channel than the prior art. In general, conventional channels can reach 5 microns (μιη) due to the resolution of the exposure machine, while this embodiment can be less than 5 microns, for example up to 2 microns. As shown in Fig. 2G, the present embodiment may further include a formation-purification layer 27 to cover the drain layer 24, the portion of the source electrode 26, and the portion of the drain electrode 25. The material of the passivation layer 27 contains a nitrogen ruthenium compound and can be formed by chemical vapor deposition and forms a contact hole (c〇ntact 201113952 hole) by a yellow lithography process and a (4) process. Next, as shown in Fig. 2H, a patterned halogen element layer is deposited on the passivation layer 27, and the halogen electrode layer is in contact with the drain electrode 25 via the contact hole. It is not inferior to slam the sputum substrate. • Yeah > Bu called defeat _ j Na Shows the invention of the preferred real orchid - species - 岐 6G. In the present embodiment, the display panel 60 is exemplified by a liquid crystal display panel, the substrate 40, the active device substrate 30, and a liquid crystal layer%. The substrate 4A is disposed opposite to the active device substrate 30, and the liquid crystal layer 5 is disposed between the substrate 4A and the active device substrate 30. The substrate 40 of the present embodiment can be regarded as a color light-emitting substrate, and includes a carrier 41, a light shielding layer 42, a light-passing layer 43, a purification layer 44, a common electrode layer 45, an alignment layer 46, and a polarizing light. Layer 47. The light-shielding pre-layer 43, the passivation layer 44, the common electrode layer 45, and the alignment layer 46 are provided on the green sheet of the carrier 41 and the polarizing layer 〇 is provided on the carrier = side. Due to the general technique of the above-mentioned component materials, it will not be described here. The other liquid crystal layer 50 contains liquid crystal molecules and a plurality of spacers. The active device substrate 3G includes a carrier 31, a gate %, a layer 33, a channel layer 34, a drain 35, a gate, a flange, a cover 38, a main source 36, and a passivation layer 37. , Fang. Since the above-mentioned components are detailed in the above embodiments, the process integration of the other components of the above-mentioned components is not paid. For example, the active substrate 30 is a reporter, When the gate is formed, the singer can return to the singer/single pen 39a; in the formation of the singularity, the singer will form another storage electrode 39b, and the two storage batteries, ... can simultaneously hold the t pole 39a and 39b is formed ~ 201113952 storage capacitor; after forming the drain 35 and the source 36, a halogen electrode layer 3a can be formed, and the pixel electrode layer 3a is in contact with the storage electrode 39b; after forming the halogen electrode layer 3a, The other alignment layer 3b is formed such that the liquid crystal molecules 51 are interposed between the two alignment layers 46, 3b. Further, the active device substrate 30 further has a polarizing layer 3c disposed on one side of the carrier 31 away from the liquid crystal layer 50. The active device substrate of the invention can also be applied to a display device. Fig. 4 shows a display device 7 according to a preferred embodiment of the present invention. In the embodiment, the display device 7 is exemplified by a liquid crystal display device, which includes a display panel 60 and a backlight module The backlight module 70 can be adjacent to the display panel 60. The backlight module 70 can be an edge-lit backlight module or a direct-lit backlight module. For example, the backlight module 70 can include a light guide plate 71, a light source 7.2, a reflector 73, a reflection sheet 74, and an optical film group 75. The light source 72 is adjacent to ^ is disposed on one side of the light guide plate 71, the reflection cover 73 is disposed on the periphery of the light source 72, and the reflection sheet 74 and the optical film group 75 are disposed on the opposite side of the light guide plate 71. Since the above members are all common technologies, they are not described herein. In summary, a display device, a display panel, an active device substrate, and a method for fabricating the same according to the present invention do not directly perform the residual of the channel layer after forming the drain and the source, but first form a cover layer covering channel. a layer, and at least a portion of the drain and the source, and the cover layer has a recess corresponding to the channel layer. The cover layer is then partially removed (eg, engraved) such that the channel layer is partially exposed corresponding to the recess. At this time, the exposed portion of the channel layer Long Must be Γ 11 201113952 is less than the distance between the drain and the source, and then partially remove the channel layer, that is, remove the exposed portion of the channel layer, so that the channel layer has a groove between the drain and the source, the groove can be regarded as a The channel of the active component. Thus, the present invention can break the limit of the resolution of the conventional exposure machine, shorten the length of the channel, thereby promoting the electric field distribution and improving the performance of the component. Moreover, in the removal process, the cover layer can also protect the channel layer without the need for The removed portion is protected from ions and thus avoids leakage currents. The above description is by way of example only and not as a limitation of the invention. , should be included in the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1F are flowcharts showing a manufacturing process of a conventional thin film transistor; FIG. 2A to FIG. 2H are flowcharts showing a manufacturing process of an active device substrate according to a preferred embodiment of the present invention; A schematic view of a display panel of a preferred embodiment; and FIG. 4 is a schematic diagram of a display device in accordance with a preferred embodiment of the present invention. [Main component symbol description] 11: Glass carrier 12, 22, 32: Gate 13, 23, 33: Insulation layer 14' 24, 34: Channel layer 12 201113952 141: Amorphous germanium layer 142, 242: Erbium doped layer 143, 243: grooves 15, 25, 35: drains 16, 26, 36: sources 17, 27, 37, 44: pure 4 layers 20, 30: active device substrates 21, 31, 41: carrier board # 241: semiconductor layer 28, 38: cover layer 281: recessed portions 39a, 39b: storage electrode 3a, PE: halogen electrode layer 40: substrate 42: light shielding layer • 43: filter layer 45: common electrode layer 46, 3b: alignment Layers 47, 3c: polarizing layer 50: liquid crystal layer 51: liquid crystal molecules 60: display panel 7: display device 70: backlight module 201113952 71: light guide plate 72: light source 73: reflector 74: reflective sheet 75: optical film group D1 : Spacing D2 : Width Η : Contact hole