TWI500371B - Mark for inspection and printed circuit board having the same - Google Patents
Mark for inspection and printed circuit board having the same Download PDFInfo
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- TWI500371B TWI500371B TW101109545A TW101109545A TWI500371B TW I500371 B TWI500371 B TW I500371B TW 101109545 A TW101109545 A TW 101109545A TW 101109545 A TW101109545 A TW 101109545A TW I500371 B TWI500371 B TW I500371B
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- pattern
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- opening
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- length
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- 238000007689 inspection Methods 0.000 title claims description 35
- 229910000679 solder Inorganic materials 0.000 claims description 32
- 239000002335 surface treatment layer Substances 0.000 claims description 23
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 17
- 239000010410 layer Substances 0.000 claims description 14
- 239000010931 gold Substances 0.000 claims description 12
- 238000005259 measurement Methods 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 238000000034 method Methods 0.000 description 16
- 239000010949 copper Substances 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 230000007547 defect Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/162—Testing a finished product, e.g. heat cycle testing of solder joints
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
本發明係關於一種檢查記號以及一種具有該種檢查記號的印刷電路板。The present invention relates to an inspection mark and a printed circuit board having such an inspection mark.
近來,在印刷電路板(Printed Circuit Board,PCB)產業中,對用於覆晶晶片(Flip Chip,FC)之基板的重視程度逐漸增加。Recently, in the printed circuit board (PCB) industry, the importance of substrates for flip chip (FC) has gradually increased.
其中一種製造用於倒裝晶片之基板的常見製程為凸塊製程(bumping process)。One common process for fabricating substrates for flip chip is a bumping process.
凸塊製程為一種形成可在印刷電路板上電性連接半導體晶片的凸塊的製程,隨著半導體晶片的高度整合,需要形成具有細間距(fine pitch)的凸塊。The bump process is a process for forming bumps that can be electrically connected to a semiconductor wafer on a printed circuit board. As the semiconductor wafer is highly integrated, it is necessary to form bumps having fine pitch.
為形成細間距凸塊,重要的一點為確保關於精細度(fineness)的製程能力(process capacity),如關於凸塊尺寸、接墊(pad)間距或防焊劑偏心度(eccentricity)等等的製程能力。然而,在減少凸塊尺寸與接墊間距精細度一事上有其限制存在。因此需要一種減少用以支撐凸塊之接墊的尺寸的製程。In order to form fine pitch bumps, an important point is to ensure process capacity with respect to fineness, such as processes regarding bump size, pad pitch or solder eccentricity, and the like. ability. However, there is a limitation in reducing the bump size and the pitch fineness of the pads. There is therefore a need for a process that reduces the size of the pads used to support the bumps.
然而上述製程可能因基板歪曲(substrate distortion)、尺度異常(scale abnormality)等等,使得為了形成凸塊而形成在防焊劑的防焊劑開口(SRO)偏離超出接墊邊界,導致如開路(electrical open)缺陷或凸塊缺陷等問題的發生。為避免上述缺陷,則必須管理接墊邊界到介面表面(interface surface)之間的距離,即防焊劑開口的偏心位置(eccentric position)。However, the above process may be caused by substrate distortion, scale abnormality, etc., so that the solder resist opening (SRO) formed in the solder resist deviates beyond the pad boundary in order to form a bump, resulting in an open circuit (electrical open). Problems such as defects or bump defects. In order to avoid the above defects, it is necessary to manage the pad boundary to the interface surface (interface The distance between the surfaces, ie the eccentric position of the solder resist opening.
同時,韓國專利公開號2006-0026191一案中,揭露一種根據先前技術來檢測防焊劑開口是否有偏心情形的方法。Meanwhile, in the case of Korean Patent Publication No. 2006-0026191, a method of detecting whether or not the solder resist opening is eccentric according to the prior art is disclosed.
然而,前述根據先前技術檢測防焊劑開口是否有偏心情形的方法,可能因接墊表面與防焊劑表面於z軸方向上的高度不同,導致工作者在根據防焊劑開口(SRO)之形狀及焦點進行量測時,在不同工作者之間有測量誤差的存在,並可能會難以系統性地監測偏心方向。However, the foregoing method for detecting whether the solder resist opening is eccentric according to the prior art may be caused by the difference in the height of the pad surface and the solder resist surface in the z-axis direction, resulting in the worker's shape and focus according to the solder resist opening (SRO). When measuring, there is a measurement error between different workers, and it may be difficult to systematically monitor the eccentric direction.
本發明係用以提供一種檢查記號以及一種具有該種檢查記號的印刷電路板,能夠以精確的數值檢測出一防焊劑開口的偏心量與偏心方向。SUMMARY OF THE INVENTION The present invention is directed to providing an inspection mark and a printed circuit board having such an inspection mark capable of detecting an eccentric amount and an eccentric direction of a solder resist opening with accurate values.
另外,本發明用以提供一種檢查記號以及一種具有該種檢查記號的印刷電路板,能夠使檢查成本降至最低並降低製程能力(process capacity)。In addition, the present invention is used to provide an inspection mark and a printed circuit board having such an inspection mark, which can minimize inspection costs and reduce process capacity.
根據本發明一較佳實施例,提供一種檢查記號,包括多個電壓施加終端、一第一圖案、多個第二圖案、多個電壓測量終端、一防焊劑層以及一表面處理層。電壓施加終端係包括一對第一電壓施加終端以及一對第二電壓施加終端,第一電壓施加終端彼此分離並於一第一方向彼此相對,第二電壓施加終端彼此分離並於垂直第一方向之一第二方向彼此相對。第一圖案係包括一第1-1圖案及一第1-2 圖案,連接該對第一電壓施加終端及該對第二電壓施加終端。第二圖案為延伸形態,具有連接至第1-1圖案及第1-2圖案之兩側之一表面或另一表面的末端。電壓測量終端係連接至第二圖案的另一末端。防焊劑層具有第一開口及第二開口,第一開口暴露出電壓施加終端及電壓測量終端,第二開口暴露出第一圖案。表面處理層係形成在藉由第一開口及第二開口而暴露出之電壓施加終端、電壓測量終端及第一圖案上,其中第一圖案之第1-1圖案與第1-2圖案係互相交叉,第二開口暴露出第一圖案之一交叉部分。According to a preferred embodiment of the present invention, an inspection mark is provided, including a plurality of voltage application terminals, a first pattern, a plurality of second patterns, a plurality of voltage measuring terminals, a solder resist layer, and a surface treatment layer. The voltage application terminal includes a pair of first voltage application terminals and a pair of second voltage application terminals, the first voltage application terminals are separated from each other and opposed to each other in a first direction, and the second voltage application terminals are separated from each other and in a vertical first direction One of the second directions is opposite to each other. The first pattern includes a 1-1st pattern and a 1-2th pattern a pattern connecting the pair of first voltage application terminals and the pair of second voltage application terminals. The second pattern is an extended form having ends connected to one of the sides of the 1-1st pattern and the 1-2th pattern or the other surface. The voltage measuring terminal is connected to the other end of the second pattern. The solder resist layer has a first opening and a second opening, the first opening exposing the voltage application terminal and the voltage measuring terminal, and the second opening exposing the first pattern. The surface treatment layer is formed on the voltage application terminal, the voltage measurement terminal, and the first pattern exposed by the first opening and the second opening, wherein the 1-1st pattern and the 1-2th pattern of the first pattern are mutually Crossing, the second opening exposes an intersection of one of the first patterns.
第二圖案之連接至第1-1圖案與第1-2圖案的末端可鄰接於電壓施加終端。The end of the second pattern connected to the 1-1st pattern and the 1-2th pattern may be adjacent to the voltage application terminal.
表面處理層可由鎳(Ni)及金(Au)製成。The surface treatment layer may be made of nickel (Ni) and gold (Au).
第1-1圖案與第1-2圖案可具有相同的長度。The 1-1st pattern and the 1-2th pattern may have the same length.
第二開口之橫向長度與縱向長度彼此可不相等。The lateral length and the longitudinal length of the second opening may not be equal to each other.
第二開口之橫向長度與縱向長度的相加值可等於第1-1圖案的長度或第1-2圖案的長度。The added value of the lateral length and the longitudinal length of the second opening may be equal to the length of the 1-1st pattern or the length of the 1-2th pattern.
第一電壓施加終端對之其中一者可標號為1,其他各個電壓施加終端可以編號1者為基準而逆時鐘地標號成2、3及4,第1-1圖案的長度及第1-2圖案的長度可各為a+b,第二開口之平行於第1-1圖案的部分的長度可為a,第二開口之垂直於第1-1圖案的部分的長度可為b,且當電壓施加終端1及2之間的電阻值為R12
、電壓施加終端2及3之間的電阻值為R23
、電壓施加終端3及4之間的電阻值為R34
、電壓施加終端4及1之間的電阻值為R41
、電壓施加終端1及3之間的電阻值為R13
且電壓施加終端2
及4之間的電阻值為R24
時,一偏心量x與一偏心量y可分別由以下等式表示:
根據本發明另一較佳實施例,提供一種印刷電路板,包括一基板單位區及一環繞基板單位區的空白區。該印刷電路板包括一檢查記號,檢查記號包括多個電壓施加終端、一第一圖案、多個第二圖案、多個電壓測量終端、一防焊劑層以及一表面處理層。電壓施加終端係包括一對第一電壓施加終端以及一對第二電壓施加終端,第一電壓施加終端彼此分離並於一第一方向彼此相對,第二電壓施加終端彼此分離並於垂直第一方向之一第二方向彼此相對。第一圖案係包括一第1-1圖案及一第1-2圖案,連接該對第一電壓施加終端及該對第二電壓施加終端。第二圖案為延伸形態,具有連接至第1-1圖案及第1-2圖案兩側之一表面或另一表面的末端。電壓測量終端係連接至第二圖案的另一末端。防焊劑層具有第一開口及第二開口,第一開口暴露出電壓施加終端及電壓測量終端,第二開口暴 露出第一圖案。表面處理層係形成在藉由第一開口及第二開口而暴露出之電壓施加終端、電壓測量終端及第一圖案上,其中第一圖案之第1-1圖案與第1-2圖案係互相交叉,第二開口暴露出第一圖案之一交叉部分。According to another preferred embodiment of the present invention, a printed circuit board is provided comprising a substrate unit area and a blank area surrounding the substrate unit area. The printed circuit board includes an inspection mark including a plurality of voltage application terminals, a first pattern, a plurality of second patterns, a plurality of voltage measuring terminals, a solder resist layer, and a surface treatment layer. The voltage application terminal includes a pair of first voltage application terminals and a pair of second voltage application terminals, the first voltage application terminals are separated from each other and opposed to each other in a first direction, and the second voltage application terminals are separated from each other and in a vertical first direction One of the second directions is opposite to each other. The first pattern includes a 1-1st pattern and a 1-2th pattern, and connects the pair of first voltage application terminals and the pair of second voltage application terminals. The second pattern is an extended form having ends connected to one of the sides of the 1-1st pattern and the 1-2th pattern or the other surface. The voltage measuring terminal is connected to the other end of the second pattern. The solder resist layer has a first opening and a second opening, the first opening exposing the voltage application terminal and the voltage measuring terminal, and the second opening storm The first pattern is exposed. The surface treatment layer is formed on the voltage application terminal, the voltage measurement terminal, and the first pattern exposed by the first opening and the second opening, wherein the 1-1st pattern and the 1-2th pattern of the first pattern are mutually Crossing, the second opening exposes an intersection of one of the first patterns.
第二圖案之連接至第1-1圖案與第1-2圖案的末端可鄰接於電壓施加終端。The end of the second pattern connected to the 1-1st pattern and the 1-2th pattern may be adjacent to the voltage application terminal.
表面處理層可由鎳(Ni)及金(Au)製成。The surface treatment layer may be made of nickel (Ni) and gold (Au).
第1-1圖案與第1-2圖案可具有相同的長度。The 1-1st pattern and the 1-2th pattern may have the same length.
第二開口之橫向長度與縱向長度彼此可不相等。The lateral length and the longitudinal length of the second opening may not be equal to each other.
第二開口之橫向長度與縱向長度的相加值可等於第1-1圖案的長度或第1-2圖案的長度。The added value of the lateral length and the longitudinal length of the second opening may be equal to the length of the 1-1st pattern or the length of the 1-2th pattern.
第一電壓施加終端對之其中一者可標號為1,其他各個電壓施加終端可以編號1者為基準而逆時鐘地標號成2、3及4,第1-1圖案的長度及第1-2圖案的長度可各為a+b,第二開口之平行於第1-1圖案的部分的長度可為a,第二開口之垂直於第1-1圖案的部分的長度可為b,且當電壓施加終端1及2之間的電阻值為R12
、電壓施加終端2及3之間的電阻值為R23
、電壓施加終端3及4之間的電阻值為R34
、電壓施加終端4及1之間的電阻值為R41
、電壓施加終端1及3之間的電阻值為R13
且電壓施加終端2及4之間的電阻值為R24
時,一偏心量x與一偏心量y可分別由以下等式表示:
空白區可包括一長條空白區,該長條空白區位於包括多個基板單位的複數個長條中,或者空白區可包括一平板空白區,平板空白區位於一平板中,多個長條排列於該平板內。The blank area may include a long blank area located in a plurality of strips including a plurality of substrate units, or the blank area may include a flat blank area, the flat blank area is located in a flat plate, and the plurality of strips Arranged in the plate.
本發明之不同優點與特徵,係藉由以下實施例說明與所附圖式來進行揭露。The advantages and features of the present invention are disclosed by the following embodiments and the accompanying drawings.
本發明說明書以及申請專利範圍中所用的字詞,不應以限定於其通常意義或字典中之定義的方式進行解釋,而應基於發明者可適當定義術語之概念來以最佳方式描述其發明的法則,解釋為具有關於本發明技術領域之意義及概念。Words used in the description of the present invention and in the scope of the claims should not be construed as being limited to their ordinary meaning or definition in the dictionary, but should be described in an optimal manner based on the concept that the inventor can appropriately define the term. The law is interpreted as having meaning and concepts related to the technical field of the present invention.
藉由配合所附圖式而進行的詳細說明,本發明所屬領域中具有通常知識者能夠清楚明白如上所述或其他本發明不同之目的、優點與特徵。在發明說明書與圖式中,即使是繪示於不同圖中,相似的元件符號係用以指示相似的元件。在對於本發明之描述中,若對於本發明相關之習知 技術進行詳述會導致閱讀重點失焦,則詳細的敘述說明便會自說明書省略。在發明說明書中,第一、第二等用語僅為分辨不同元件之用,而非用以限定各元件。The above objects or other objects, advantages and features of the present invention will become apparent to those skilled in the <RTIgt; In the description and drawings, like reference numerals are used to refer to the In the description of the present invention, if it is relevant to the present invention Detailed description of the technique will result in the focus of the reading being out of focus, and the detailed description will be omitted from the manual. In the description of the invention, the terms first, second, etc. are used to distinguish different elements, and are not intended to limit each element.
以下將配合所附圖式,對於本發明之較佳實施例進行詳細說明。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail in conjunction with the drawings.
第1圖係繪示根據本發明一較佳實施例之檢查記號(mark for inspection)的俯視圖,而第2圖係繪示根據本發明較佳實施例之檢查記號中,設置在防焊劑(solder resist)之底部上的圖案的俯視圖。1 is a plan view showing a mark for inspection according to a preferred embodiment of the present invention, and FIG. 2 is a view showing a solder resist (solder) in an inspection mark according to a preferred embodiment of the present invention. Top view of the pattern on the bottom of the resist).
請參照第1圖及第2圖,根據本發明一較佳實施例之一檢查記號100,係包括電壓施加終端(voltage applying terminal)1、2、3、4,第一圖案101,第二圖案111a、111b、111c及111d,電壓測量終端(voltage measuring terminal)1'、2'、3'、4',防焊劑層150,以及表面處理層(surface treatment layer)160。Referring to FIG. 1 and FIG. 2, an inspection mark 100 according to a preferred embodiment of the present invention includes a voltage applying terminal 1, 2, 3, 4, a first pattern 101, and a second pattern. 111a, 111b, 111c, and 111d, voltage measuring terminals 1', 2', 3', 4', solder resist layer 150, and surface treatment layer 160.
如第1圖及第2圖所示,電壓施加終端1、2、3、4可包括一對彼此分離並於一第一方向彼此相對的第一電壓施加終端1及3,以及一對彼此分離並於一第二方向彼此相對第二電壓施加終端2及4,第二方向係垂直於第一方向。As shown in FIGS. 1 and 2, the voltage application terminals 1, 2, 3, 4 may include a pair of first voltage application terminals 1 and 3 which are separated from each other and opposed to each other in a first direction, and a pair are separated from each other. And in a second direction, the second voltage application terminals 2 and 4 are opposite to each other, and the second direction is perpendicular to the first direction.
在本例中,第一方向可代表第1圖及第2圖之垂直方向,而第二方向可代表第1圖及第2圖之水平方向,但本發明之較佳實施例並不受限於此。第一方向可為水平方向,而二方向可為垂直方向。In this example, the first direction may represent the vertical direction of the first and second figures, and the second direction may represent the horizontal direction of the first and second figures, but the preferred embodiment of the present invention is not limited herein. The first direction may be a horizontal direction, and the two directions may be a vertical direction.
在本例中,電壓施加終端1、2、3及4可由銅(Cu)製 成,但不特別限定於此。In this example, the voltage application terminals 1, 2, 3, and 4 can be made of copper (Cu). However, it is not particularly limited to this.
第一圖案101可包括第1-1圖案101a及第1-2圖案101b,第1-1圖案101a及第1-2圖案101b係分別連接第一電壓施加終端對1、3以及第二電壓施加終端2、4。The first pattern 101 may include a 1-1st pattern 101a and a 1-2st pattern 101b, and the 1-1st pattern 101a and the 1-2th pattern 101b are respectively connected to the first voltage application terminal pair 1, 3 and the second voltage application. Terminals 2, 4.
在本例中,類似於電壓施加終端1、2、3及4,第一圖案101可由銅(Cu)製成,但不限於此。In this example, similar to the voltage application terminals 1, 2, 3, and 4, the first pattern 101 may be made of copper (Cu), but is not limited thereto.
在本例中,第1-1圖案101a與第1-2圖案101b可具有相同的長度,但不限於此。In this example, the 1-1st pattern 101a and the 1-2st pattern 101b may have the same length, but are not limited thereto.
第二圖案111a、111b、111c及111d,係為以連接至第1-1圖案101a與第1-2圖案101b兩側之一表面或另一表面的方式延伸形成的圖案。The second patterns 111a, 111b, 111c, and 111d are patterns extending to be connected to one surface or the other surface of both sides of the 1-1st pattern 101a and the 1-2th pattern 101b.
例如請參照第2圖,第二圖案111a及111c可形成在鄰接位於第1-1圖案101a兩側之第一電壓施加終端1及3的部分,亦即,第二圖案111b及111d係可形成在鄰接位於連接第二電壓施加終端2、4之第1-2圖案101b兩側之第二電壓施加終端2及4的部分。For example, referring to FIG. 2, the second patterns 111a and 111c may be formed adjacent to the portions of the first voltage application terminals 1 and 3 located on both sides of the 1-1st pattern 101a, that is, the second patterns 111b and 111d may be formed. The portions of the second voltage application terminals 2 and 4 located on both sides of the 1-2th pattern 101b connecting the second voltage application terminals 2, 4 are adjacent.
在本例中,如第2圖所示,各個第二圖案111a、111b、111c、111d可以朝同一方向延伸的方式形成,但不特別限定於此。然而,第二圖案111a、111b、111c及111d可以不會造成彼此間短路的方式形成。In this example, as shown in FIG. 2, each of the second patterns 111a, 111b, 111c, and 111d may be formed to extend in the same direction, but is not particularly limited thereto. However, the second patterns 111a, 111b, 111c, and 111d may be formed in such a manner as not to cause a short circuit between each other.
此外,第二圖案111a、111b、111c及111d也可由銅(Cu)製成,但不限於此。Further, the second patterns 111a, 111b, 111c, and 111d may also be made of copper (Cu), but are not limited thereto.
再者,第二圖案111a、111b、111c及111d可具有相同的長度,但不特別限定於此。Furthermore, the second patterns 111a, 111b, 111c, and 111d may have the same length, but are not particularly limited thereto.
電壓測量終端1'、2'、3'及4'為各自連接至第二圖案 111a、111b、111c及111d的終端,也可由銅(Cu)製成,但不限於此。Voltage measuring terminals 1', 2', 3' and 4' are each connected to a second pattern The terminals of 111a, 111b, 111c, and 111d may also be made of copper (Cu), but are not limited thereto.
如第1圖及第2圖所示,第二圖案111a、111b、111c、111d的一末端與第一圖案101相連接,而另一末端可與前述之電壓測量終端1'、2'、3'、4'相連接。As shown in FIGS. 1 and 2, one end of the second patterns 111a, 111b, 111c, 111d is connected to the first pattern 101, and the other end is connectable to the aforementioned voltage measuring terminals 1', 2', 3 ', 4' are connected.
此外,檢查記號100可包括一防焊劑層150,防焊劑層150包括暴露出前述電壓施加終端1、2、3、4及前述電壓測量終端1'、2'、3'、4'的第一開口150a,以及暴露出第一圖案101中第1-1圖案101a與第1-2圖案101b互相交叉之部分的第二開口150b。In addition, the inspection mark 100 may include a solder resist layer 150 including a first electrode exposing the aforementioned voltage application terminals 1, 2, 3, 4 and the aforementioned voltage measuring terminals 1', 2', 3', 4' The opening 150a and the second opening 150b exposing a portion of the first pattern 101 where the 1-1st pattern 101a and the 1-2st pattern 101b cross each other.
在此,第二開口150b之橫向長度(horizontal length)與縱向長度(vertical length)可彼此不相等。Here, the lateral length and the vertical length of the second opening 150b may not be equal to each other.
另外,第二開口150b之橫向長度與縱向長度的相加值(sum)可等於第1-1圖案101a的長度或第1-2圖案101b的長度。In addition, the added value (sum) of the lateral length and the longitudinal length of the second opening 150b may be equal to the length of the 1-1st pattern 101a or the length of the 1-2th pattern 101b.
舉例而言,如第2圖所示,當第1-1圖案101a或第1-2圖案101b的長度為a+b,第二開口150b的橫向長度可被設定成等於a、縱向長度可被設定成等於b。在此例中,第二開口150b的橫向長度也可被設定成等於b,而縱向長度也可被設定成等於a。For example, as shown in FIG. 2, when the length of the 1-1st pattern 101a or the 1-2st pattern 101b is a+b, the lateral length of the second opening 150b can be set equal to a, and the longitudinal length can be Set to equal b. In this case, the lateral length of the second opening 150b can also be set equal to b, and the longitudinal length can also be set equal to a.
亦即,根據本發明較佳實施例之檢查記號100,係以使得第1-1圖案101a與第1-2圖案101b的長度彼此相等,且暴露於外第1-1圖案101a、第1-2圖案101b交叉部分之第二開口150b,其橫向與縱向長度的相加值等於第1-1圖案101a之長度或第1-2圖案101b之長度的方式來形成。That is, the inspection mark 100 according to the preferred embodiment of the present invention is such that the lengths of the 1-1st pattern 101a and the 1-2th pattern 101b are equal to each other, and are exposed to the outer 1-1st pattern 101a, first The second opening 150b of the intersection portion of the pattern 101b is formed in such a manner that the added value of the lateral direction and the longitudinal length is equal to the length of the 1-1st pattern 101a or the length of the 1-2st pattern 101b.
即使任何部分暴露於外,所暴露於外之第1-1圖案101a及第1-2圖案101b的長度係保持定值。藉由維持被暴露於外之圖案的長度為定值,可簡化對於偏心值(eccentric value)的計算操作。Even if any portion is exposed, the lengths of the 1-1st pattern 101a and the 1-2th pattern 101b exposed are kept constant. The calculation operation for the eccentric value can be simplified by maintaining the length of the pattern exposed to the outside as a constant value.
對於偏心值的計算操作將於以下的部分進行討論。The calculation of the eccentricity value will be discussed in the following sections.
此外,檢查記號100更可包括表面處理層160,表面處理層160係形成在由第一開口150a及第二開口150b暴露於外之電壓施加終端1、2、3、4、電壓測量終端1'、2'、3'、4'、第1-1圖案101a以及第1-2圖案101b之上。In addition, the inspection mark 100 may further include a surface treatment layer 160 formed on the voltage application terminals 1, 2, 3, 4 exposed by the first opening 150a and the second opening 150b, and the voltage measurement terminal 1' , 2', 3', 4', the 1-1st pattern 101a, and the 1-2th pattern 101b.
在本例中,表面處理層160可依序由鎳(Ni)及金(Au)製成,但不特別限定於此。In this example, the surface treatment layer 160 may be made of nickel (Ni) and gold (Au) in order, but is not particularly limited thereto.
在此,於電壓施加終端1、2、3、4與電壓測量終端1'、2'、3'、4'上形成表面處理層160,係為了避免前述終端因暴露於空氣之中而被氧化。Here, the surface treatment layer 160 is formed on the voltage application terminals 1, 2, 3, 4 and the voltage measurement terminals 1', 2', 3', 4' in order to prevent the terminal from being oxidized by exposure to air. .
同時,在暴露於外之第1-1圖案101a與第1-2圖案101b上形成表面處理層160,係為了避免被暴露於外的圖案被氧化,並且使得暴露於外的圖案與未暴露的圖案之間的電阻值(resistance value)不同。Meanwhile, the surface treatment layer 160 is formed on the 1-1st pattern 101a and the 1-2th pattern 101b which are exposed to the outside, in order to prevent the exposed pattern from being oxidized, and to expose the exposed pattern to the unexposed one. The resistance values between the patterns are different.
亦即,未暴露於外的第1-1圖案101a與第1-2圖案101b係由銅(Cu)製成,暴露於外的第1-1圖案101a與第1-2圖案101b係由銅(Cu)/鎳(Ni)及金(Au)製成,以使得暴露部分與未暴露部分的電阻值不同。That is, the 1-1st pattern 101a and the 1-2st pattern 101b which are not exposed are made of copper (Cu), and the 1-1st pattern 101a and the 1-2st pattern 101b which are exposed are made of copper. (Cu)/nickel (Ni) and gold (Au) are formed so that the resistance values of the exposed portion and the unexposed portion are different.
如上所述,係藉由使暴露部分與未暴露部分的電阻值不同來測量電阻值,並可藉由使用測量而得的電阻值,計算第1-1圖案101a與第1-2圖案101b之交叉點相對於第 二開口150b中心的偏心量以及偏心方向(eccentric direction)。As described above, the resistance value is measured by making the resistance values of the exposed portion and the unexposed portion different, and the 1-1st pattern 101a and the 1-2th pattern 101b can be calculated by using the measured resistance value. Intersection relative to the first The amount of eccentricity at the center of the two openings 150b and the eccentric direction.
這將例如配合第3圖來進行描述。This will be described, for example, in conjunction with Figure 3.
請參照第3圖,當彼此交叉之第1-1圖案101a與第1-2圖案101b的中心點以Q表示,以中心點Q為原點,第1-1圖案101a的縱向長度可等於N,第1-2圖案101b的橫向長度也可等於N。Referring to FIG. 3, when the center points of the 1-1st pattern 101a and the 1-2st pattern 101b crossing each other are represented by Q, with the center point Q as the origin, the longitudinal length of the 1-1st pattern 101a may be equal to N. The lateral length of the 1-2th pattern 101b may also be equal to N.
在本例中,第1-1圖案101a之縱向長度與第1-2圖案101b之橫向長度亦彼此相等,如此一來,第一圖案的縱向與橫向長度以中心點Q為原點而等於N。In this example, the longitudinal length of the 1-1st pattern 101a and the lateral length of the 1-2st pattern 101b are also equal to each other, such that the longitudinal and lateral lengths of the first pattern are centered at the center point Q and equal to N. .
在這樣的情形下,亦即在防焊劑層150與表面處理層160形成前的情形下(請參照第2圖),測量個別終端間的電阻值皆可得到相同的結果。In such a case, that is, in the case where the solder resist layer 150 and the surface treatment layer 160 are formed (refer to FIG. 2), the same result can be obtained by measuring the resistance value between the individual terminals.
亦即,以中心點為原點,第一圖案全部的縱向、橫向長度皆相同,且所有組成成分(component)亦相同,因此測量得到相同的電阻值。That is, with the center point as the origin, all the longitudinal and lateral lengths of the first pattern are the same, and all the components are the same, so the same resistance value is measured.
在此,具有暴露出第一圖案101之一部分之第二開口150b的防焊劑層150係被形成,暴露出的該部分包括中心點Q,表面處理層160係形成於被暴露於外的第一圖案101上,接著,各個終端之間的電阻值係被測量。Here, a solder resist layer 150 having a second opening 150b exposing a portion of the first pattern 101 is formed, the exposed portion including the center point Q, and the surface treatment layer 160 is formed on the first exposed to the outside On the pattern 101, then, the resistance value between the respective terminals is measured.
在本例中,當第二開口150b的中心與中心點Q重合時,個別終端間之電阻值的測量結果可能相等,而當第二開口150b的中心與中心點Q未重合時,個別終端間之電阻值的測量結果可能不相等。In this example, when the center of the second opening 150b coincides with the center point Q, the measurement results of the resistance values between the individual terminals may be equal, and when the center of the second opening 150b does not coincide with the center point Q, the individual terminals are interposed. The measurement of the resistance value may not be equal.
在此,當第二開口150b的中心與中心點Q重合時, 電阻值測量結果相等的原因在於表面處理層160形成部分的縱向與橫向長度也相等。當第二開口150b的中心與中心點Q未重合時,電阻值測量結果不相等的原因係為位在第一圖案101之表面處理層160部分,其縱向與橫向長度彼此不相等。Here, when the center of the second opening 150b coincides with the center point Q, The reason why the resistance value measurement results are equal is that the longitudinal and lateral lengths of the portion in which the surface treatment layer 160 is formed are also equal. When the center of the second opening 150b and the center point Q are not coincident, the reason why the resistance value measurement results are not equal is the portion of the surface treatment layer 160 of the first pattern 101 whose longitudinal and lateral lengths are not equal to each other.
以下將配合第3圖,對於使用測量得到之電阻值來計算偏心量與偏心方向的方法進行描述。第3圖係繪示防焊劑之第二開口中心相對於第一圖案101之中心部分Q有偏心狀況的情形。亦即繪示在x方向有偏心量x、y方向有偏心量y的情形。The method of calculating the eccentric amount and the eccentric direction using the measured resistance value will be described below with reference to Fig. 3. 3 is a view showing a case where the center of the second opening of the solder resist is eccentric with respect to the central portion Q of the first pattern 101. That is, the case where there is an eccentric amount x in the x direction and an eccentric amount y in the y direction is shown.
首先,使用測量而得之電阻值,計算防焊劑第二開口150b之偏心量與偏心方向的公式,係如以下等式1所示。First, using the measured resistance value, the formula of the eccentric amount and the eccentric direction of the solder resist second opening 150b is calculated as shown in the following Equation 1.
在此,R12 係表示電壓施加終端1與2之間的電阻值,R23 係表示電壓施加終端2與3之間的電阻值,R34 係表示電壓施加終端3與4之間的電阻值,R41 係表示電壓施加終端4與1之間的電阻值,R13 係表示電壓施加終端1與3之間的電阻值,而R24 係表示電壓施加終端2與4之間的電阻值。Here, R 12 denotes a resistance value between the voltage application terminals 1 and 2, R 23 denotes a resistance value between the voltage application terminals 2 and 3, and R 34 denotes a resistance value between the voltage application terminals 3 and 4. R 41 denotes a resistance value between the voltage application terminals 4 and 1, R 13 denotes a resistance value between the voltage application terminals 1 and 3, and R 24 denotes a resistance value between the voltage application terminals 2 and 4.
另外,a代表基於第3圖之第二開口150b的橫向長度,b代表第二開口150b的縱向長度。在此例中,第1-1圖案101a及第1-2圖案101b的長度各為a+b。Further, a represents the lateral length of the second opening 150b based on Fig. 3, and b represents the longitudinal length of the second opening 150b. In this example, the lengths of the 1-1st pattern 101a and the 1-2st pattern 101b are each a+b.
並且,x代表第二開口150b之中心部分在x方向的偏心情形,y代表第二開口150b之中心部分在y方向的偏心情形。Also, x represents an eccentricity of the central portion of the second opening 150b in the x direction, and y represents an eccentricity of the central portion of the second opening 150b in the y direction.
亦即,如第3圖所示,根據本發明較佳實施例之檢查記號100可包括防焊劑層150以及表面處理層160,防焊劑層150具有一第二開口150b,第二開口150b形成在包括第1-1圖案101a及第1-2圖案101b的第一圖案101上,表面處理層160則形成在藉由第二開口150b而暴露於外的第一圖案101上,其中第二開口150b之橫向長度為a、縱向長度為b,且第一圖案101的長度為a+b。That is, as shown in FIG. 3, the inspection mark 100 according to the preferred embodiment of the present invention may include a solder resist layer 150 and a surface treatment layer 160 having a second opening 150b formed in the second opening 150b. On the first pattern 101 including the 1-1st pattern 101a and the 1-2st pattern 101b, the surface treatment layer 160 is formed on the first pattern 101 exposed by the second opening 150b, wherein the second opening 150b The lateral length is a, the longitudinal length is b, and the length of the first pattern 101 is a+b.
檢查記號100之個別終端間的電阻值係被測量,測量得到的電阻值以及預先決定的a值與b值被代入前述的等式1中,從而得到x與y。The resistance value between the individual terminals of the check mark 100 is measured, and the measured resistance value and the predetermined values of a and b are substituted into Equation 1 described above to obtain x and y.
所得到的x與y係代表基於第二開口150b之中心,在x方向的偏心量與在y方向的偏心量。The obtained x and y represent the amount of eccentricity in the x direction and the amount of eccentricity in the y direction based on the center of the second opening 150b.
如上所述,根據本發明較佳實施例之檢查記號100,係電性測量出電阻值,將測量值代入相關等式中,從而計算出精確的偏心量與偏心方向。As described above, according to the inspection mark 100 of the preferred embodiment of the present invention, the resistance value is electrically measured, and the measured value is substituted into the correlation equation to calculate an accurate eccentric amount and an eccentric direction.
此外,根據本發明較佳實施例之檢查記號100,係以一個別的製程形成,但可於在基板上形成圖案與防焊劑層的同時一起形成,因而不需要額外的製程步驟與成本。In addition, the inspection mark 100 according to the preferred embodiment of the present invention is formed by a separate process, but can be formed while forming a pattern on the substrate together with the solder resist layer, thereby eliminating the need for additional process steps and costs.
第4圖係繪示具有根據本發明一較佳實施例之檢查記 號的印刷電路板的俯視圖。Figure 4 is a diagram showing an inspection in accordance with a preferred embodiment of the present invention. Top view of the printed circuit board.
同時,檢查記號100的細節已於上文中描述,以下便省略相關敘述內容。Meanwhile, the details of the check mark 100 have been described above, and the related description will be omitted below.
如第4圖所示,根據本發明較佳實施例之檢查記號100可形成在一印刷電路板300的空白區(dummy region)220,印刷電路板300包括含有多個基板單位(unit substrate)10的基板單位區213以及環繞基板單位區213的空白區220,但不特別限定於此。As shown in FIG. 4, the inspection mark 100 according to the preferred embodiment of the present invention may be formed in a dummy region 220 of a printed circuit board 300, the printed circuit board 300 including a plurality of unit substrates 10 The substrate unit area 213 and the blank area 220 surrounding the substrate unit area 213 are not particularly limited thereto.
在此,空白區220可為一環繞基板單位區213的長條空白區(strip dummy region)211,位於包括多個基板單位10的長條(strip)210之中。Here, the blank area 220 may be a strip dummy region 211 surrounding the substrate unit area 213, located in a strip 210 including a plurality of substrate units 10.
另外,空白區220可為一環繞長條區215的平板空白區(panel dummy region)201,長條區215中排列有複數個長條210,平板空白區位於包括多個長條210的平板200之中。In addition, the blank area 220 may be a panel dummy region 201 surrounding the strip region 215. The strip region 215 is arranged with a plurality of strips 210 disposed on the flat panel 200 including the plurality of strips 210. Among them.
在此所述者僅為一較佳實施例,因此,檢查記號100形成的區域並不特別限定於此。The above description is only a preferred embodiment, and therefore, the area in which the inspection mark 100 is formed is not particularly limited thereto.
本發明之較佳實施例,係藉由對於由防焊劑開口暴露於外之圖案進行表面處理,接著測量各終端的電阻值,計算出偏心值,而可以精確的數值檢測出防焊劑開口的偏心量與偏心方向。In a preferred embodiment of the present invention, the eccentricity value is calculated by performing surface treatment on the pattern exposed by the solder resist opening, and then measuring the resistance value of each terminal, and the eccentricity of the solder resist opening can be accurately detected. Volume and eccentric direction.
並且,本發明之較佳實施例可如上所述以精確的數值檢測防焊劑開口的偏心量與偏心方向,從而精確地測量出各位置不規則的偏心度(eccentricity),例如尺度異常(scale abnormality)及歪曲(distortion)等等。Moreover, the preferred embodiment of the present invention can detect the eccentricity and eccentricity of the solder resist opening with accurate values as described above, thereby accurately measuring the irregular eccentricity of each position, such as scale abnormality. ) and distortion and so on.
本發明之較佳實施例更可以僅藉由測量各終端之電阻值便檢測出偏心度,不需使用額外的設備,如顯微鏡等等,因而降低了製程成本。The preferred embodiment of the present invention can detect the eccentricity only by measuring the resistance values of the terminals, without using additional equipment such as a microscope or the like, thereby reducing the process cost.
綜上所述,雖然本發明已以較佳實施例揭露如上,然其係用以具體地解釋本發明之實施情形,而非用以限定根據本發明之檢查記號及具有其之印刷電路板。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。In view of the above, the present invention has been described above in terms of preferred embodiments, which are intended to specifically explain the embodiments of the present invention, and are not intended to limit the inspection marks and printed circuit boards having the same according to the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention.
因此,本發明包括任何及所有不脫離本發明精神和範圍之各種更動與潤飾,而本發明之保護範圍當視後附之申請專利範圍所界定者為準。Accordingly, the present invention includes any and all modifications and variations of the present invention, and the scope of the present invention is defined by the scope of the appended claims.
1、2、3、4‧‧‧電壓施加終端1, 2, 3, 4‧‧‧ voltage application terminals
1'、2'、3'、4'‧‧‧電壓測量終端1', 2', 3', 4'‧‧‧ voltage measuring terminals
10‧‧‧基板單位10‧‧‧Substrate unit
100‧‧‧檢查記號100‧‧‧Check marks
101‧‧‧第一圖案101‧‧‧ first pattern
101a‧‧‧第1-1圖案101a‧‧‧1-1st pattern
101b‧‧‧第1-2圖案101b‧‧‧1-2th pattern
111a、111b、111c、111d‧‧‧第二圖案111a, 111b, 111c, 111d‧‧‧ second pattern
150‧‧‧防焊劑層150‧‧‧ solder resist layer
150a‧‧‧第一開口150a‧‧‧first opening
150b‧‧‧第二開口150b‧‧‧second opening
160‧‧‧表面處理層160‧‧‧Surface treatment layer
200‧‧‧平板200‧‧‧ tablet
201‧‧‧平板空白區201‧‧‧Table blank area
210‧‧‧長條210‧‧‧ strips
211‧‧‧長條空白區211‧‧‧ long blank area
213‧‧‧基板單位區213‧‧‧Substrate unit area
215‧‧‧長條區215‧‧‧Long strip area
220‧‧‧空白區220‧‧‧Blank area
300‧‧‧印刷電路板300‧‧‧Printed circuit board
第1圖係繪示根據本發明一較佳實施例之檢查記號的俯視圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a plan view showing an inspection mark in accordance with a preferred embodiment of the present invention.
第2圖係繪示根據本發明較佳實施例之檢查記號中、設置在防焊劑之底部上的圖案的俯視圖。Fig. 2 is a plan view showing a pattern provided on the bottom of the solder resist in the inspection mark according to the preferred embodiment of the present invention.
第3圖係繪示根據本發明較佳實施例之檢查記號中、防焊劑之第二開口的一偏心情形的俯視圖。Figure 3 is a plan view showing an eccentricity of the second opening of the solder resist in the inspection mark according to the preferred embodiment of the present invention.
第4圖係繪示具有根據本發明一較佳實施例之檢查記號的印刷電路板的俯視圖。Figure 4 is a top plan view of a printed circuit board having inspection indicia in accordance with a preferred embodiment of the present invention.
1、2、3、4‧‧‧電壓施加終端1, 2, 3, 4‧‧‧ voltage application terminals
1'、2'、3'、4'‧‧‧電壓測量終端1', 2', 3', 4'‧‧‧ voltage measuring terminals
100‧‧‧檢查記號100‧‧‧Check marks
150‧‧‧防焊劑層150‧‧‧ solder resist layer
150a‧‧‧第一開口150a‧‧‧first opening
150b‧‧‧第二開口150b‧‧‧second opening
160‧‧‧表面處理層160‧‧‧Surface treatment layer
Claims (15)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020110131500A KR101499281B1 (en) | 2011-12-09 | 2011-12-09 | Mark for inspecting and printed circuit board having the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201325359A TW201325359A (en) | 2013-06-16 |
| TWI500371B true TWI500371B (en) | 2015-09-11 |
Family
ID=48774825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101109545A TWI500371B (en) | 2011-12-09 | 2012-03-20 | Mark for inspection and printed circuit board having the same |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP5829165B2 (en) |
| KR (1) | KR101499281B1 (en) |
| TW (1) | TWI500371B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104573160A (en) * | 2013-10-25 | 2015-04-29 | 英业达科技有限公司 | Method and device for inspecting printed circuit |
| TWI471066B (en) * | 2013-11-06 | 2015-01-21 | Inventec Corp | Device and method for checking printed circuitry |
| JP6852375B2 (en) * | 2016-12-08 | 2021-03-31 | 凸版印刷株式会社 | Electroless nickel plating management method and wiring board manufacturing method |
| JP7277279B2 (en) * | 2019-06-20 | 2023-05-18 | ファナック株式会社 | Printed wiring board for deterioration detection |
| TWI723829B (en) * | 2020-04-01 | 2021-04-01 | 頎邦科技股份有限公司 | Circuit board |
| JP2022015110A (en) * | 2020-07-08 | 2022-01-21 | ファナック株式会社 | How to manufacture a printed circuit board and how to use a printed circuit board |
| KR102908324B1 (en) | 2020-09-18 | 2026-01-05 | 삼성전기주식회사 | Printed circuit board |
| TWI777806B (en) * | 2021-10-07 | 2022-09-11 | 易華電子股份有限公司 | Circuit board with test marks |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004045194A (en) * | 2002-07-11 | 2004-02-12 | Nec Toppan Circuit Solutions Toyama Inc | Inspection method for printed wiring board |
| WO2004111660A2 (en) * | 2003-06-05 | 2004-12-23 | Yieldboost Tech, Inc. | System and method for classifying defects in and identifying process problems for an electrical circuit |
| TW201036311A (en) * | 2009-03-31 | 2010-10-01 | Semiconductor Components Ind | Compensation method and circuit |
| JP2010263091A (en) * | 2009-05-07 | 2010-11-18 | Fujitsu Semiconductor Ltd | Wiring board manufacturing method and wiring board inspection method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3288320B2 (en) * | 1998-12-21 | 2002-06-04 | 沖電気工業株式会社 | Registration mark |
| JP2001024303A (en) * | 1999-07-09 | 2001-01-26 | Nippon Avionics Co Ltd | Recognition mark |
| JP2002064297A (en) * | 2000-08-22 | 2002-02-28 | Nec Ibaraki Ltd | Substrate aligning device |
| KR100894179B1 (en) * | 2007-10-26 | 2009-04-22 | 삼성전기주식회사 | PCB Strip |
-
2011
- 2011-12-09 KR KR1020110131500A patent/KR101499281B1/en not_active Expired - Fee Related
-
2012
- 2012-03-20 TW TW101109545A patent/TWI500371B/en not_active IP Right Cessation
- 2012-03-29 JP JP2012075738A patent/JP5829165B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004045194A (en) * | 2002-07-11 | 2004-02-12 | Nec Toppan Circuit Solutions Toyama Inc | Inspection method for printed wiring board |
| WO2004111660A2 (en) * | 2003-06-05 | 2004-12-23 | Yieldboost Tech, Inc. | System and method for classifying defects in and identifying process problems for an electrical circuit |
| TW201036311A (en) * | 2009-03-31 | 2010-10-01 | Semiconductor Components Ind | Compensation method and circuit |
| JP2010263091A (en) * | 2009-05-07 | 2010-11-18 | Fujitsu Semiconductor Ltd | Wiring board manufacturing method and wiring board inspection method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013123026A (en) | 2013-06-20 |
| KR101499281B1 (en) | 2015-03-06 |
| KR20130064891A (en) | 2013-06-19 |
| JP5829165B2 (en) | 2015-12-09 |
| TW201325359A (en) | 2013-06-16 |
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