TWI575745B - Mos transistor and process thereof - Google Patents

Description

MOS transistor and its process

The present invention relates to a MOS transistor and a process thereof, and more particularly to a MOS transistor having a metal gate and a process therefor.

In the conventional semiconductor industry, polycrystalline lanthanide is widely used in semiconductor components such as metal-oxide-semiconductor (MOS) transistors as a standard gate filling material. However, as the size of the MOS transistor continues to shrink, the conventional polysilicon gate causes a decrease in component efficiency due to boron penetration effects, and an unavoidable depletion effect, etc., resulting in an equivalent gate. The thickness of the dielectric layer increases, and the value of the gate capacitance decreases, which leads to the dilemma of the deterioration of the component driving capability. Therefore, the semiconductor industry is trying to replace the traditional polysilicon gate with a new gate filling material, such as a work function metal, to match the high dielectric constant (High-K) gate dielectric layer. Control electrode.

The present invention provides a MOS transistor and a process thereof for diffusing a low resistivity material to a wetting layer to form a transition layer having a function of a work function layer, so that it is not necessary to additionally form a success function layer.

The invention provides an MOS transistor, comprising a gate structure on a substrate, and the gate structure comprises a wetting layer, a transition layer and a low resistivity from bottom to top A material in which the transition layer has the function of a work function layer, and the gate structure does not contain any work function layer.

The present invention provides a MOS transistor process comprising the following steps. Forming a gate structure on a substrate, and the gate structure comprises a wetting layer, a transition layer and a low resistivity material from bottom to top, wherein the transition layer is formed by diffusion of the low resistivity material to the wetting layer, And the transition layer has the function of a work function layer, and the gate structure does not contain any work function layer.

Based on the above, the present invention provides a MOS transistor and a process thereof, which first form a wetting layer and a low resistivity material, and then form a transition layer by diffusing a component of the low resistivity material to the wetting layer. Between the wetting layer and the low resistivity material. The transition layer has the function of a work function layer, so that the metal gate formed by the present invention does not need to contain another work function layer. In this way, the MOS transistor of the present invention and the process thereof can improve the problem of filling holes and reduce the process cost.

The following is an example in which the present invention is combined with a Gate-Last for High-K First process, but in other embodiments, the present invention can also be applied to a post-high dielectric constant. The Gate-Last for High-K Last process, etc., but the invention is not limited thereto.

1 to 6 are schematic cross-sectional views showing a process of a MOS transistor according to a first embodiment of the present invention. As shown in FIG. 1, a substrate 110 is provided. The substrate 110 is, for example, a germanium substrate, a germanium-containing substrate, a tri-five-layered germanium substrate (eg, GaN-on-silicon), and a graphite. A semiconductor substrate such as a graphene-on-silicon or a silicon-on-insulator (SOI) substrate. An insulating structure 10 is formed in the substrate 110 to electrically insulate the respective transistors. The insulating structure 10 is, for example, a shallow trench isolation (STI) structure, which is formed, for example, by a shallow trench isolation process. The detailed formation method is well known in the art and will not be described again, but the invention is not limited thereto.

Continuing, a buffer layer (not shown), a gate dielectric layer (not shown), a bottom barrier layer (not shown), and a sacrificial electrode layer (not shown) are sequentially formed from bottom to top. And a cap layer (not shown) covering the substrate 110; subsequently, a cap layer (not shown), a sacrificial electrode layer (not shown), a bottom barrier layer (not shown), a gate dielectric layer ( The buffer layer (not shown) is patterned to form a buffer layer 122, a gate dielectric layer 124, a bottom barrier layer 126, a sacrificial electrode layer 128, and a cap layer 129 on the substrate 110. on. At this time, a sacrificial gate G is formed by the buffer layer 122, the gate dielectric layer 124, the bottom barrier layer 126, the sacrificial electrode layer 128, and the cap layer 129.

The buffer layer 122 can be an oxide layer, which is formed, for example, by a thermal oxidation process or a chemical oxidation process, but the invention is not limited thereto. The buffer layer 122 is located between the gate dielectric layer 124 and the substrate 110 for buffering the gate dielectric layer 124 and the substrate 110. In this embodiment, the gate dielectric layer 124 is a high dielectric constant gate dielectric layer, and the gate dielectric layer 124 is a high dielectric constant gate dielectric layer. It may be selected from hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (aluminum oxide, Al _{2 ).} O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), Strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium bismuth tantalate (SrBi _{2 )} Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST) A group is formed, but the invention is not limited thereto. In another embodiment, when applied to a post-gate high-potential (Gate-Last for High-K Last) process, the gate dielectric layer 124 is removed first in subsequent processes. In addition, a high dielectric constant gate dielectric layer is additionally filled. Therefore, the gate dielectric layer 124 in this embodiment may be a sacrificial material which is generally convenient for removal in a subsequent process, or a gate dielectric layer is not required. 124. Wait until the sacrificial electrode layer 128 is removed to form a high dielectric constant gate dielectric layer as the gate dielectric layer. The bottom barrier layer 126 is located on the gate dielectric layer 124, and is, for example, a single layer structure or a composite layer structure such as tantalum nitride (TaN) or titanium nitride (TiN). The sacrificial electrode layer 128 may be formed, for example, of polysilicon, but the invention is not limited thereto. The cap layer 129 may comprise a single layer or a plurality of layers such as a nitride layer or an oxide layer for use as a patterned hard mask.

Then, a spacer 130 is formed on the substrate 110 on the side of the sacrificial gate G, and an ion implantation process is performed to form a source/drain region 140 in the substrate 110 on its side. The spacer 130 is, for example, a single layer or a multilayer composite structure composed of a material such as tantalum nitride or tantalum oxide. Thereafter, an automatic alignment metal salicide process can be selectively performed to form a metal halide (not shown) on the source/drain region 140. Then, a contact etch stop layer (CESL) 150 can be selectively overlaid on the gate structure G, the spacers 130, and the substrate 110. Of course, before the ion implantation process is performed to form the source/drain region 140, A liner layer may be additionally formed and an ion implantation process may be performed to form a lightly doped source/drain region (not shown).

Then, an interlayer dielectric layer (not shown) is overlying the substrate 110 and the sacrificial gate G, and then planarized to remove the contact etch stop layer (CESL) on the sacrificial electrode layer 128. 150 and cap layer 129, and as shown in FIG. 2, an interlayer dielectric layer 160 is formed and the sacrificial electrode layer 128 is exposed. Next, the sacrificial electrode layer 128 is removed, and a recess r is formed as shown in FIG. 3 and the bottom barrier layer 126 is exposed.

Next, the bottom barrier layer 126 is removed, and as shown in FIG. 4, a U-shaped bottom barrier layer 126' is formed to cover the gate dielectric layer 124 and the interlayer dielectric layer 160, wherein the U-shaped bottom resistance The barrier layer 126' may be, for example, a single layer structure or a composite layer structure such as tantalum nitride (TaN) or titanium nitride (TiN). Then, an etch stop layer 127 is formed on the U-shaped bottom barrier layer 126', wherein the etch stop layer 127 is composed of a material such as tantalum nitride for removing the p-type during the CMOS transistor integration process. The work function layer in the transistor is used as an etch stop layer. Then, a work function layer 172 is formed to cover the etch stop layer 127. In this embodiment, an NMOS transistor is formed, and the formed work function layer 172 is an aluminum-titanium metal layer, but the invention is not limited thereto. In other embodiments, the work function layer 172 may also be a work function layer such as a titanium nitride layer to form a transistor having other electrical properties. A top barrier layer 174 is then formed over the work function layer 172. The top barrier layer 174 may be a titanium nitride layer or the like for preventing components in the material layer subsequently formed thereon from diffusing downward to the work function layer 172, the etch stop layer 127, the bottom barrier layer 126 or the gate. Dielectric layer 124, etc., reduce electricity The isoelectric property of the work function value of the crystal.

As shown in FIG. 5, a wetting layer 176 is formed over the top barrier layer 174. In the present embodiment, the wetting layer 176 is a titanium layer, but the invention is not limited thereto. The wetting layer 176 can be composed, for example, of a metal material such as titanium, cobalt or tantalum, which is interposed between the top barrier layer 174 and the subsequently formed low resistivity material to serve as a buffer for both and a low resistivity material. For attachment. A low resistivity material 178 is then formed over the wetting layer 176. The low resistivity material 178 can comprise a material comprised of aluminum or tungsten. The resistivity of the low resistivity material 178 is less than the resistivity of the wetting layer 176.

As shown in FIG. 6, a planarization process such as a chemical mechanical polishing (CMP) process is performed, uniformly planarized to expose the interlayer dielectric layer 160, and a metal gate M1 is formed in the recess r. The buffer layer 122, the gate dielectric layer 124, the flattened U-shaped bottom barrier layer 126", the planarized etch stop layer 127', and the planarized work function layer 172' a top barrier layer 174', a wetting layer 176' and a low resistivity material 178'. Then, for example, a lithography and etching process is performed to form at least one contact hole R in the interlayer dielectric layer 160, and The source/drain region 140 (or metal telluride (not shown) is exposed. Thereafter, a metal such as copper may be refilled to form a contact plug (not shown) in the contact hole R, and the source/ The drain region 140 is electrically connected to other semiconductor components. Of course, a contact plug (not shown) is also formed over the metal gate M1 to electrically connect the metal gate M1 to other semiconductor components. For example, in other implementations. In the aspect, an interlayer dielectric layer may be formed before the contact hole R is formed (not Illustrated on the interlayer dielectric layer 160 to cover the interlayer dielectric layer 160 and the metal gate M1. Then, the contact holes R are simultaneously formed to inter-layer dielectric A layer (not shown) and an interlayer dielectric layer 160 are further filled with a metal such as copper and planarized, thereby simultaneously forming contact plugs (not shown) in the source/drain region 140 (or metal germanide (or metal halide). Not shown)) and the metal gate M1.

In the above, the present invention forms a metal gate M1 including a buffer layer 122, a gate dielectric layer 124, a planarized U-shaped bottom barrier layer 126", a planarized etch stop layer 127', and a work function layer 172' a stack structure of a top barrier layer 174', a wetting layer 176', and a low resistivity material 178'. However, as the size of the semiconductor component shrinks, too many of the material layers are formed in the recess r. The low resistivity material 178' is difficult to fill due to the small opening of the groove r, and it is necessary to go through multiple processes to form these material layers separately, resulting in high process cost.

Therefore, the second embodiment of the present invention is further proposed to further improve the problems such as difficulty in filling holes in the first embodiment, and to simplify the manufacturing process to reduce the process cost. 7-9 are schematic cross-sectional views showing a process of a MOS transistor according to a second embodiment of the present invention. The process of the present embodiment is the same as that of the first embodiment, as in the first embodiment, in other words, the sacrificial gate G is formed on the substrate 110; the spacer 130 is formed on the substrate 110 on the side of the sacrificial gate G; Forming a source/drain region 140 in the substrate 110 on the side of the spacer 130; forming a metal halide (not shown) on the source/drain region 140; selectively covering a contact hole etch stop layer (contact The etch stop layer (CESL) 150 is on the gate structure G, the spacer 130, and the substrate 110; the interlayer dielectric layer 160 is formed and the sacrificial electrode layer 128 is exposed; the process of forming the recess r and exposing the bottom barrier layer 126 are performed. The first embodiment is the same.

After the recess r is formed and the bottom barrier layer 126 is exposed, the bottom barrier layer 126 is removed first, and as shown in FIG. 7, a U-shaped bottom barrier layer 126' is overlaid to cover the gate dielectric layer 124. And the interlayer dielectric layer 160, wherein the U-shaped bottom barrier layer 126 ′ can also be a single layer structure or a composite layer structure such as tantalum nitride (TaN) or titanium nitride (TiN). Then, an etch stop layer 127 is formed on the U-shaped bottom barrier layer 126', wherein the etch stop layer 127 is composed of a material such as tantalum nitride for removing the p-type during the CMOS transistor integration process. The work function layer in the transistor is used as an etch stop layer. Then, the second embodiment directly forms a top barrier layer 274 to cover the etch stop layer 127 without forming a work function layer as described in the first embodiment. A wetting layer 276 is then formed over the top barrier layer 274. In a preferred embodiment, top barrier layer 274 and wetting layer 276 are formed in-situ. For example, when the top barrier layer 274 is a titanium nitride layer and the wetting layer 276 is a titanium layer, a deposition process such as a physical vapor deposition (PVD) process may be performed, which may be preceded by When titanium is applied, nitrogen gas is introduced to form a titanium nitride layer, and then nitrogen gas is stopped to form a titanium layer, but the invention is not limited thereto. In this way, the thickness of the top barrier layer 274 plus the wetting layer 276 can be reduced, and the top barrier layer 274 can be effectively prevented from being oxidized before the wetting layer 276 is formed, and the thickness of an additional oxide layer is increased. Reduce the electrical conductivity. For example, in the first embodiment, the top barrier layer 174' is a titanium nitride layer having a thickness of 40 angstroms, and the wetting layer 176' is a titanium layer having a thickness of 100 angstroms ( Angstroms), and the top barrier layer 174' and the wetting layer 176' are prepared on different machines, not only need to break the vacuum, affecting the productivity, but also easily cause the top barrier layer 274 to be oxidized, and the subsequent wetting layer 176' is not easily attached; but in the present embodiment, the top barrier layer 274 plus the wetting layer 276 has a thickness of only 100 angstroms, and By controlling the time of nitrogen gas flow, the top barrier layer 274 and the wetting layer 276 are continuously formed in an in-situ manner, which not only has good bonding, process simplification, but also eliminates the original top barrier layer 174. 'thickness of. Furthermore, the thickness of the bottom layer S1 of the wetting layer 276 is preferably greater than the thickness of the side wall S2 (for example, the thickness of the bottom layer S1 of the wetting layer 276 is 80 angstroms, and the thickness of the side wall S2 is 40 angstroms). The portion of the bottom layer S1 of the wetting layer 276 can sufficiently prevent the components formed subsequently thereon from diffusing downward, and the thinner side wall portion S2 of the wetting layer 276 can increase the opening width of the recess r, so that the subsequent low resistance Rate material filling holes is easier.

Next, as shown in FIG. 8, a low resistivity material 280 is formed on the wetting layer 276. It should be noted that the second embodiment diffuses to the wetting layer 276 by the low resistivity material 280 to form a transition layer 290 directly between the low resistivity material 280 and the wetting layer 276, and by selecting The low resistivity material 280 and the material of the wetting layer 276, the transition layer 290 has the function of a work function layer, so that the formed gate structure does not contain any work function layer, especially the top barrier layer 274 and etching Between the stop layers 127, preferably, there is no work function layer between the wetting layer 276 and the gate dielectric layer 124. Thus, since it is not necessary to additionally form the work function layer 172' as described in the first embodiment, the top barrier layer 274 and the wetting layer 276 are continuously formed in an in-situ manner to have a thinner film. The embodiment can solve the problem that the low resistivity material 280 is difficult to fill holes and the process cost is reduced in the previous embodiment. In particular, the wetting layer 276 can be, for example, a titanium layer and the low resistivity material 280, for example, aluminum. As such, as the aluminum of the low resistivity material 280 diffuses down to the wetting layer 276, it can react with the titanium in the partially wetting layer 276 to form the transition layer 290 of the aluminum titanium metal layer. The chemical formula of the transition layer 290 may include Ti _x Al _y , preferably y > x. For example, the chemical formula of the transition layer 290 is preferably TiAl ₃ , but the invention is not limited thereto. In this embodiment, the transition layer 290 is also an aluminum-titanium metal layer, and thus can replace the work function layer 172' (which is also an aluminum-titanium metal layer for forming an NMOS transistor) in the first embodiment. In other embodiments, the wetting layer 276 and the low resistivity material 280 can also be a combination of other materials. For example, the wetting layer 276 can comprise titanium, cobalt or tantalum, etc., and the combined low resistivity material 280 can comprise tungsten, aluminum, or the like. The low-resistivity material 280 composed of tungsten has a slower diffusion rate than aluminum, so that the lower U-shaped bottom barrier layer 126', the etch stop layer 127, and the top barrier layer 274' can be further reduced. thickness.

As shown in FIG. 9, a polishing process such as a chemical mechanical polishing process is performed to planarize the low resistivity material 280, the transition layer 290, the wetting layer 276, the top barrier layer 274, the etch stop layer 127, and the U-shaped bottom. The barrier layer 126' is formed to form a planarized U-shaped bottom barrier layer 126", a planarized etch stop layer 127', and a planarized top barrier layer 274', a wetting layer 276', a transition layer 290', and a low resistivity material 280', thus forming a metal gate M2. Thereafter, at least one contact hole R is formed in the interlayer dielectric layer 160 and the source/drain region 140 is exposed ( Or a metal telluride (not shown). Then, a contact plug (not shown) may be formed in the contact hole R to cause the source/drain region 140 (or metal telluride (not shown)). The other semiconductor components are electrically connected to the outside. Similarly, in other embodiments, an interlayer dielectric layer (not shown) may be formed on the interlayer dielectric layer 160 before the contact holes R are formed to cover the interlayer layers. Dielectric layer 160 and metal gate M2. Then, each contact hole R is simultaneously formed on the interlayer dielectric layer (not shown) and between the layers Layer 160, a metal such as copper and then filled and planarized, thereby forming the contact plug (not shown) 140 (or a metal silicide in the source / drain regions at the same time (not Show)) and the metal gate M2. Thereafter, other subsequent semiconductor processes can be performed, which are well known in the art and will not be described again.

According to the present invention, a MOS transistor can be formed by applying the above MOS transistor process. As shown in FIG. 9, the metal gate M2 (or a gate structure) can be disposed on the substrate 110. The metal gate M2 may be a stacked structure, and may include a buffer layer 122, a gate dielectric layer 124, a U-shaped bottom barrier layer 126", an etch stop layer 127', and a top barrier layer 274' from bottom to top. a wetting layer 276', a transition layer 290', and a low resistivity material 280'. Since the transition layer 290' of the present invention has the function of a work function layer, the metal gate M2 of the present invention does not need to contain other work. The function layer, in particular, does not have any work function layer between the wetting layer 276' and the gate dielectric layer 124. Thus, since the present invention does not require another step of depositing a work function layer, even In the tendency that the size of the semiconductor element is shrinking, the opening having the larger groove r can be filled with the low-resistivity material 280', thereby solving the problem of filling holes in the first embodiment and reducing the process cost. For example, the wetting layer 276' of the present invention may be composed of a titanium layer, and the low-resistivity material 280' may be composed of aluminum, and the transition layer 290' formed by the two is an aluminum-titanium metal layer, which may have Function of the work function layer. In detail, by adjusting the low resistivity material 28 The process temperature of 0' or an annealing process after forming the low resistivity material 280 can change the phase of the transition layer 290', and can change the microstructure of the transition layer 290', thereby adjusting the work function. Value isoelectric parameters to achieve the desired use. For example, at different process temperatures of the low resistivity material 280' or different annealing processes, the transition layer 290' may have a chemical formula of Ti _x Al _y , The x, y values may be variable; or, the x, y values may have different distributions depending on their different positions or depths.

In addition, the present invention can be adjusted by adjusting the thickness of the U-shaped bottom barrier layer 126', the etch stop layer 127, the top barrier layer 274', the wetting layer 276', the transition layer 290', and the low resistivity material 280' or Material to change the isoelectric parameter of the work function value of the formed transistor. For example, by changing the thickness or material of the U-shaped bottom barrier layer 126', the etch stop layer 127, the top barrier layer 274', the gate of the low-resistivity material 280' and the like can be controlled to diffuse to or below the gate. The content of the dielectric layer 124 changes the electrical function value of the transistor, the Equivalent Oxide Thickness (EOT) or the leakage current density (Jg). In general, since a low-resistivity material 280' or the like diffuses to the gate dielectric layer 124, a problem of leakage current occurs, and the bottom barrier layer 126' or the etch stop layer is generally controlled to diffuse into a U-shape. 127 instead of spreading down is better. More preferably, however, the thickened etch stop layer 127 is preferably thicker than the thicker U-shaped bottom barrier layer 126' or top barrier layer 274' because of the thickened U-shaped bottom barrier layer 126' or The thickness of the top barrier layer 274' may cause the work function value to be opposite to the desired value, wherein the method of thickening the etch stop layer 127, for example, by an atomic layer deposition (ALD) process, may increase the process The etch stop layer 127 can be thickened by cycles. In addition, for example, when the material of the top barrier layer 274' is titanium nitride, the degree of downward diffusion of the metal component or the like above can be controlled by adjusting the ratio of nitrogen and titanium to change the work function value isoelectricity. parameter. Moreover, since the U-shaped bottom barrier layer 126' or the etch stop layer 127 is adjusted to prevent the metal component or the like above from diffusing downward, the top barrier layer 274' can be omitted to further reduce the process cost and Improve the difficulty of filling holes.

In summary, the present invention provides a MOS transistor and a process thereof, which first form a wetting layer and a low resistivity material, and then form a transition layer by diffusing a component of the low resistivity material to the wetting layer. . The transition layer has the function of a work function layer, so that the metal gate formed by the present invention does not need to contain another work function layer. In this way, the MOS transistor of the present invention and the process thereof can improve the problem of filling holes and reduce the process cost. Furthermore, the electrical parameters of the formed transistor can be changed by adjusting the material and thickness of the bottom barrier layer, the etch stop layer, the top barrier layer, the wetting layer, the transition layer, and the low resistivity material. For example, work function value, Equivalent Oxide Thickness (EOT) or leak current density (Jg).

Furthermore, the top barrier layer and the wetting layer of the present invention may be formed in situ. For example, when the top barrier layer is a titanium nitride layer and the wetting layer is a titanium layer, a deposition process such as a physical vapor deposition (PVD) process can be performed, which can be first performed during titanium plating. Nitrogen gas was introduced to form a titanium nitride layer, and then nitrogen gas flow was stopped to form a titanium layer by electroplating. Thus, the thickness of the top barrier layer plus the wetting layer can be reduced, and the top barrier layer can be prevented from being oxidized before the wetting layer is to be formed.

Although the U-shaped bottom barrier layer 126", etch stop layer 127', top barrier layer 274', wetting layer 276', transition layer 290', and low resistivity material 280' are coplanar in the illustration (ie, The upper surface is cut, but it should be understood that an etch back process may be performed for one or more of the film layers after forming the film layers and performing a polishing process such as the chemical mechanical polishing process of FIG. The upper surface is made lower than the upper surface of the ground interlayer dielectric layer 160.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Insulation structure

110‧‧‧Base

122‧‧‧buffer layer

124‧‧‧ gate dielectric layer

126‧‧‧ bottom barrier

126', 126"‧‧ U-shaped bottom barrier layer 126'

127, 127' ‧ ‧ etch stop layer

128‧‧‧Sacrificial electrode layer

129‧‧‧ cover

130‧‧‧ spacer

140‧‧‧Source/Bungee Zone

150‧‧‧Contact hole etch stop layer

160‧‧‧Interlayer dielectric layer

172, 172'‧‧‧ work function layer

174, 174', 274, 274' ‧ ‧ top barrier

176, 176', 276, 276' ‧ ‧ wetting layer

178, 178', 280, 280'‧‧‧ low resistivity materials

290, 290’ ‧ ‧ transition layer

G‧‧‧sacrificial gate

M1, M2‧‧‧ metal gate

R‧‧‧ groove

R‧‧‧Contact hole

S1‧‧‧ bottom

S2‧‧‧ side wall

1 to 6 are schematic cross-sectional views showing a process of a MOS transistor according to a first embodiment of the present invention.

7-9 are schematic cross-sectional views showing a process of a MOS transistor according to a second embodiment of the present invention.

10‧‧‧Insulation structure

110‧‧‧Base

122‧‧‧buffer layer

124‧‧‧ gate dielectric layer

126"‧‧‧U-shaped bottom barrier

127’‧‧‧etch stop layer

130‧‧‧ spacer

140‧‧‧Source/Bungee Zone

150‧‧‧Contact hole etch stop layer

160‧‧‧Interlayer dielectric layer

274’‧‧‧Top barrier

276'‧‧‧ Wetting layer

280'‧‧‧ Low resistivity material

290’‧‧‧Transition layer

M2‧‧‧Metal Gate

R‧‧‧Contact hole

Claims (20)

A MOS transistor comprising: a gate structure on a substrate, the gate structure comprising a wetting layer, a transition layer and a low resistivity material from bottom to top, wherein the transition layer is sandwiched between the Between the wet layer and the low resistivity material, the transition layer functions as a work function layer. The MOS transistor of claim 1, wherein the wetting layer comprises titanium, cobalt or ruthenium. The MOS transistor according to claim 1, wherein the low resistivity material has a resistivity smaller than a resistivity of the wetting layer and the transition layer, and the low resistivity material comprises aluminum or tungsten. The MOS transistor of claim 1, wherein the transition layer comprises Ti _x Al _y . The MOS transistor of claim 4, wherein the transition layer comprises TiAl ₃ . The MOS transistor of claim 1, wherein the MOS transistor comprises an NMOS transistor. The MOS transistor according to claim 1, wherein the gate structure further comprises a dielectric layer, a bottom barrier layer and an etch stop layer from bottom to top. Between the substrate and the wetting layer. The MOS transistor according to claim 7, wherein the bottom barrier layer comprises a titanium nitride layer, and the etch stop layer comprises a tantalum nitride layer. The MOS transistor of claim 1, wherein the gate structure further comprises a top barrier layer between the substrate and the wetting layer. The MOS transistor of claim 9, wherein the top barrier layer comprises a titanium nitride layer. A MOS transistor process includes: forming a gate structure on a substrate, and the gate structure includes a wetting layer, a transition layer, and a low resistivity material from bottom to top, wherein the transition layer is low A resistivity material is formed by diffusion into the wetting layer, the transition layer being sandwiched between the wetting layer and the low resistivity material, and the transition layer has the function of a work function layer. The MOS transistor process of claim 11, wherein the wetting layer comprises titanium, cobalt or ruthenium. The MOS transistor process of claim 11, wherein the low resistivity material comprises aluminum or tungsten. The MOS transistor process of claim 11, wherein the transition layer comprises Ti _x Al _y . The MOS transistor process of claim 14, wherein the transition layer comprises TiAl ₃ . The MOS transistor process of claim 11, wherein the MOS transistor comprises an NMOS transistor. The MOS transistor process of claim 11, wherein the step of forming the gate structure further comprises: forming a dielectric layer, a bottom barrier layer, and an etch stop layer from bottom to top, the substrate is located on the substrate And between the wetting layers. The MOS transistor process of claim 11, wherein the step of forming the gate structure further comprises: forming a top barrier layer between the substrate and the wetting layer. The MOS transistor process of claim 18, wherein the top barrier layer and the wetting layer are formed in-situ. The MOS transistor process of claim 19, wherein the top barrier layer comprises a titanium nitride layer and the wetting layer comprises a titanium layer.