TW201301360A - Transistor having aluminum metal gate and method of making the same - Google Patents

Abstract

A transistor having an aluminum metal gate includes a substrate, a high-k gate dielectric layer, an aluminum metal gate and a source/drain region. The high-k gate dielectric layer is disposed on the substrate. The aluminum metal gate includes a work function tuning layer and an aluminum layer disposed orderly on the high-k gate dielectric layer. The aluminum layer includes a first aluminum layer and a second aluminum layer formed through a two-step aluminum disposition process. The source/drain region is disposed in the substrate at two sides of the aluminum metal gate.

Description

Transistor with aluminum metal gate and manufacturing method thereof

The invention relates to a crystal having an aluminum metal gate and a manufacturing method thereof, in particular to a crystal of an aluminum metal gate having a relatively uniform crystal size distribution and a manufacturing method thereof.

As the size of metal-oxide-semiconductor (MOS) transistor components continues to shrink, the thickness of the gate dielectric layer also shrinks with line width. However, if the thickness of the gate dielectric layer is insufficient to support the gate Extreme voltages can cause severe leakage currents. In addition, polysilicon gates are also susceptible to reduced device performance due to boron penetration effects. Therefore, the semiconductor industry has attempted to use a metal gate and a high dielectric constant (High-K) material to replace the conventional polysilicon gate and oxide gate dielectric layer as a new gate combination.

In order to match the high dielectric constant (High-K) gate dielectric layer, the metal gate can be formed by a combination of a work function metal layer and a low resistance metal layer, wherein the material of the low resistance metal layer can include aluminum. Therefore, how to make a good quality aluminum metal gate to increase the reliability of the electrical component of the transistor is a problem that the related art desires to improve.

One of the objects of the present invention is to provide a transistor having an aluminum metal gate and a method of fabricating the same to obtain electrical reliability of a preferred transistor component.

A preferred embodiment of the present invention provides a method of fabricating a metal gate comprising the following steps. A substrate is provided and a sacrificial gate structure is formed on the substrate, and an opening is formed in the sacrificial gate structure. And then filling an aluminum metal layer into the opening, and the step of: performing a pre-deposition step to form a first aluminum metal layer on the opening, and performing a main deposition step to form a second aluminum metal layer On the first aluminum metal layer.

Another preferred embodiment of the present invention provides a transistor having an aluminum metal gate including: a substrate; a high dielectric constant gate dielectric layer disposed on the substrate; an aluminum metal gate, an aluminum metal gate The pole includes a work function metal layer and an aluminum metal layer sequentially disposed on the high dielectric constant gate dielectric layer, wherein the aluminum metal layer comprises a first aluminum metal layer and a second aluminum metal layer; and a source / drain region, disposed in the substrate on both sides of the aluminum metal gate.

The invention forms a aluminum metal layer of an aluminum metal gate in a two-stage process, comprising a pre-deposition step to form a first aluminum metal layer and a main deposition step to form a second aluminum metal layer, wherein a process average temperature of the pre-deposition step is substantially The upper portion is smaller than the average process temperature of forming the second aluminum metal layer, and in the pre-deposition step of forming the first aluminum metal layer, a fluid which assists heat conduction such as argon gas or the like is not introduced into the back surface of the substrate. The two-stage aluminum metal deposition process can reduce the hole-like defects of the aluminum metal layer to improve the crystal size uniformity of the aluminum metal layer and increase the reliability of the electrical properties of the transistor element.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

In order to reduce the hole-like defects formed by the current physical vapor deposition (PVD) process of the aluminum metal layer due to different crystal sizes, the present invention proposes to deposit aluminum alloy with better uniformity by a two-stage process. Floor. Please refer to Table 1. Table 1 shows the gate-fill process steps of the first preferred embodiment and the second preferred embodiment of the present invention. As shown in Table 1, the process steps of the first preferred embodiment can be divided into three steps including: preheating, aluminum metal layer deposition, and reflow, while the process steps of the second preferred embodiment are compared with the first step. Compared with the steps of the preferred embodiment, the process steps of the second preferred embodiment do not perform the preheating step, and the aluminum metal layer deposition is divided into two steps, that is, the first preferred embodiment is fixed at a fixed A single aluminum metal layer deposition is performed at a temperature, and the aluminum metal layer deposition of the second preferred embodiment can be divided into a pre-deposition step for performing a first aluminum metal layer deposition and a main deposition step for performing a second aluminum metal layer deposition. The process average temperature of the pre-deposition step in which the first aluminum metal layer is formed is substantially smaller than the process average temperature at which the second aluminum metal layer is formed. In addition, a heater for controlling the process temperature is disposed on the back surface of the substrate for which aluminum metal deposition is scheduled, in order to keep the substrate heated uniformly and the process temperature is stable, and a fluid for assisting heat conduction may be introduced into the back surface of the substrate during the process, for example, : Argon and so on. In the second preferred embodiment of the step of forming the first aluminum metal layer, the back side of the substrate on which the aluminum metal layer is deposited is not subjected to a fluid for assisting heat conduction, for example, argon gas is not introduced into the back surface of the wafer. In addition, the second preferred embodiment can also adjust the thermal budget of the process by using a different temperature recovery step time than the first preferred embodiment, for example, to compensate for the thermal budget loss without performing the preheating step. And increase the time of the warming step.

It is to be noted that the aluminum metal layer of the first preferred embodiment has a crystal size (grain) obtained by the process of the first preferred embodiment as compared with the aluminum metal layer of the second preferred embodiment. The size is different, and a rough surface having a pin hole is formed, and the aluminum metal crystal size distribution is different between different transistor elements. However, the aluminum metal layer obtained by the process of the second preferred embodiment has a small number of surface pin holes and a large refractive index, that is, the two-stage aluminum of the second preferred embodiment is used. The metal layer deposition process can obtain an aluminum metal layer having a better grain size uniformity, and can provide better reliability of the electrical characteristics of the transistor element.

The invention can be applied to various semiconductor processes, such as metal interconnects and metal gates. Now, the high-k first process integrated in the gate last process and the two-stage deposition process of the aluminum metal layer of the second preferred embodiment are taken as an example. Referring to Figures 1 through 6, Figures 1 through 6 are schematic views of a transistor having an aluminum metal gate in accordance with a preferred embodiment of the present invention. As shown in FIG. 1, a substrate 11 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate, and a plurality of shallow trench isolations are formed on the substrate. , STI) 12. Next, an interfacial layer 13, a high dielectric constant gate dielectric layer 14, an etch stop layer 15, a sacrificial gate material layer 16, and a cap layer 17 are deposited on the substrate 11. The formation method can be carried out by various conventional deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., but not limited thereto. The dielectric layer 13 is selectively disposed on the substrate 11 to provide a high dielectric constant gate dielectric layer 14 having better adhesion to the substrate 11. The material may be cerium oxide or nitrogen-containing cerium oxide. Nitridation silicon dioxide or low dielectric constant material, but not limited to this. The high dielectric constant gate dielectric layer 14 can be a metal oxide layer, such as a rare earth metal oxide layer. The high dielectric constant gate dielectric layer 14 may be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and hafnium silicon oxynitride (HfSiON). , aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), oxidation Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), yttrium Oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr) _a group consisting of _1-x TiO ₃ , BST). The etch stop layer 15 may be formed of titanium nitride (TiN) or tantalum nitride (TaN), but is not limited thereto, and is selectively disposed on the high dielectric constant gate dielectric layer 14 and the sacrificial gate material layer 16. As a barrier layer, the lower high dielectric constant gate dielectric layer 14 is protected. The sacrificial gate material layer 16 may be composed of a polycrystalline germanium material having no undoped or polycrystalline germanium material having an N+ dopant, and the cap layer 17 is disposed on the sacrificial gate material layer 16, which may be made of cerium oxide (SiO). ₂ ), tantalum nitride or bismuth oxynitride (SiON) and other materials, the constituent materials are not limited to this.

Then, as shown in FIG. 2, a patterned photoresist layer (not shown) is formed on the cap layer, and a pattern transfer process is performed using the patterned photoresist layer as a mask to perform single or successive etching. The step of removing a portion of the cap layer 17, a portion of the sacrificial gate material layer 16, a portion of the etch stop layer 15, a portion of the high dielectric constant gate dielectric layer 14 and a portion of the dielectric layer 13, and stripping the patterning The photoresist layer is formed to form a patterned dielectric layer 13, a patterned high-k gate dielectric layer 14, a patterned etch stop layer 15, a patterned sacrificial gate material layer 16, and a patterned cap layer 17. The sacrificial gate structure 18. At this time, a lightly doped source/drain region 19 may be further formed in the substrate on both sides of the sacrificial gate structure 18.

Next, as shown in FIG. 3, a sidewall 20 is formed on the sidewall of the sacrificial gate structure 18. The sidewall 20 may be a single layer or a multilayer structure, or may include a liner (not shown) and the like. composition. The material of the sidewall 20 may include a high temperature oxide (HTO), tantalum nitride, hafnium oxide or tantalum nitride (HCD-SiN) formed using hexachlorodisilane (Si ₂ Cl ₆ ). But not limited to this. The method of forming the side wall 20 is a conventional technique and will not be described herein. Then, using the sidewall 20 and the cap layer 17 as a mask, an ion implantation process is performed, and a suitable dopant is doped, and the dopant may include an N-type or P-type dopant to sacrifice the substrate on both sides of the gate structure 18. A source/drain region 21 is formed in each of 11 and is combined with an annealing process to activate the source/drain regions 21.

In addition, the transistor of the present invention may still comprise other semiconductor structures (not shown), such as a metal silicide layer on the source/drain region 21, with a substrate etch back process and a selective A selective epitaxial growth (SEG) process is performed to form an epitaxial layer having germanium and other materials in the source/drain regions 21 or other protective layers. In an embodiment, after the source/drain region 21 or the metal telluride layer (not shown) is completed, the sidewall spacers 20 may be further partially or completely removed, so that the subsequently formed contact hole etch stop layer is formed. (Contact etch stop layer, CESL) has better stress for the transistor, and the material of the contact hole etch stop layer may include, for example, tantalum nitride. In addition, although the present embodiment preferably forms the lightly doped source/drain region 19, the sidewall spacer 20, and the source/drain region 21 in sequence, the present invention is not limited thereto, and the present invention may be further in accordance with the process. The above requirements arbitrarily adjust the order in which the sidewalls and the doped regions are formed, which are all covered by the present invention.

As shown in FIG. 4, a contact hole etch stop layer 22 and an inter-layer dielectric (ILD) 23 are sequentially deposited to cover the sacrificial gate structure 18, and a planarization process is performed, for example, a chemical mechanical polish (CMP) process or an etch process to sequentially remove portions of the inner dielectric layer 23, a portion of the contact hole etch stop layer 22, and a portion of the sidewall spacers 20, The patterned cap layer 17 is completely removed until the sacrificial gate material layer 16 is exposed. Next, as shown in FIG. 5, the sacrificial gate material layer 16 is removed using the etch stop layer 15 as a protective layer of the high dielectric constant gate dielectric layer 14 to form an opening in the sacrificial gate structure 18. 24, this can be achieved by, for example, an etching process including dry etching or wet etching. For example, in one embodiment, the sacrificial gate material layer 16 is dry etched with chlorine gas as an etching gas, and then four hydroxides are used. The tetramethyl ammonium hydroxide (TMAH) solution is used as an etchant to remove the remaining sacrificial gate material layer 16, but is not limited thereto.

Then, as shown in FIG. 6, and referring to FIG. 5 together, a work function metal layer 25 is formed in the opening 24 and an aluminum metal layer 26 is filled to complete an aluminum metal gate 27. The work function metal layer 25 is disposed on the high dielectric constant gate dielectric layer 14 and on the sidewall of the opening 24, and the work function of the aluminum metal gate 27 formed thereafter can be adjusted to make it suitable for an N-type transistor (NMOS). Or P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 25 may be selected from a metal material having a work function of 3.9 eV to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), and tungsten aluminide. (WAl), tantalum aluminide (TaAl) or hafnium aluminide (HfAl), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 25 may have a work function of 4.8 eV to 5.2 eV. Metal materials such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto.

It should be noted that the deposition method of the aluminum metal layer 26 of the present invention filled in the opening 24 is the two-stage process of the second preferred embodiment. As mentioned above, the two-stage process can be a pre-deposition step and a main deposition step. In the pre-deposition step, the temperature in the reaction chamber is slightly decreased when the substrate 11 first enters the reaction stage, and is shortened. The temperature time and the increase of the thermal budget are avoided, at which time a fluid that assists in heat conduction, such as argon, is not introduced into the back side of the substrate 11, and the deposition of the first aluminum metal layer 28 is performed at this stage. After the first aluminum metal layer 28 is deposited to a predetermined thickness, the main deposition step is performed. In the main deposition step, the temperature in the reaction chamber is stabilized, and aluminum deposition can be performed under constant temperature conditions, and a fluid that assists heat conduction is applied to the back surface of the substrate 11 to stabilize the temperature of the substrate 11, and the second stage is performed at this stage. Deposition of the aluminum metal layer 29. In other words, in the preferred embodiment, the average process temperature of the pre-deposition step of forming the first aluminum metal layer 28 is substantially less than the average process temperature of the main deposition step of forming the second aluminum metal layer 29, and in forming In the pre-deposition step of the aluminum metal layer 28, a fluid such as argon gas or the like which assists heat conduction is not introduced to the back surface of the substrate 11. Therefore, the two-stage process of the present invention can provide an aluminum metal layer 26 having a uniform crystal size uniformity and a large surface refractive index. In addition, after the success function metal layer 25 and the aluminum metal layer 26, a planarization process, such as a chemical mechanical polish (CMP) process, removing part of the work function metal layer 25 and portions may be performed. The aluminum metal layer 26 is on the top surface of the inner dielectric layer 23, and thus a transistor 30 having an aluminum metal gate 27 is completed.

In the transistor having the aluminum metal gate of the embodiment, the thickness of the first aluminum metal layer is preferably substantially smaller than the thickness of the second aluminum metal layer, that is, the thickness of the first aluminum metal layer is substantially smaller than the aluminum metal gate. One-half of the total thickness of the aluminum metal layer required. In the aluminum-metal two-stage process, the pre-deposition step and the main deposition step are based on the above description at the average process temperature and whether a fluid for assisting heat conduction is introduced at the back of the substrate. Conditions vary. In addition, the present embodiment can control the thickness of the aluminum metal layer formed by the two-stage process by changing the aluminum metal deposition time while maintaining the same reactant concentration and other identical reaction conditions, wherein the thickness is changed in such a manner that the deposition time is not adjusted. Limited. In more detail, the thickness of the first aluminum metal layer in the aluminum metal gate is substantially equal to or greater than one eighth of a predetermined total thickness of the aluminum metal layer of the aluminum metal gate, and the thickness of the first aluminum metal layer is less than the second The thickness of the aluminum metal layer, that is, when the aluminum metal layer of the aluminum metal gate has a predetermined total thickness of 4000 angstroms, the thickness of the first aluminum metal layer may be substantially between 500 angstroms and 2000 angstroms. In addition, the refractive index of the aluminum metal gate is proportional to the thickness of the first aluminum metal layer in the aluminum metal gate, that is, when the thickness of the first aluminum metal layer is larger, a flat surface of the aluminum metal gate can be provided. In order to detect a larger refractive index, in other embodiments, the thickness of the first aluminum metal layer is preferably substantially one-fifth or better than a predetermined total thickness of the aluminum metal layer of the aluminum metal gate. It is substantially one third of a predetermined total thickness of the aluminum metal layer of the aluminum metal gate, and the thickness of the first aluminum metal layer needs to be smaller than the thickness of the second aluminum metal layer.

The transistor having the aluminum metal gate of the present invention is not limited to the above embodiment. Hereinafter, a transistor having an aluminum metal gate according to another preferred embodiment of the present invention will be described. For example, the present invention can also be integrated into a gate-high-K last process after a gate last process. And in conjunction with the second preferred embodiment of the foregoing aluminum metal layer two-stage deposition process, and in order to facilitate the comparison of the various embodiments and simplify the description, the same symbols are used in the following embodiments to mark the same components. The description of the differences between the embodiments will be mainly made, and the repeated parts will not be described again. Please refer to Figure 7, and please refer to Figure 3 together. Figure 7 is a schematic view of a transistor having an aluminum metal gate in accordance with another preferred embodiment of the present invention. As shown in FIG. 7, unlike the previous embodiment, the present embodiment completely removes the linear high dielectric constant gate dielectric layer 14, the etch stop layer 15, and the sacrificial gate material layer 16 in the sacrificial gate structure 18. And patterning the cap layer 17 to form an opening (not shown) exposing a portion of the substrate 11, and re-forming a metal gate structure 31 in the opening on the substrate 11, the gate structure 31 including a cross section U A high dielectric constant gate dielectric layer 32 and an aluminum metal gate 27 are formed. The method of forming the U-shaped high dielectric constant gate dielectric layer 32 is known to those skilled in the art and will not be described herein. The aluminum metal gate 27 includes a work function metal layer 25 and an aluminum metal layer 26. It should be noted that the aluminum metal layer 26 of the present embodiment includes a first aluminum metal layer 28 and a second aluminum metal layer 29 prepared by a two-stage process, and the first aluminum metal layer 28 has a thickness h1 smaller than that of the second aluminum metal layer. The thickness h2 of 29, and the thickness h1 of the first aluminum metal layer 28 is substantially greater than or equal to one eighth of the thickness h of the aluminum metal layer 26 of the aluminum metal gate 27. In other embodiments, the first aluminum metal layer 28 The thickness h1 is preferably substantially one-fifth or more of the thickness h of the aluminum metal layer 26 of the aluminum metal gate 27, or more preferably three or more of the thickness h of the aluminum metal layer 26 of the aluminum metal gate 27. one. The source/drain regions 21 are disposed in the substrate 11 on both sides of the aluminum metal gate 27. In addition, a dielectric layer can be selectively disposed between the substrate 11 and the U-shaped high dielectric constant gate dielectric layer 32 to provide better adhesion of the U-shaped high dielectric constant gate dielectric layer 32. The material of the dielectric layer may be cerium oxide or nitrogen-containing nitridation silicon dioxide, but not limited thereto.

In summary, the present invention performs aluminum metal layer deposition of an aluminum metal gate in a two-stage process, including a pre-deposition step to form a first aluminum metal layer and a main deposition step to form a second aluminum metal layer, wherein the pre-deposition step The average process temperature is substantially less than the process average temperature at which the second aluminum metal layer is formed, and in the pre-deposition step of forming the first aluminum metal layer, a fluid such as argon gas or the like which assists heat conduction is not introduced into the back surface of the substrate. The two-stage aluminum metal deposition process can reduce the hole-like defects of the aluminum metal layer and improve the uniformity of the crystal size distribution to increase the reliability of the electrical properties of the transistor element.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

11. . . Base

12. . . Shallow trench isolation

13. . . Dielectric layer

14. . . High dielectric constant gate dielectric layer

15. . . Etch stop layer

16. . . Sacrificial gate material layer

17. . . Cover

18. . . Sacrificial gate structure

19. . . Lightly doped source/drain region

20. . . Side wall

twenty one. . . Source/bungee area

twenty two. . . Contact hole etch stop layer

twenty three. . . Inner dielectric layer

twenty four. . . Opening

25. . . Work function metal layer

26. . . Aluminum metal layer

27. . . Aluminum metal gate

28. . . First aluminum metal layer

29. . . Second aluminum metal layer

30. . . Transistor

31. . . Gate structure

32. . . U-shaped high dielectric constant gate dielectric layer

h, h1, h2. . . thickness

1 to 6 are schematic views showing the fabrication of a transistor having an aluminum metal gate in accordance with a preferred embodiment of the present invention.

Figure 7 is a schematic view of a transistor having an aluminum metal gate in accordance with another preferred embodiment of the present invention.

11. . . Base

12. . . Shallow trench isolation

13. . . Dielectric layer

14. . . High dielectric constant gate dielectric layer

15. . . Etch stop layer

19. . . Lightly doped source/drain region

20. . . Side wall

twenty one. . . Source/bungee area

twenty two. . . Contact hole etch stop layer

twenty three. . . Inner dielectric layer

25. . . Work function metal layer

26. . . Aluminum metal layer

27. . . Aluminum metal gate

28. . . First aluminum metal layer

29. . . Second aluminum metal layer

30. . . Transistor

Claims (26)

A method of fabricating a metal gate includes: providing a substrate; forming a sacrificial gate structure on the substrate; forming an opening in the sacrificial gate structure; and filling an aluminum metal layer in the opening, the step The method includes: performing a pre-deposition step to form a first aluminum metal layer in the opening; and performing a main deposition step to form a second aluminum metal layer on the first aluminum metal layer. The method of fabricating a metal gate according to claim 1, wherein an average process temperature of the pre-deposition step of forming the first aluminum metal layer is substantially smaller than one of the main deposition steps of forming the second aluminum metal layer. Average process temperature. The method of fabricating a metal gate according to claim 1, wherein the pre-deposition step of forming the first aluminum metal layer does not pass through a fluid assisting heat conduction on a back surface of the substrate. The method of fabricating a metal gate according to claim 1, wherein a thickness of one of the first aluminum metal layers is substantially smaller than a thickness of the second aluminum metal layer, and the thickness of the first aluminum metal layer is substantially It is less than one-half the thickness of one of the aluminum metal layers. The method of fabricating a metal gate according to claim 4, wherein the thickness of the first aluminum metal layer is substantially equal to or greater than one eighth of the thickness of the aluminum metal layer. The method of fabricating a metal gate according to claim 4, wherein the thickness of the first aluminum metal layer is substantially equal to or greater than one fifth of the thickness of the aluminum metal layer. The method of fabricating a metal gate according to claim 4, wherein the thickness of the first aluminum metal layer is substantially greater than or equal to one third of the thickness of the aluminum metal layer. A method of fabricating a metal gate according to claim 1, wherein a refractive index of one of the aluminum metal layers is proportional to the thickness of the first aluminum metal layer. The method of fabricating a metal gate according to claim 1, wherein the sacrificial gate structure comprises a high dielectric constant gate dielectric layer and a sacrificial gate material layer, and the high dielectric constant gate dielectric layer Provided between the substrate and the sacrificial gate material layer. A method of fabricating a metal gate as recited in claim 9, wherein the sacrificial gate material layer comprises a polycrystalline germanium material having no undoped or polycrystalline germanium material having an N+ dopant. The method of fabricating a metal gate according to claim 9, wherein the high dielectric constant gate dielectric layer comprises hafnium oxide (HfO ₂ ), hafnium niobate (HfSiO ₄ ), niobium niobate niobate ( HfSiON), alumina (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconia (ZrO ₂ ), barium titanate ( SrTiO ₃ ), zirconium oxynitride (ZrSiO ₄ ), hafnium zirconate (HfZrO ₄ ), antimony oxide (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and group of barium titanate (Ba _x Sr _1-x TiO ₃ , BST). The method of fabricating a metal gate according to claim 9, wherein the sacrificial gate structure further comprises a dielectric layer disposed between the substrate and the high dielectric constant gate dielectric layer. The method of fabricating a metal gate according to claim 12, wherein the dielectric layer comprises cerium oxide, a nitrogen-containing cerium oxide layer or a material having a low dielectric constant. The method of fabricating a metal gate according to claim 9, wherein the sacrificial gate structure further comprises an etch stop layer disposed between the high dielectric constant gate dielectric layer and the sacrificial gate material layer. The method of fabricating a metal gate according to claim 14, wherein the etch stop layer comprises titanium nitride (TiN) or tantalum nitride (TaN). The method of fabricating a metal gate according to claim 1, further comprising forming a source/drain region disposed in the substrate on both sides of the sacrificial gate structure. A transistor having an aluminum metal gate, comprising: a substrate; a high dielectric constant gate dielectric layer disposed on the substrate; an aluminum metal gate, the aluminum metal gate including a work function metal layer and An aluminum metal layer is sequentially disposed on the high dielectric constant gate dielectric layer, wherein the aluminum metal layer comprises a first aluminum metal layer and a second aluminum metal layer; and a source/drain region is disposed In the substrate on both sides of the aluminum metal gate. The transistor having an aluminum metal gate according to claim 17, wherein a thickness of one of the first aluminum metal layers is substantially smaller than a thickness of the second aluminum metal layer, and the thickness of the first aluminum metal layer It is substantially less than one-half the thickness of one of the aluminum metal layers. A transistor having an aluminum metal gate according to claim 17, wherein the thickness of the first aluminum metal layer is substantially equal to or greater than one eighth of the thickness of the aluminum metal layer. The transistor having an aluminum metal gate according to claim 17, wherein the thickness of the first aluminum metal layer is substantially equal to or greater than one fifth of the thickness of the aluminum metal layer. The transistor having an aluminum metal gate according to claim 17, wherein the thickness of the first aluminum metal layer is substantially equal to or greater than one third of the thickness of the aluminum metal layer. A transistor having an aluminum metal gate according to claim 17, wherein a refractive index of one of the aluminum metal layers is proportional to the thickness of the first aluminum metal layer. A transistor having an aluminum metal gate as claimed in claim 17, wherein the transistor is an N-type transistor or a P-type transistor. The transistor of claim 17 having an aluminum metal gate, wherein the source/drain region comprises an epitaxial layer. The transistor having an aluminum metal gate according to claim 17, wherein the high dielectric constant gate dielectric layer comprises a U-shaped high dielectric constant gate dielectric layer or a one-line high dielectric constant gate Dielectric layer. The transistor having an aluminum metal gate according to claim 25, wherein the high dielectric constant gate dielectric layer comprises hafnium oxide (HfO ₂ ), hafnium niobate (HfSiO ₄ ), niobium niobate niobate Compound (HfSiON), alumina (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconia (ZrO ₂ ), titanic acid SrTiO ₃ , ZrSiO ₄ , Zirconium hydride (HfZrO ₄ ), SrBi ₂ Ta ₂ O ₉ , SBT, Lead Zirconate Titanate (PbZr _x Ti _1- A group consisting of _x O ₃ , PZT) and barium titanate (Ba _x Sr _1-x TiO ₃ , BST).