TWI530991B - Semiconductor device having metal gate and manufacturing method thereof - Google Patents

Description

Semiconductor component with metal gate and manufacturing method thereof

The present invention relates to a semiconductor device having a metal gate and a method of fabricating the same, and more particularly to a semiconductor device having a metal gate which can reduce process complexity and a method of fabricating the same.

As the semiconductor component continues to shrink, a work function metal is used to replace the conventional polysilicon as a control electrode for matching a high dielectric constant (high-k) dielectric layer. The function gate metal gate can be divided into two types: front gate (gate first) and back gate (gate last). The latter gate process can avoid source/drain super shallow connection. Surface activation tempering and high-heat budget processes such as metal telluride, and a wider material selection, gradually replaced the front gate process.

In the conventional gate process, a dummy gate or a replacement gate is formed first, and after the fabrication of the general MOS transistor is completed, the dummy/replacement gate is removed. A gate trench is formed, and different metals are filled in the gate trench according to electrical requirements.

It can be seen that the post-gate process can avoid the high-heat budget process such as source/drain ultra-shallow junction activation tempering and metal halide formation. Material selection, but still facing the requirements of integration of complex processes and film formation results.

Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor device having a metal gate to reduce the complexity of the metal gate process and to improve the gate trench fill capability.

The present invention provides a method of fabricating a semiconductor device having a metal gate, the method first providing a substrate having a first semiconductor component and a second semiconductor component, the first semiconductor component including a first gate a trench, and the second semiconductor component includes a second gate trench. Next, a first work function metal layer and an etch stop layer are respectively formed in the first gate trench and the second gate trench. The manufacturing method provided by the present invention further comprises forming a metal layer in the second gate trench, and the metal layer comprises the same material as the first work function metal layer. After forming the metal layer, a filling metal layer is formed in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench.

The present invention further provides a method of fabricating a semiconductor device having a metal gate. The fabrication method first provides a substrate having a first semiconductor component and a second semiconductor component formed on the surface. Forming a first gate trench in the first semiconductor component, and forming a first layer in the first gate trench a metal layer. After forming the first metal layer, forming a second gate trench in the second semiconductor device, and then forming a second metal layer in the first gate trench and the second gate trench, and The two metal layers comprise the same material as the first metal layer. After the second metal layer is formed, a filling metal layer is formed in the first gate trench and the second gate trench.

The invention further provides a semiconductor device having a metal gate, the semiconductor device comprising a substrate, a first metal gate disposed on the substrate, and a second metal gate disposed on the substrate. The first metal gate includes at least one first metal layer, and the second metal gate includes at least one second metal layer. The second metal layer and the first metal layer comprise the same material, and the thickness of the second metal layer is less than or equal to the thickness of the first metal layer.

According to the present invention, a method for fabricating a semiconductor device having a metal gate is formed by forming a filling metal layer and diffusing metal ions in the filling metal layer to form a first work function metal formed in the first gate trench The layer or metal layer is directly converted into a second work function metal layer. Therefore, the fabrication method provided by the present invention can omit complicated steps such as forming different work function metal layers and removing non-essential work function metal layers in different gate processes, thereby simplifying the metal gate process and reducing the process complexity. And improve the gate ditches to fill the results.

Please refer to Figures 1 to 5, and Figures 1 to 5 are the present invention. A schematic diagram of a first preferred embodiment of a method of fabricating a semiconductor device having a metal gate. As shown in FIG. 1, the preferred embodiment first provides a substrate 100, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate. A first semiconductor component 110 and a second semiconductor component 112 are formed on the substrate 100, and a shallow trench isolation (shallow trench) for providing electrical isolation is formed in the substrate 100 between the first semiconductor component 110 and the second semiconductor component 112. Isolation, STI) 102. The first semiconductor component 110 has a first conductivity type, and the second semiconductor component 112 has a second conductivity pattern, and the first conductivity pattern is complementary to the second conductivity pattern. In the preferred embodiment, the first semiconductor component 110 is an n-type semiconductor component; and the second semiconductor component 112 is a p-type semiconductor component.

Please continue to see Figure 1. The first semiconductor device 110 and the second semiconductor device 112 each include a dielectric layer 104, a dummy gate such as a polysilicon layer (not shown), and a patterned hard mask for defining a dummy gate position (Fig. Not shown) is placed over the dielectric layer 104. In addition, the first semiconductor component 110 and the second semiconductor component 112 respectively include a first light doped drain (LDD) 120 and a second LDD 122, a sidewall 124, and a first source/汲The pole 130 and a second source/drain 132. The surface of the first source/drain 130 and the second source/drain 132 respectively comprise a metal telluride (not shown). In addition, in a post-contact salicide process, a metal telluride is formed in a contact opening. after that. On the first semiconductor device 110 and the second semiconductor device 112, a contact etch stop layer (CESL) 140 and an inter-layer dielectric (ILD) layer 142 are sequentially formed. . The fabrication steps and material selection of the above-mentioned components, and even the selective epitaxial growth (SEG) method for forming the source/drain electrodes 130, 132, etc. in the semiconductor industry to provide stress and improve electrical performance are Those skilled in the art are well known and will not be described here.

Please still refer to Figure 1. After forming the CESL 140 and the ILD layer 142, a portion of the ILD layer 142 and the CESL 140 are removed by a planarization process until the patterned hard mask or dummy of the first semiconductor component 110 and the second semiconductor component 112 is exposed. Set the gate. Then, the patterned hard mask and the dummy gate of the first semiconductor element 110 and the second semiconductor element 112 are removed by a suitable etching process, and a first one is formed in the first semiconductor element 110 and the second semiconductor element 112, respectively. The first gate trench 150 and the second gate trench 152 expose the dielectric layer 104. It should be noted that since the preferred embodiment is integrated with the high-k last process, the dielectric layer 104 exposed to the bottom of the gate trench 150/152 can serve as an interface layer ( Interfacial layer). Although the preferred embodiment is integrated with the post gate dielectric layer process, it can also be integrated with the front gate dielectric layer process. Next, a high-k gate dielectric layer 106 is formed in the substrate 100 and the first gate trench 150 and the second gate trench 152. The high-k gate dielectric layer 106 can be a metal oxide layer, such as a rare earth metal oxide layer. The high-k gate dielectric layer 106 can be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and hafnium silicon oxynitride (HfSiON). , aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), oxidation Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), yttrium Oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr) _a group consisting of _1-x TiO ₃ , BST).

Please refer to Figure 2. After the high-k gate dielectric layer 106 is formed, a first titanium nitride (TiN) layer 160 and a tantalum nitride (hereinafter referred to as tantalum nitride) are sequentially formed on the substrate 100. TaN) layer 162, and a second TiN layer 164. The first TiN layer 160, the TaN layer 162, and the second TiN layer 164 may be formed by any suitable process, such as an atomic layer deposition (ALD) process. In addition, the TiN, TaN, and the like disclosed in the preferred embodiment are merely exemplified as constituent elements, and do not represent an actual atomic composition ratio of 1:1. In other words, the atomic composition ratio of the first TiN layer 160 to the second TiN layer 164 can be adjusted, such as Ti _x N _y . As shown in FIG. 2, the first TiN layer 160, the TaN layer 162 and the second TiN layer 164 are formed in the first gate trench 150 and the second gate trench 152, and the second TiN layer 164 is completely covered. A gate drain trench 150 and a second gate trench 152 sidewall and bottom TaN etch stop layer 162. The first TiN layer 160 can serve as a first work function metal layer, and the material is different from the first TiN layer 160 and the TaN layer 162 of the second TiN layer 164 as an etch stop layer. The thickness of the first TiN layer 160 is about 30 to 40 angstroms, but is not limited thereto. The thickness of the TaN layer 162 is about 10 angstroms, but is not limited thereto. The thickness of the second TiN layer 164 is about 20 to 40 angstroms, but is not limited thereto. In addition, it should be noted that the thicknesses of the first TiN layer 160 and the second TiN layer 164 can be adjusted according to a desired work function.

Please refer to Figure 3. Next, a patterned protective layer (not shown) is formed on the substrate 100 to protect the second TiN layer 164 at the second semiconductor element 112. An etching process is then performed to remove the second TiN layer 164 in the first gate trench 150 such that the TaN etch stop layer 162 is exposed to the sidewalls and bottom of the first gate trench 150. In other words, after the etching process, the second TiN layer 164 remains only at the second semiconductor component 112, particularly the sidewalls and bottom of the second gate trench 152. Since the etch process may consume a portion of the TaN etch stop layer 162, the thickness of the TaN etch stop layer 162 at the first semiconductor device 110 is less than the thickness of the TaN etch stop layer 162 at the second semiconductor device 112 after the etch process. Finally, the patterned protective layer can be removed.

Please refer to Figure 4. Next, tied to the first gate trench 150 and the second A fill metal layer 166 is formed in the gate trench 152. The filling metal layer 166 is used to fill the first gate trench 150 and the second gate trench 152, and may select a metal or metal oxide having excellent filling ability and lower resistance, such as aluminum (Al). Titanium aluminide (TiAl) or titanium aluminum oxide (TiAlO), but is not limited thereto. As described above, the TiAl, TiAlO, and the like disclosed in the preferred embodiment are merely exemplified as constituent elements, and do not represent an actual atomic composition ratio of 1:1. It should be noted that, while forming the filling metal layer 166, the aluminum ions contained in the filling metal layer 166 in the first gate trench 150 diffuse into the first gate trench 150 as shown in FIG. The first TiN layer 160 can adjust the work function of the first TiN layer 160 in the first gate trench 150 to about 4.35 electron volts (hereinafter referred to as eV), and even form a titanium aluminum nitride (TiAlN) layer. The work function requirements of an n-type semiconductor device 110 are met. In other words, the first TiN layer 160 in the first gate trench 150 is transformed into a second work function metal layer 168 (shown in FIG. 5) after forming the fill metal layer 166.

Please continue to see Figure 4. In the second gate trench 152, the second TiN layer 164 can serve as a barrier layer. Therefore, the aluminum ions contained in the filling metal layer 166 in the second gate trench 152 can only diffuse to the first layer. The second TiN layer 164 is blocked from the first TiN layer 160. In other words, the second TiN layer 164 in the second gate trench 152 is converted into a TiAlN layer 168 (shown in FIG. 5), and the first TiN layer 160 in the second gate trench 152 can still function as a first work function metal layer and conforming to p-type semiconducting The required work function of body element 112 is 4.85 eV.

Please refer to Figure 5. Finally, a planarization process, such as a CMP process, is performed to remove the excess fill metal layer 166, the second TiN layer 164, the TaN layer 162, the first TiN layer 160, and the high-k gate dielectric layer 106, The fabrication of a first metal gate 170 and a second metal gate 172 is completed. In addition, the present embodiment can also selectively remove the ILD layer 142 and the CESL 140 and the like, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. Since the above CMP process and the like are known to those skilled in the art, they are not described or illustrated herein.

Also, please refer back to Figure 5. According to the manufacturing method of the semiconductor device having the metal gate provided by the preferred embodiment, the first metal gate 170 and the second metal gate 172 each include a TiAlN layer 168 having the same diffusion aluminum ion, but the second metal gate The thickness of the TiAlN layer 168 of the pole 172 is different from the thickness of the TiAlN layer 168 of the first metal gate 170. In addition, the second metal gate 172 further includes a TiN layer 160 having no diffused aluminum ions. Since the TiN layer 160 does not have diffused aluminum ions, the work function of the TiN layer 160 is different from the TiAlN layer 168 having diffused aluminum ions. In other words, the TiAlN layer 168 in the first metal gate 170 serves as a work function metal layer of the first semiconductor device 110; the TiN layer 160 in the second metal gate 172 serves as a work function metal of the second semiconductor device 112. The layer, and the TiAlN layer 168 in the second metal gate 172 is a barrier layer. In addition, the first metal gate 170 and the first The second metal gate 172 further includes a TaN etch stop layer 162 having an etch rate different from that of the TiN layer 160. The TaN etch stop layer 162 in the first metal gate 170 is disposed between the fill metal layer 166 and the TiAlN layer 168; and the etch stop layer 162 in the second metal gate 172 is disposed on the TiN layer 160 and the TiAlN layer. Between 168.

According to the manufacturing method of the semiconductor device having the metal gate provided by the preferred embodiment, the aluminum diffusion mechanism is used to automatically complete the fabrication of the n-type work function metal layer 168 when forming the filling metal layer 166, and in the p-type The work function metal layer 160 is unaffected by the arrangement of the second TiN layer 164 to block aluminum diffusion. It can be seen that the manufacturing method of the semiconductor device having the metal gate provided by the preferred embodiment can reduce the setting and removal of the metal layer, thereby effectively simplifying the metal gate process. Moreover, since the manufacturing method provided by the preferred embodiment can reduce the setting and removal of the metal layer, the filling result of the gate trench can be improved, and the yield of the metal gate process can be improved.

Please refer to FIG. 6 to FIG. 9 . FIG. 6 to FIG. 9 are schematic diagrams showing a second preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention. It should be noted that the same components in the second preferred embodiment as the first preferred embodiment may be made of the same material, and the material selection is not described again. As shown in FIG. 6, the preferred embodiment first provides a substrate 200 having a first semiconductor component 210 and a second semiconductor component 212 formed thereon, and the first semiconductor component 210 and the second semiconductor component. An STI 202 that provides electrical isolation is formed within the substrate 200 between 212. The first semiconductor component 210 has a first conductivity type, and the second semiconductor component 212 has a second conductivity pattern, and the first conductivity pattern is complementary to the second conductivity pattern. In the preferred embodiment, the first semiconductor component 210 is an n-type semiconductor component; and the second semiconductor component 212 is a p-type semiconductor component.

Please continue to see Figure 6. The first semiconductor device 210 and the second semiconductor device 212 each include a dielectric layer 204, a dummy gate such as a polysilicon layer (not shown), and a patterned hard mask for defining a dummy gate position (Fig. Not shown) is disposed over the dielectric layer 204. In addition, the first semiconductor device 210 and the second semiconductor device 212 respectively include a first LDD 220 and a second LDD 222, a sidewall 224, a first source/drain 230, and a second source/drain 232. In addition, the surface of the first source/drain 230 and the second source/drain 232 respectively comprise a metal halide (not shown). On the first semiconductor element 210 and the second semiconductor element 212, a CESL 240 and an ILD layer 242 are sequentially formed. The fabrication steps and material selection of the above components, and even the implementation of the SEG method to form the source/drain electrodes 230, 232, etc. in the semiconductor industry to provide stress and improve electrical performance are well known to those skilled in the art. No longer.

Please still refer to Figure 6. After forming the CESL 240 and the ILD layer 242, a portion of the ILD layer 242 and the CESL 240 are removed by a planarization process until the first semiconductor device 210 and the second semiconductor device 212 are exposed. Case hard mask or dummy gate. Then, the patterned hard mask and the dummy gate of the first semiconductor element 210 and the second semiconductor element 212 are removed by a suitable etching process, and a first one is formed in the first semiconductor element 210 and the second semiconductor element 212, respectively. The first gate trench 250 and the second gate trench 252 expose the dielectric layer 204. The preferred embodiment is also integrated with the back gate dielectric layer process so that the dielectric layer 204 exposed to the bottom of the gate trenches 250/252 can serve as an interface layer. As described above, although the preferred embodiment is integrated with the post gate dielectric layer process, it can also be integrated with the front gate dielectric layer process. Next, a high-k gate dielectric layer 206 is formed in the substrate 200 and the first gate trench 250 and the second gate trench 252. Immediately after the formation of the high-k gate dielectric layer 206, a TaN layer 262 is formed on the substrate 200. The TaN layer 262 covers the bottom and sidewalls of the first gate trench 250 and the second gate trench 252, and has a thickness of about 10 angstroms, but is not limited thereto. After the TaN layer 262 is formed, a first TiN layer 260 is formed on the substrate 200. As shown in FIG. 6, the first TiN layer 260 also covers the sidewalls and the bottom of the first gate trench 250 and the second gate trench 252, and the thickness of the first TiN layer 260 is about 30-40 angstroms, but is not limited thereto. this. The first TiN layer 260 has a work function of about 4.85 eV, and thus can serve as the first work function metal layer of the p-type semiconductor device 212.

Please refer to Figure 7. After the high-k gate dielectric layer 206, the TaN layer 262, and the first TiN layer 260 are sequentially formed, a patterned protective layer (not shown) is formed on the substrate 200 to protect the second semiconductor device 212. The first TiN layer 260 is located. An etching process is then performed to remove the exposed substrate 200. Above, in particular, the first TiN layer 260 at the first semiconductor component 210. In this etching process, the TaN layer 262 serves as an etch stop layer for protecting the underlying high-k gate dielectric layer 206. Therefore, the first TiN layer 260 remains only in the second semiconductor component 212, particularly in the second gate trench 252. The TaN layer 262 is exposed to the sidewalls and bottom of the first gate trench 250 after the etching process. As described above, since the etching process may consume a portion of the TaN etch stop layer 262, the thickness of the TaN etch stop layer 262 at the first semiconductor device 210 is less than the TaN etch stop at the second semiconductor device 212 after the etching process. The thickness of layer 262. Finally, the patterned protective layer can be removed.

Please refer to Figure 8. After the first TiN layer 260 in the first gate trench 250 is removed, a second TiN layer 264 and a fill metal layer 266 are formed on the substrate 200 in sequence. The thickness of the second TiN layer 264 is about 20 to 40 angstroms, but is not limited thereto. As shown in FIG. 8, in the first gate trench 250, the second TiN layer 264 is formed on the TaN etch stop layer 262; but in the second gate trench 252, the second TiN layer 264 is formed on the second gate trench 252. A TiN layer 260. It should be noted that while the filling metal layer 266 is formed, the aluminum ions contained in the filling metal layer 266 in the first gate trench 250 diffuse into the second TiN layer 264 as shown in FIG. The work function of the second TiN layer 264 in the first gate trench 250 is adjusted to about 4.35 eV, and even a TiAlN layer is formed, which conforms to the work function requirement of an n-type semiconductor device 210. In other words, the second TiN layer 264 in the first gate trench 250 is formed to fill The metallization layer 266 is then converted into a second work function metal layer 268 (shown in Figure 9).

Please continue to see Figure 8. In the second gate trench 252, the second TiN layer 264 can serve as a barrier layer, so the aluminum ions contained in the filling metal layer 266 in the second gate trench 252 can only diffuse to the second TiN layer 264. Inside, it is blocked outside the first TiN layer 260. In other words, the first TiN layer 260 in the second gate trench 252 can still serve as the first work function metal layer and conform to the required work function of the p-type semiconductor device 212, ie 4.85 eV.

Please refer to Figure 9. Finally, a planarization process, such as a CMP process, is performed to remove excess fill metal layer 266, second TiN layer 264, TaN layer 262, first TiN layer 260, and high-k gate dielectric layer 206, The fabrication of a first metal gate 270 and a second metal gate 272 is completed. In addition, the present embodiment can also selectively remove the ILD layer 242 and the CESL 240 and the like, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. Since the above CMP process and the like are known to those skilled in the art, they are not described or illustrated herein.

In addition, please refer to Figure 9 again. According to the manufacturing method of the semiconductor device having the metal gate provided by the preferred embodiment, the first metal gate 270 and the second metal gate 272 each include a TiAlN layer 268 having the same diffused aluminum ions, and the second metal gate The thickness of the TiAlN layer 268 of the pole 272 is approximately equal to The thickness of the TiAlN layer 268 of a metal gate 270. In addition, the second metal gate 272 further includes a TiN layer 260 having no diffused aluminum ions. Since the TiN layer 260 does not have diffused aluminum ions, the work function of the TiN layer 260 is different from the TiAlN layer 268 having diffused aluminum ions. In other words, the TiAlN layer 268 in the first metal gate 270 serves as a work function metal layer of the first semiconductor device 210; the TiN layer 260 in the second metal gate 272 serves as a work function metal of the second semiconductor device 212. The layer, and the TiAlN layer 268 in the second metal gate 272 is a barrier layer. In addition, the first metal gate 270 and the second metal gate 272 further include a TaN etch stop layer 262 having an etch rate different from that of the TiN layer 260. The etch stop layer 262 in the first metal gate 270 is disposed between the high-k gate dielectric layer 206 and the TiAlN layer 268; and the etch stop layer 262 in the second metal gate 272 is disposed at the high- Between the gate dielectric layer 206 and the TiN layer 260.

According to the manufacturing method of the semiconductor device having the metal gate provided by the preferred embodiment, the fabrication of the n-type work function metal layer 268 is automatically completed when the filling metal layer 266 is formed by using the mechanism of aluminum diffusion, and the p-type is formed. The work function metal layer 260 is unaffected by the arrangement of the second TiN layer 264 to block aluminum diffusion. It can be seen that the manufacturing method of the semiconductor device having the metal gate provided by the preferred embodiment can reduce the setting and removal of the metal layer, thereby effectively simplifying the metal gate process. Moreover, since the manufacturing method provided by the preferred embodiment can reduce the setting and removal of the metal layer, the filling result of the gate trench can be improved, and the yield of the metal gate process can be improved.

Please refer to FIG. 10 to FIG. 13 . FIG. 10 to FIG. 13 are schematic diagrams showing a third preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention. It should be noted that, in the third preferred embodiment, the same components as those of the foregoing preferred embodiment may be made of the same material, so that the material selection is not described again. As shown in FIG. 10, the preferred embodiment first provides a substrate 300 having a first semiconductor component 310 and a second semiconductor component 312 formed thereon, and between the first semiconductor component 310 and the second semiconductor component 312. The substrate 300 is formed with an STI 302 that provides electrical isolation. The first semiconductor component 310 has a first conductivity type, and the second semiconductor component 312 has a second conductivity pattern, and the first conductivity pattern is complementary to the second conductivity pattern. In the preferred embodiment, the first semiconductor component 310 is a p-type semiconductor component; and the second semiconductor component 312 is an n-type semiconductor component.

Please continue to see Figure 10. The first semiconductor component 310 and the second semiconductor component 312 each include a dielectric layer 306, a selectively formed etch stop layer (not shown), a dummy gate such as a polysilicon layer 303, and a dummy dummy A patterned hard mask 305 at the gate position. It should be noted that the preferred embodiment can be integrated with the back gate dielectric layer process or integrated with the front gate dielectric layer process. When the preferred embodiment is integrated with the front gate dielectric layer process, the dielectric layer 306 includes a high-k gate dielectric layer. In addition, the first semiconductor component 310 and the second semiconductor component 312 respectively include a first LDD 320 and a second LDD 322, a sidewall 324, and a first source/drain 330 and a first Two source/bungee 332. In addition, the surface of the first source/drain 330 and the second source/drain 332 respectively comprise a metal telluride (not shown). On the first semiconductor element 310 and the second semiconductor element 312, a CESL 340 and an ILD layer 342 are sequentially formed. The fabrication steps and material selection of the above-mentioned components, and even the implementation of the SEG method to form the source/drain electrodes 330, 332 and the like in the semiconductor industry to provide stress and improve electrical performance are well known to those skilled in the art. No longer.

Please still refer to Figure 10. After forming the CESL 340 and ILD layer 342, portions of the ILD layer 342 and CESL 340 are removed by a planarization process until the patterned hard mask 305 of the first semiconductor component 310 and the second semiconductor component 312 is exposed. Forming a patterned protective layer (not shown) at the second semiconductor device 312, and removing the patterned hard mask and the dummy gate of the first semiconductor device 310 by a suitable etching process, and first A first gate trench 350 is formed in the semiconductor device 310 and exposes a high-k gate dielectric layer 306. After the first gate trench 350 is formed, a first TiN layer 360 is formed on the substrate 300. The first TiN layer 360 covers the sidewalls and the bottom of the first gate trench 350 and has a thickness of about 30 to 40 angstroms, but is not limited thereto.

Please refer to Figure 11. After forming the first TiN layer 360, a patterned protective layer (not shown) is formed on the substrate 300 to protect the first TiN layer 360 in the first gate trench 350, and then the second semiconductor component is removed. 312 The patterned hard mask 305 and the dummy gate 303 are patterned, and a second gate trench 352 is formed in the second semiconductor component 312. As shown in FIG. 11, the high-k gate dielectric layer 306 is exposed to the bottom of the second gate trench 352. After forming the second gate trench 352, the aforementioned patterned protective layer is removed.

Please refer to Figure 12. Next, a second TiN layer 364 and a filling metal layer 366 are sequentially formed on the substrate 300. The thickness of the second TiN layer 364 is about 20 to 40 angstroms, but is not limited thereto. As shown in FIG. 12, in the first gate trench 350, the second TiN layer 364 is formed on the first TiN layer 360, and since the first TiN layer 360 and the second TiN layer 364 comprise the same material, The first TiN layer 360 and the second TiN layer 364 in the first semiconductor component 310 can be considered as a thick TiN layer. However, in the second gate trench 352, only the second TiN layer 364 is formed in the second gate trench 352 and directly contacts the high-k gate dielectric layer 306. In addition, it is more remarkable that while the filling metal layer 366 is formed, the aluminum ions contained in the filling metal layer 366 in the second gate trench 352 diffuse into the second TiN layer 364 as shown in FIG. Therefore, the work function of the second TiN layer 364 in the second semiconductor element 312 can be adjusted to about 4.35 eV, and even a TiAlN layer can be formed, which conforms to the work function requirement of the n-type semiconductor element 312. In other words, the second TiN layer 364 in the second gate trench 352 is transformed into a second work function metal layer 368 (shown in FIG. 13) after forming the fill metal layer 366.

Please continue to see Figure 12. And in the first gate trench 350, the second TiN The layer 364 can serve as a barrier layer, so that the aluminum ions contained in the fill metal layer 366 in the first gate trench 350 can only diffuse into the second TiN layer 364 and are blocked from the first TiN layer 360. . In other words, the first TiN layer 360 in the first gate trench 350 can still serve as the first work function metal layer and conform to the required work function of the p-type semiconductor device 310, ie 4.85 eV.

Please refer to Figure 13. Finally, a planarization process, such as a CMP process, is performed to remove the excess fill metal layer 366, the second TiN layer 364 and the first TiN layer 360, and complete a first metal gate 370 and a second metal. Production of gate 372. In addition, the present embodiment can also selectively remove the ILD layer 342 and the CESL 340, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. Since the above CMP process and the like are known to those skilled in the art, they are not described or illustrated herein.

Please refer to Figure 13 again. According to the manufacturing method of the semiconductor device having the metal gate provided by the preferred embodiment, the first metal gate 370 and the second metal gate 372 each include a TiAlN layer 368 having the same diffusion aluminum ion, and the second metal gate The thickness of the TiAlN layer 368 of the pole 372 is equal to the thickness of the TiAlN layer 368 of the first metal gate 370. In addition, the first metal gate 370 further includes a TiN layer 360 that does not have diffused aluminum ions. Since the TiN layer 360 does not have diffused aluminum ions, the work function of the TiN layer 360 is different from the TiAlN layer 368 having diffused aluminum ions. In other words, within the second metal gate 372 The TiAlN layer 368 serves as a work function metal layer of the second semiconductor element 310; the TiN layer 360 in the first metal gate 370 serves as a work function metal layer of the first semiconductor element 312, and TiAlN in the first metal gate 370 Layer 368 is a barrier layer.

According to the manufacturing method of the semiconductor device having the metal gate provided by the preferred embodiment, the aluminum diffusion mechanism is used to automatically complete the fabrication of the n-type work function metal layer 368 when forming the filling metal layer 366, and in the p-type The work function metal layer 360 is unaffected by the arrangement of the second TiN layer 364 to block aluminum diffusion. In addition, by separately forming the first gate trench 350 and the second gate trench 352, the formation of the TaN etch stop layer can be further eliminated. It can be seen that the manufacturing method of the semiconductor device having the metal gate provided by the preferred embodiment can reduce the setting and removal of the metal layer, thereby effectively simplifying the metal gate process. Moreover, since the manufacturing method provided by the preferred embodiment can reduce the setting and removal of the metal layer, the filling result of the gate trench can be improved, and the yield of the metal gate process can be improved.

In summary, the method for fabricating a semiconductor device having a metal gate according to the present invention is formed in the first gate trench by the formation of a filling metal layer and the diffusion of metal ions in the filling metal layer. The first work function metal layer or metal layer is converted into a second work function metal layer. Therefore, the manufacturing method provided by the present invention can omit complicated steps such as forming different work function metal layers and removing non-essential work function metal layers in different gate processes. Simplify the metal gate process and increase the gate trench fill results.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200, 300‧‧‧ base

102, 202, 302‧‧‧ shallow trench isolation

303‧‧‧Polysilicon layer

104, 204‧‧‧ dielectric layer

305‧‧‧ patterned hard mask

106, 206, 306‧‧‧High dielectric constant gate dielectric layer

110, 210, 310‧‧‧ first semiconductor components

112, 212, 312‧‧‧second semiconductor components

120, 220, 320‧‧‧ first lightly doped bungee

122, 222, 322‧‧‧ second lightly doped bungee

124, 224, 324‧‧‧ side wall

130, 230, 330‧‧‧First source/bungee

132, 232, 332‧‧‧Second source/bungee

140, 240, 340‧‧‧ contact hole etch stop layer

142, 242, 342‧‧‧ inner dielectric layer

150, 250, 350‧‧‧ first gate ditches

152, 252, 352‧‧‧ second gate ditches

160, 260, 360‧‧‧ first titanium nitride layer

162, 262‧‧‧ tantalum nitride layer

164, 264, 364‧‧‧ second titanium nitride layer

166, 266, 366‧‧‧ fill metal layers

168, 268, 368‧‧‧ aluminum nitride titanium layer

170, 270, 370‧‧‧ first metal gate

172, 272, 372‧‧‧ second metal gate

1 to 5 are schematic views showing a first preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention.

6 to 9 are schematic views showing a second preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention.

10 to 13 are schematic views showing a third preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention.

100‧‧‧Base

102‧‧‧Shallow trench isolation

104‧‧‧ dielectric layer

106‧‧‧High dielectric constant gate dielectric layer

110‧‧‧First semiconductor component

112‧‧‧Second semiconductor component

120‧‧‧First lightly doped bungee

122‧‧‧Second lightly doped bungee

124‧‧‧ Sidewall

130‧‧‧First source/bungee

132‧‧‧Second source/bungee

140‧‧‧Contact hole etch stop layer

142‧‧‧ Inner dielectric layer

150‧‧‧First Gate Ditch

152‧‧‧Second gate ditches

160‧‧‧First Titanium Nitride Layer

162‧‧‧ layer of tantalum nitride

164‧‧‧Second titanium nitride layer

166‧‧‧Filled metal layer

Claims (18)

A method for fabricating a semiconductor device having a metal gate includes: providing a substrate, a surface of the substrate is formed with a first semiconductor component and a second semiconductor component, the first semiconductor component includes a first gate trench, and the The second semiconductor device includes a second gate trench; a first work function metal layer is formed in the first gate trench and the second gate trench; and the first gate trench and the second gate Forming an etch stop layer in the trench; forming a metal layer in the first gate trench and the second gate trench, and the metal layer comprises the same material as the first work function metal layer; A gate metal layer is formed in the gate trench and the second gate trench to form a second work function metal layer in the first gate trench and the second gate trench respectively. The manufacturing method of claim 1, further comprising forming a high dielectric constant (high-k) gate dielectric in the first gate trench and the second gate trench respectively. The step of layering is performed prior to forming the first work function metal layer. The manufacturing method of claim 1, wherein the etch stop layer is formed after the first work function metal layer and before the metal layer. The manufacturing method of claim 3, wherein the step of forming the metal layer in the first gate trench and the second gate trench further comprises: forming the metal layer on the substrate, and the metal a layer covering the bottom and sidewalls of the first gate trench and the second gate trench and the etch stop layer; and removing the metal layer in the first gate trench. The manufacturing method of claim 4, wherein the first work function metal layer in the first gate trench is transformed into the second work function metal layer after forming the filling metal layer. The manufacturing method of claim 1, wherein the etch stop layer is formed before the first work function metal layer. The manufacturing method of claim 6, further comprising the step of removing the first work function metal layer in the first gate trench. The manufacturing method of claim 7, wherein the metal layer is formed on the etch stop layer in the first gate trench. The manufacturing method of claim 8, wherein the metal layer in the first gate trench is converted into the second work function metal layer after forming the filling metal layer. A method for fabricating a semiconductor device having a metal gate includes: providing a substrate having a first semiconductor component and a second semiconductor component; and forming a first gate trench in the first semiconductor component; Forming a first metal layer in the first gate trench; forming a second gate trench in the second semiconductor device; forming a second metal in the first gate trench and the second gate trench a layer, and the second metal layer and the first metal layer comprise the same material; and forming a filling metal layer in the first gate trench and the second gate trench to convert the first gate trench and The second metal layer in the second gate trench forms a second work function metal layer. The manufacturing method of claim 10, wherein the first metal layer in the first gate trench is used as a first work function metal layer. A semiconductor device having a metal gate includes: a substrate; a first metal gate disposed on the substrate, the first metal gate comprising a high dielectric constant gate dielectric layer, a first metal a layer and a filling metal layer; and a second metal gate disposed on the substrate, the second metal gate comprising the high dielectric constant gate dielectric layer, a second metal layer, and a third metal layer And the filler metal layer, wherein the second metal layer and the first metal layer are Filling the metal layer to transform and comprising the same material and work function, wherein the work function of the third metal layer is different from the work function of the first metal layer and the second metal layer, and the thickness of the second metal layer is less than or equal to The thickness of the first metal layer. The semiconductor device of claim 12, wherein the first metal gate and the second metal gate each comprise an etch stop layer, and the etch stop layer has an etch rate different from the first metal layer The etching rate of the second metal layer and the third metal layer. The semiconductor device of claim 13, wherein the etch stop layer in the first metal gate is disposed between the fill metal layer and the first metal layer. The semiconductor device of claim 14, wherein the etch stop layer in the second metal gate is disposed between the second metal layer and the third metal layer. The semiconductor device of claim 13, wherein the etch stop layer in the first metal gate is disposed between the high dielectric constant gate dielectric layer and the first metal layer. The semiconductor component according to claim 16, wherein the first The etch stop layer in the two metal gates is disposed between the high dielectric constant gate dielectric layer and the third metal layer. The semiconductor device of claim 13, wherein the first metal layer comprises titanium aluminum nitride (TiAlN), the second metal layer comprises titanium aluminum nitride, and the third metal layer comprises titanium nitride, and The etch stop layer comprises tantalum nitride.