TWI571981B - Power semiconductor device with small size patch footprint and preparation method - Google Patents

Description

Power semiconductor device with small size patch footprint and preparation method

The present invention relates generally to power semiconductor packages, and more particularly to designing a power semiconductor having a small-sized patch footprint and a method of fabricating the same.

In power transistor applications, the overall size and heat dissipation of the device are two important parameters. The heat dissipation performance of the device is usually improved by exposing a part of the electrodes of the transistor, but the implementation process is often difficult to control and the heat dissipation effect is not good. In some switching circuits, such as synchronous buck converters, half bridge converters, and inverters, two power MOSFETs are required to switch in a complementary manner.

As shown in FIG. 1A, a stacked dual MOSFET package is disclosed in US Pat. No. 7,485,954 B2. The integrated circuit package includes a high side MOSFET die 230 coupled to the first conductive tab 210 such that the drain of the high side MOSFET die 230 is electrically coupled to the first conductive tab 210. A second conductive tab 243 is electrically coupled to the source of the high side MOSFET die 230 in a multi-layer relationship. A low side MOSFET die 250, coupled to the second conductive tab 243, electrically couples the drain of the low side MOSFET die 250 to the second conductive tab 243. The high-side MOSFET die 230, the low-side MOSFET die 250, and the first conductive via 210 and the second conductive via 243 are stacked such that the second conductive via 243 simultaneously contacts the high-side MOSFET die 230 and the low-side MOSFET die. Each of the particles 250 has an electrode and electrically charges the top surface of the high side MOSFET die 230 The bottom electrode of the pole and low side MOSFET die 250 is connected to a plane that is coplanar with the bottom surface of the first conductive tab 210.

Further, as shown in FIG. 1B, a semiconductor device in which a high-side and a low-side wafer is jointly packaged and a method of fabricating the same are disclosed, in which the low-side wafer 200 and the high-side wafer 300 are respectively adhered to both sides of the conductive lead frame 100. The bottom of the low-side wafer 200 is electrically connected to the top surface of the carrier substrate 110, and the top source of the high-side wafer 300 is electrically connected to the bottom surface of the carrier substrate 110 through corresponding solder balls 311. The top surface electrode and the bottom surface electrode of the low side wafer 200 are both connected to a plane coplanar with the bottom surface electrode of the high side wafer 300 through an electrical connection conductor. In the invention, since the low-side wafer 200, the slide substrate 110 of the lead frame 100, and the high-side wafer 300 are three-dimensionally arranged, the size of the entire device can be reduced; after the three are molded, the metal covered on the back side of the high-side wafer 300 The layer or conductive metal patch 320 exposes the package 400 disposed on the back side of the semiconductor device, thereby effectively improving the heat dissipation performance of the device.

From the prior art of FIG. 1A to FIG. 1B, such a layout does not optimize the heat dissipation, and in particular, the device itself occupies a relatively large imprint area, such as the height and plane dimensions of the pins or metal sheets. The device occupies a large area on the PCB circuit board for the patch, and the integration of the PCB cannot be improved to reduce the overall area of the PCB, resulting in an excessively large terminal device incorporating the devices.

The present invention discloses a power semiconductor device comprising: a pedestal; and first and second wafers respectively adhered to the front and back sides of the pedestal; one or more interconnecting sheets disposed on the front surface of the first wafer and One or more interconnecting sheets on the front side of the two wafers; a molding body covering the first and second wafers, and the pedestal and the interconnecting sheets, which are coated at least for each of the interconnecting sheets A side edge surface is exposed from one of the side edges of the molding body.

In the above power semiconductor device, a side edge surface of the susceptor is coplanar with the side edge surface of each of the interconnecting sheets exposed to the molding body, and is also exposed from the side edge surface of the molding body for exposing the side edge surface of the interconnecting sheet. .

In the above power semiconductor device, the susceptor is covered by the molded body without the side edge surface being exposed.

In the above power semiconductor device, a top surface of at least one of the interconnecting sheets disposed on the front surface of the first wafer is exposed from the top surface of the molding body.

In the above power semiconductor device, the top surface of each of the interconnection sheets provided on the front surface of the first wafer is covered with a molding body.

In the above power semiconductor device, a top surface of at least one of the interconnecting sheets disposed on the front surface of the second wafer is exposed from the bottom surface of the molding body.

In the above power semiconductor device, the top surface of each of the interconnection sheets provided on the front surface of the second wafer is covered with a molding body.

In the above power semiconductor device, interconnecting sheets are respectively adhered to respective electrodes on the front surfaces of the first and second wafers, and electrodes on the back surfaces of the first and second wafers are respectively adhered to the front and back surfaces of the susceptor by conductive materials.

In the above power semiconductor device, the thickness between the main and sub-interconnect sheets provided on the two electrodes on the front surface of each of the first or second wafers is not equal, and the main interconnect sheet is substantially rectangular and has a slit formed by one corner portion thereof. An L-shape is formed, and the sub-interconnect sheet is disposed in the slit, and the thickness of the main interconnect sheet is greater than the thickness of the sub-interconnect sheet.

The power semiconductor device is disposed on a top surface of the main interconnecting film on the front surface of the first wafer Exposed from the top surface of the molding body, the top surface of the main interconnecting sheet disposed on the front surface of the second wafer is exposed from the bottom surface of the molding body; and the top surface of the main interconnecting sheet is pasted with an L shape matching the shape of the main interconnecting sheet The heat sink is arranged to coincide with the main interconnecting piece, and a side edge perpendicular to the heat sink is extended on one side edge of the heat sink, and the side edge of the heat sink is aligned with the side edge surface of the outer surface of the plastic sealing exposed piece.

The present invention also provides a method of fabricating a power semiconductor device, comprising the steps of: providing a first lead frame having a plurality of pedestals; attaching a first wafer to the front surface of each pedestal, and flipping the first lead frame after each a second wafer is adhered to the back of the base; a second lead frame provided with a plurality of interconnecting sheets is mounted on the plurality of first wafers so as to be aligned with each other on each of the electrodes on the front surface of each of the first wafers a third lead frame provided with a plurality of interconnecting sheets mounted on the plurality of second wafers for aligning and attaching one of the interconnecting sheets on each of the electrodes on the front surface of each of the second wafers; performing a molding process using the plastic seal Covering the first, second and third lead frames, and coating each of the first and second wafers; cutting a stack between adjacent pedestals, the stack comprising first, second and third a lead frame and a molding compound; each of the pedestals and the first and second wafers adhered thereon are covered by a molding body cut by a molding compound, and the molding body is further coated on the pedestal One or more of the front side of a wafer Interconnecting the sheets and coating disposed on the second front surface of the base wafer or a plurality of interconnected pieces, so that one side edge face of each sheet to be interconnected are exposed from the cut side edge surface of a plastic body.

In the above method, the electrodes on the back surfaces of the first and second wafers are respectively adhered to the front and back sides of the susceptor by the conductive materials.

In the above method, each side edge surface of the interconnecting piece on the first wafer on each of the pedestals is on the same common side as the one side rim surface of the pedestal, and the interconnecting piece on the second wafer on the pedestal Each of the side edge faces is also located within the common face; the laminate is cut along the common face, shaped Forming a cutting side edge surface of the plastic sealing body such that the side edge surface of the base in the common surface, and the side edge surface of any one of the interconnecting sheets in the common surface, one of the molding bodies obtained by cutting along the common surface The side edges are bare.

The above method is characterized in that each side edge surface of the interconnecting piece on the first wafer on each pedestal is on the same common surface, and one side edge surface of each of the interconnecting pieces on the second wafer on the pedestal is also Located on the common surface; cutting the laminate along the common surface to form a cut side edge surface of the molding body, such that the side edge surfaces of any one of the interconnecting sheets in the common surface are formed by cutting along the common surface The side of the side is bare.

In the above method, the molding material in the molding process covers the top surface of each of the interconnecting sheets, and after cutting to form the plastic sealing body, the top surface of each of the interconnecting sheets is covered by the molding body.

In the above method, the molding compound in the molding process exposes a top surface of at least one of the interconnecting sheets disposed on the front surface of the first wafer from the molding compound, and after cutting to form the molding body, one of the at least one interconnecting sheet disposed on the front surface of the first wafer The top surface is exposed from the top surface of the molded body.

In the above method, the molding compound in the molding process exposes a top surface of at least one of the interconnecting sheets disposed on the front surface of the second wafer from the molding compound, and after cutting to form the molding body, one of the at least one interconnecting sheet disposed on the front surface of the second wafer The top surface is exposed from the bottom surface of the molded body.

In the above method, the thickness between the main and sub-interconnecting sheets on the two electrodes of the front surface of each of the first or second wafers is unequal, and the main interconnecting sheet is substantially rectangular and forms an L-shape by the opening of one corner portion thereof. The secondary interconnecting sheet is disposed in the slit, and the thickness of the primary interconnecting sheet is greater than the thickness of the secondary interconnecting sheet.

In the above power semiconductor device, the top surface of the main interconnecting sheet on the front surface of the first wafer is exposed from the top surface of the molding body, and the top surface of the main interconnecting sheet on the front surface of the second wafer is disposed from the bottom of the molding body The surface is exposed; and an L-shaped heat sink corresponding to the shape of the main interconnect sheet is adhered on the top surface of each main interconnect sheet so as to coincide with the main interconnect sheet and extend on one side edge of the heat sink A side flap perpendicular to the heat sink is disposed, and the side edge of the heat sink is aligned with the side edge surface of the molded body for exposing the interconnect sheet.

The present invention provides a method of fabricating another power semiconductor device, comprising the steps of: providing a second lead frame having a plurality of interconnecting sheets, flipping the first wafer on the second lead frame, on the front side of each of the first wafers Attaching an interconnecting piece to each of the electrodes; mounting a first lead frame having a plurality of pedestals on the plurality of first dies to adhere the electrodes on the back surface of each of the first wafers to a pedestal a back surface; a second wafer is attached to the front surface of each of the bases; and a third lead frame provided with a plurality of interconnecting sheets is mounted on the plurality of second wafers so as to be on the respective electrodes on the front surface of each of the second wafers Aligning and attaching an interconnecting sheet; performing a laminating process, coating the first, second and third lead frames with a molding compound, and coating each of the first and second wafers; cutting the stack between adjacent pedestals The laminate includes first, second, and third lead frames and a molding compound; each of the pedestals and the first and second wafers adhered thereto are covered by a molding body cut by a molding compound. , the plastic body is also covered One or more interconnecting sheets on the front surface of the first wafer on the pedestal and one or more interconnecting sheets covering the front surface of the second wafer on the pedestal, such that one side edge surface of each interconnecting sheet is from the plastic sealing body Exposed in a cut side edge.

In the above method, each of the side edges of the interconnecting sheets on the first wafer on each of the pedestals is on the same common side as the side rim of the pedestal, and the interconnecting sheets on the second wafer on the pedestal are respectively a side edge face is also located in the common face; the laminate is cut along the common face to form a cut side edge face of the molded body, such that the base is in the side face of the common face, and any one of the interconnect pieces is in common The side surface of the in-plane, the side of the molded body obtained by cutting along the common surface The face is bare.

In the above method, one side edge surface of each of the interconnecting sheets on the first wafer on each pedestal is on the same common surface, and one side edge surface of each of the interconnecting sheets on the second wafer on the susceptor is also located on the common surface. Cutting the laminate along the common surface to form a cutting side edge surface of the molding body such that the side edge surfaces of any one of the interconnecting sheets in the common surface are from one side edge of the molding body obtained by cutting along the common surface Exposed in the face.

100, 400‧‧‧ lead frame

101‧‧‧Base

101', 301', 401'‧‧‧ side margin

105, 305, 405‧‧‧ positioning holes

110‧‧‧Slide base

200‧‧‧Low side wafer

201, 202‧‧‧ wafer

210, 243‧‧‧ Conductive tabs

230, HS FET‧‧‧ high-side MOSFET die

250, LS FET‧‧‧Low-side MOSFET die

300‧‧‧High Side Wafer

301, 401‧‧‧ Interconnected film unit

311‧‧‧ solder balls

320‧‧‧metal layer or conductive metal patch

500‧‧‧plastic body

500A‧‧‧ top surface

500B‧‧‧ bottom

500C‧‧‧lateral side

501‧‧‧ molding compound

508‧‧ ‧ public side

554‧‧‧ cutting line

555‧‧‧Power semiconductor device

600, PCB‧‧‧ circuit board

601, 603, 604‧‧ ‧ pads

700a‧‧ ‧ heat sink

700b‧‧‧Flanking

700c‧‧‧lateral edge

MOSFET‧‧‧Gold Oxygen Half Field Effect Crystal

Features and advantages of the present invention will become apparent after reading the following detailed description and reference to the accompanying drawings. FIG. 1A through FIG. 1B are power semiconductor packages related to the background art. 2A to 2I are diagrams showing the flow of the steps of preparing a patch with a side edge of the device.

Figures 3A through 3C show the manner in which the power device is mounted to the PCB board. 4A to 4B are power semiconductor devices with heat sinks.

5A to 5B are embodiments in which the susceptor is not exposed from the molded body.

6A to 6B are views showing an embodiment in which the top surface of the interconnect sheet is not exposed from the molded body.

7A to 7D are flowcharts showing another process for preparing a power device different from the processes of FIGS. 2A to 2I.

In FIG. 2A, the lead frame 100 includes a plurality of metal bases 101, and a plurality of positioning holes 105 are disposed at the periphery of the lead frame 100 (the number or the orientation is merely exemplary, Other places in the wire frame 100 can also be arranged with some positioning holes not shown. The base 101 is generally a square flat structure having opposing front and back faces. Since the connection of the susceptor 101 to the bezel or the support strip of the lead frame 100 by a plurality of connecting ribs has been well known to those skilled in the art, the specific structure of the lead frame 100 and the susceptor 101 will not be further described. In order to distinguish from other subsequent lead frames, the lead frame 100 is defined as a first lead frame.

In FIG. 2B, based on the existing patch technology, for example, a plurality of first wafers 201 are pasted one by one by using a conductive adhesive material (such as solder paste, conductive silver paste, etc.) or by eutectic soldering or the like. On the plurality of pedestals 101, the first wafer 201 is adhered to the front surface of the susceptor 101 at this time. The first wafer 201 is a vertical power MOSFET having electrodes on its front side and electrodes on the back side. Current flows from the front side to the back side or vice versa. The specific structure of the first wafer 201 will be described in detail later. The back side of the first wafer 201 is adhered to the front surface of the susceptor 101, whereby the electrodes on the back surface of the first wafer 201 can be electrically connected to the pedestal 101. Note that in the patching step of the first wafer 201, the lead frame 100 and each of the pedestals 101 are face up

In Fig. 2C, the lead frame 100 is flipped so that the back surface of the lead frame 100 faces upward and faces downward, and each of the susceptors 101 and the associated first wafer 201 are also synchronously flipped. Then, the plurality of second wafers 202 are also adhered one by one to the plurality of susceptors 101, and the second wafer 202 is adhered to the back surface of the susceptor 101. The second wafer 202 is also a vertical power MOSFET having electrodes on its front side and electrodes on the back side. Current flows from the front side to the back side or vice versa. The structure of the second wafer 202 will be described in detail later. The back side of the second wafer 202 is adhered to the back surface of the susceptor 101, whereby the electrodes on the back surface of the second wafer 202 can be electrically connected to the pedestal 101. In this way, a first wafer 201 and a second wafer 202 are disposed on the front and back sides of each of the pedestals 101.

For a more detailed understanding of the first wafer 201, the second wafer 202, and the susceptor 101 In relation to the relationship, the second wafer 201 and the first wafer 201 and the second wafer 202 adhered to the front and back sides of the second substrate are taken as an example, but it is emphasized that this is only for visual observation. Actually, no cutting step is performed on the lead frame 100. Referring to FIG. 2D-1, the front surface of the first wafer 201 is provided with an electrode 201a and an electrode 201b, and the electrodes on the back surface of the first wafer 201 are not shown. Although the second wafer 202 is blocked by the susceptor 101 of the second D-1, the second D-2 shows the electrode 202a and the electrode 202b disposed on the front surface of the second wafer 202, and the electrode on the back surface of the second wafer 202 is noted. Not shown.

In FIG. 2E-1, a lead frame 300 is provided. The lead frame 300 includes a plurality of interconnecting sheet units 301, each of which includes one or more interconnecting sheets spaced apart from each other, for example, in one In the embodiment, the interconnecting chip unit 301 includes one interconnecting piece 301a and another interconnecting piece 301b. The interconnecting piece 301a having a larger size is defined as a main interconnecting piece, and the interconnecting piece 301b having a smaller size is defined as a secondary interconnecting piece. The interconnecting piece 301a is substantially rectangular and formed into an L shape by a slit formed at one corner thereof, and the interconnecting piece is formed. 301b is disposed within the slit such that they fit each other to occupy the smallest overall size. Since the manner in which the interconnecting pieces 301a, 301b are connected to the bezel or the support strip of the lead frame 300 by a plurality of connecting ribs is well known to those skilled in the art, the specific structure of the lead frame 300 and the interconnecting sheet unit 301 will not be further described. In order to distinguish from other lead frames, the lead frame 300 is defined as a second lead frame, and a positioning hole 305 is provided at the frame of the lead frame 300.

In FIG. 2E-2, a lead frame 400 having a structurally high similarity to the lead frame 300 is provided. The lead frame 400 includes a plurality of interconnecting chip units 401, each of which includes one or more mutual Separate interconnected sheets, for example, in one embodiment, interconnect sheet unit 401 includes interconnect sheet 401a and interconnect sheet 401b. Defining a larger size interconnect piece 401a is The main interconnecting piece, the interconnecting piece 401b having a smaller size is a sub-interconnecting piece, the interconnecting piece 401a is substantially rectangular and formed into an L shape by a slit having a corner portion thereof, and the interconnecting piece 401b is disposed in the slit, so that the interconnecting piece 401b is disposed in the slit They fit each other and occupy the smallest overall size. The lead frame 400 is defined as a third lead frame, and a positioning hole 405 is provided at the frame of the lead frame 400.

In the 2Fth diagram, the adhesion mounting step of the lead frame 300 and the lead frame 400 is performed. The second lead frame 300 having a plurality of interconnecting sheets is mounted on the plurality of first wafers 201, and in fact, one interconnecting sheet unit 301 is mounted mainly on each of the first wafers 201. In order to adhere an interconnecting piece 301a to the electrode 201a on the front surface of the first wafer 201, an interconnecting piece 301b is adhered to the electrode 201b on the front surface of the first wafer 201. The bottom surface side of the second lead frame 300 faces the first wafer 201 or the lead frame 100, but the opposite top surface side faces away from the first wafer 201 or the lead frame 100.

At the same time, the third lead frame 401 having a plurality of interconnecting sheets is mounted on the plurality of second wafers 202, and an interconnecting sheet unit 401 is mainly mounted on each of the second wafers 202. In order to adhere an interconnecting piece 401a to the electrode 202a on the front surface of the second wafer 202, an interconnecting piece 401b is adhered to the electrode 202b on the front surface of the second wafer 202. The bottom surface side of the third lead frame 400 faces the second wafer 202 or the lead frame 100, but the opposite top surface side faces away from the second wafer 202 or the lead frame 100.

In some embodiments, in the step of mounting the lead frames 300, 400, the lead frame 100 of FIG. 2C can be flipped again (to face up), and after the lead frame 300 is mounted, the lead frame 100 is flipped again (to the back). Up), then the lead frame 400 is installed. In still other embodiments, the lead frame 100 of FIG. 2C (back side up) may not be flipped, the lead frame 400 may be directly mounted first, and then the lead frame 100 may be flipped (face up) before the lead is mounted. Line frame 300. The cross-sectional view of Fig. 2F shows that the lead frame 300 and the lead frame 400 have completed their respective mounting steps.

At this time, a first wafer 201 and a second wafer 202 are adhered to each of the pedestals 101. Each of the first wafers 201 has an interconnecting sheet unit 301 adhered thereto, and each of the second wafers 202 has a sticker adhered thereto. The slice unit 401 is interconnected. In order to understand in more detail the mutual structural relationship of them directly, the 2G drawing is an example in which a susceptor 101 and a first wafer 201 and a second wafer 202 and its interconnecting chip units 301, 401 adhered to the front and back sides are taken, but It should be emphasized that this is only for the convenience of visual observation, and virtually no cutting steps are performed on the lead frames 100, 300 and 400.

Referring to FIG. 2G and FIG. 2D-1, an interconnecting piece 301a is adhered to the electrode 201a on the front surface of the first wafer 201, and an interconnecting piece 301b is adhered to the electrode 201b. An interconnecting piece 401a is adhered to the electrode 202a on the front surface of the second wafer 202, and an interconnecting piece 401b is adhered to the electrode 202b. The electrodes on the back side of the first wafer 201 and the second wafer 202 are electrically connected to the susceptor 101 at the same time. In the power management system, the first and second wafers are respectively used as a pull-up transistor and a pull-down transistor. Although the sizes of the first wafer 201 and the second wafer 202 may be slightly different, one large and one small, it can still be considered The electrode 201a of one wafer 201 and the electrode 202a of the second wafer 202 generally exhibit a symmetric arrangement with the susceptor 101 as a symmetrical center plane. Similarly, the electrode 201b of the first wafer 201 and the electrode 202b of the second wafer 202 are substantially The symmetry is also presented with the pedestal 101 as the symmetrical center plane. As a result of this design, the interconnecting piece 301a and the interconnecting piece 401a are substantially symmetrical with respect to the susceptor 101, and the interconnecting piece 301b and the interconnecting piece 401b are also substantially symmetrical with respect to the susceptor 101.

In the 2Gth diagram, the thickness between the interconnecting sheets on the two electrodes provided on the front surface of each of the first wafer 201 or the second wafer 202 is not equal. In some embodiments, at the interconnect slice unit 301 The interconnecting piece 301a (primary interconnecting piece) provided on the electrode 201a of the first wafer 201 is thicker than the interconnecting piece 301b (secondary interconnecting piece) provided on the electrode 201b, and similarly, in the interconnecting piece unit 401, The interconnection piece 401a (primary interconnection piece) on the electrode 202a of the two wafer 202 is thicker than the interconnection piece 401b (secondary interconnection piece) provided on the electrode 202b.

In the 2H drawing, the bottom surface of the interconnecting sheet 301a is adhered to the electrode 201a of the first wafer 201, and the bottom surface of the interconnecting sheet 301b is adhered to the electrode 201b of the first wafer 201. The bottom surface of the interconnection piece 401a is adhered to the electrode 202a of the second wafer 202, and the bottom surface of the interconnection piece 401b is adhered to the electrode 202b of the second wafer 201. In this way, after the molding process is performed, the lead frames 100, 300, and 400 are covered with a plastic sealing layer or a molding compound 501 such as an epoxy resin, and each of the first wafer 201 and the second wafer 202 is also coated. The degree of molding of the lead frames 300, 400 of the material 501 can be adjusted, for example, the top surface of the interconnecting sheet 301a in each of the interconnecting sheet units 301 is exposed from the molding compound 501, and likewise, the interconnecting sheet 401a of each of the interconnecting sheet units 401 The top surface can be exposed from the outside of the molding compound 501. However, the top surface of the thinner interconnecting piece 301b will undoubtedly be covered by the molding compound 501, and the top surface of the thinner interconnecting piece 401b will undoubtedly be covered by the molding compound 501.

In some embodiments, as in FIGS. 2H to 2I, one side edge 101' of each susceptor 101 and one side of the interconnection piece 301a on the first wafer 201 adhered to the susceptor 101 The rim face 301'a is on the same common face 508, and a side edge face 401'a of the interconnecting piece 401a adhered to the second wafer 202 on the susceptor 101 is also located at the common face 508. In addition, a side edge surface 301'b of the interconnection sheet 301b adhered to the first wafer 201 on the susceptor 101 is located in the common surface 508, and is adhered to the second wafer 202 on the susceptor 101. A side edge surface 401'b of the interconnecting piece 401b is also located within the common surface 508.

If not before the plastic is sealed, the interconnecting piece 301a (or 401a, 301b, 401b) The ends of the side edge faces 301'a (or 401'a, 301'b, 401'b) are the free ends of the interconnecting pieces 301a (or 401a, 301b, 401b), and the base 101 originally has a side edge face 101', then we want the side edge surface 101' of the susceptor 101 and the side edge faces (301'a, 401'a and 301'b, 401'b) of the respective interconnect sheets to be on the same common face 508. The reason is that after the lamination process is completed, it is necessary to perform a package Saw on the laminate including the lead frames 100, 300, and 400 and the molding compound 501 to obtain the power semiconductor device 555 shown in FIG. In the surface condition, the side edge faces (301'a, 401'a, and 301'b, 401'b, and 101') will each have a cut side edge of the molded body 500 obtained by cutting the plastic seal layer along the common face 508. The face 500C is bare. In this case, the side edge faces (301'a, 401'a, and 301'b, 401'b, and 101') are originally present before unmolding.

However, there are some exceptions. If the side faces (301'a, 401'a and 301'b, 401'b and 101') are not originally present, they are simply because the interconnection is cut off in the subsequent cutting process. The cut faces of the interconnected sheets formed by the sheets are not required to exist before the cutting step is performed. At this time, the susceptor 101 is cut along the one side cutting surface 500C which is a cutting forming surface of the molding body 500, and a cutting surface which is embodied as the subsequent side edge surface 101' is formed. The interconnecting piece 301a is cut along the cut forming surface, i.e., the side edge surface 500C, to form a cut surface which is embodied as a subsequent side edge surface 301'a. The interconnecting piece 301b is cut along the cut forming surface, i.e., the side edge surface 500C, to form a cut surface which is embodied as a subsequent side edge surface 301'b. The interconnecting piece 401a is cut along the cut forming surface, i.e., the side edge surface 500C, to form a cut surface which is embodied as a subsequent side edge surface 401'a. The interconnecting piece 401b is cut along the cut forming surface, i.e., the side edge surface 500C, to form a cut surface which is embodied as a subsequent side edge surface 401'b. It is apparent that these cut edge faces (301'a, 401'a, and 301'b, 401'b, and 101') are naturally coplanar with the cut face of the molded body 500, that is, the side edge face 500C.

In the steps of FIGS. 2H to 2I, the cutting as shown in FIG. 2H can be performed. Line 554, which cuts the stack between adjacent pedestals 101 (including lead frames 100, 300 and 400 and molding compound 501), produces a power semiconductor device 555 as shown in FIG. Each of the susceptor 101 and the first wafer 201 and the second wafer 202 adhered thereon are covered by a molding body 500 cut by a molding compound 501 or a plastic sealing layer, and the molding body 500 is further coated thereon. The interconnecting sheets 301a and 301b on the front surface of the first wafer 201 on the susceptor 101, and the interconnecting sheets 401a and 401b on the front surface of the second wafer 202 on the susceptor 101. In some optional embodiments, if the top surface of the interconnecting sheet 301a is exposed from the original top surface of the molding compound or the molding layer 501, and/or the top surface of the interconnecting sheet 401a is exposed from the original bottom surface of the molding compound or the molding layer 501, The top surface of the interconnecting sheet 301a is still exposed from the top surface 500A of the molding body 500 cut by the molding compound 501, and/or the top surface of the interconnecting sheet 401a is still cut from the molding body 500 by the molding compound 501. The bottom surface 500B is exposed. The base 101 is completely plastically sealed except that the side edge surface 101' is exposed to the side edge surface 500C of the molding body 500. In various embodiments, the interconnecting sheets extend to the same side edge of the molding body in a plane parallel to the base, at least a portion of the base also extending parallel to the same side edge of the molding.

Referring to FIGS. 3A-3C, a PCB circuit board 600 is provided having pads (604a, 604b and 603a, 603b, and 601) disposed on the surface of the chip, the layout of the pads and each power device The layout manner of each of the side edge surfaces exposed by the plurality of interconnecting sheets from the side edge surface 500C of the molding body 500 is the same.

3A and 3B, the size and shape of the pad 604a substantially coincide with the side edge surface 401'a of the interconnecting piece 401a, and the size and shape of the land 604b are substantially the same as the side edge surface 401'b of the interconnecting piece 401b. . The size and shape of the land 603a substantially coincide with the side edge surface 301'a of the interconnect sheet 301a, and the size and shape of the land 603b substantially coincide with the side edge surface 301'b of the interconnect sheet 301b. In addition to this, the size and shape of the land 601 substantially coincide with the side edge surface 101' of the susceptor 101. Such a pad The layout and interconnected side profile layouts prepare for subsequent patches.

As shown in FIG. 3C, the power semiconductor device 555 is erected so that the side edge surface 500C of the molding body 500 is brought close to the surface of the chip of the PCB circuit board to serve as a patch bonding surface, thereby mounting the power semiconductor device 555 by surface mounting technology. On the PCB circuit board, the pads and the side edges of the interconnect sheets having substantially the same size and shape can be aligned by solder paste. At this time, the top surface 500A and the bottom surface 500B of the molding body 500 are perpendicular to the surface of the patch of the PCB. If the top surface 500A and the bottom surface 500B of the molded body 500 are used as the device for the joint surface of the patch in the conventional technical solution, since the areas of the top surface 500A and the bottom surface 500B of the molded body 500 are much larger than the side edge surface 500C This will take up a lot of effective area of the surface of the patch on which the PCB is placed, resulting in a bulky device. The present invention is completely different from the conventional technology. The power semiconductor device 555 is perpendicular to the PCB, and the smaller side edge surface 500C serves as a patch bonding surface, which greatly reduces the occupied PCB area. Therefore, the power semiconductor device 555 provided by the present invention embodies The advantage of a small size Footprint area device.

In the embodiment of FIG. 4A to FIG. 4B, the exposed top surface of the interconnecting piece 301a (main interconnecting piece) is pasted with an L-shaped heat sink 700a adapted to the shape and size of the main interconnecting piece for the heat sink. The 700a can be aligned with the main interconnecting piece 301a to maximize heat dissipation. In some embodiments, a side flap 700b extends outwardly from a side edge 700c of the heat sink 700a in a direction away from the discrete heat sheet 700a, the side flap 700b being perpendicular to the heat sink 700a. The side edge 700c of the heat sink 700a is aligned with the side edge surface 500C of the molding body 500. In FIG. 4B, the power semiconductor device 555 is vertically mounted on the surface of the patch of the PCB, and the side flaps 700b are parallel to the surface of the patch of the PCB, and the area of the pads 604a, 603a in FIG. 3A is appropriately increased, using the conductive bonding material. For example, solder paste, the side wings 700b on the top and bottom sides of the power semiconductor device 500 are respectively adhered to the pads 604a, 603a, thereby increasing the electrical contact area of the interconnecting piece 401a and the pad 604a, and increasing The electrical contact area of the interconnect piece 301a and the pad 603a, and the degree of bonding between the power semiconductor device 500 and the PCB are also enhanced, and the side wing 700b also serves as a main heat dissipation path of the device.

In an alternative embodiment of FIG. 2I, the electrode 201b of the first wafer 201, which is a MOSFET, is the gate, the electrode 201a is the drain, and the electrode on the back side of the first wafer 201 is the source. The other electrode 202b of the second wafer 202 which is a MOSFET is a gate, the electrode 202a is a source, and the electrode of the back surface of the second wafer 202 is a drain thereof. At this time, the side edge surface 101' of the susceptor 101 must be exposed, and the susceptor 101 serves as a common coupling node LX between the pull-up transistor and the pull-down transistor of the power semiconductor device 500, and outputs a voltage.

In another alternative embodiment of FIG. 2I, the electrode 201b of the first wafer 201, which is a MOSFET, is the gate, the electrode 201a is the source, and the electrode on the back side of the first wafer 201 is its drain. The other electrode 202b of the second wafer 202 which is a MOSFET is a gate, the electrode 202a is a source, and the electrode of the back surface of the second wafer 202 is a drain thereof. At this time, whether or not the side edge surface 101' of the susceptor 101 is necessarily exposed from the outside of the side edge surface 500C is not required, and may or may not be exposed. The exposure is an embodiment of FIG. 2I, and the exposure is 5B. An embodiment of the figure.

In the embodiment of FIGS. 5A to 5B, one side edge faces (301'a, 301'b) of the interconnecting pieces (301a, 301b) on the first wafer 201 on each of the susceptors 101 are in the same The common face 508', one of the side edge faces (401'a, 401'b) of the interconnecting pieces (401a, 401b) on the second wafer 202 on the susceptor 101 is also located within the common face 508'. However, a side edge 101' of the pedestal 101 near the common plane 508' is not in the common plane 508', which corresponds to a side edge of the susceptor 101 near the common plane 508', which contracts inwardly without extending outward to Outside or coplanar with the public face 508'. Once the laminate is cut along the common face 508' to form a cut side edge face 500C of the molded body 500, any one of the interconnect pieces (301a, 301b, 401a, 401b) can be made. The side edge faces (301'a, 301'b, 401'a, 401'b) in the common face 508' are all from one side edge of the molded body 500 obtained by cutting the laminate along the common face 508'. The face 500C is exposed, but the base 101 is completely molded inside the molded body 500, and it is not exposed on the side edge face of the side edge face 500C. In an alternative embodiment of Figure 5B, the electrode 201b of the first wafer 201, which is a MOSFET, is the gate, the electrode 201a is the source, and the electrode on the back side of the first wafer 201 is its drain. The other electrode 202b of the second wafer 202 which is a MOSFET is a gate, the electrode 202a is a source, the electrode of the back surface of the second wafer 202 is a drain thereof, and the first wafer 201 and the second wafer 202 are arranged in a common drain. The difference between Fig. 5B and Fig. 2I is only whether or not the side edge surface 101' of the susceptor 101 is exposed. In addition, if the side edge faces (301'a, 301'b, 401'a, 401'b) are obtained by the cutting step to obtain the interconnected sheet cutting faces, they are not present, they are merely because of the subsequent cutting process. In the cutting surface of the interconnecting piece formed by cutting the interconnecting piece, the conditions for requiring them to be coplanar are not present before the cutting step is performed, but when the cutting face 500C is required to be formed, the cutting can not be touched to the pedestal 101 close to the cutting. The edge of the face 500C is provided with a gap distance between the edge of the base 101 near the cutting face 500C and the cutting face 500C. In various embodiments, the interconnecting sheets extend to the same side edge of the molding body in a plane parallel to the base, at least a portion of the base also extending parallel to the same side edge of the molding.

The steps of FIGS. 6A to 6B and FIGS. 2H to 2I are merely that the molding compound 501 can completely mold the second lead frame 300 and/or completely mold the third lead frame 400. If the molding compound 501 seals each of the interconnecting sheet units 301 and the third lead frame 400 in the second lead frame 300, the top surface of the interconnecting sheet 301a does not pass from the molding compound 501 or the plastic sealing layer. The top surface is exposed, and/or the top surface of the interconnect sheet 401a is not exposed from the bottom surface of the molding compound 501 or the molding layer. At this time, in the molding body 500 cut by the molding compound 501, mutual The top surfaces of the webs (301a, 301b), (401a, 401b) are completely covered by the molding body 500, except that one side edge surface of each of the interconnecting sheets is exposed from the side edge surface 500C of the molding body 500 (class Same as Figure 2I).

7A to 7D are flowcharts for replacing the 2A to 2F, and in this embodiment, it is not necessary to perform the above-described multiple inversion on the lead frame 100. In FIG. 7A, the lead frame 300 and each of the interconnecting sheets are faced with the bottom surface facing upward and the top surface facing downward, and the first wafer 201 is flip-chip mounted on the lead frame 301, that is, flipped onto the interconnecting sheet unit 301. The interconnecting sheet 301a is adhered to the electrode 201a on the front surface of each of the first wafers 201, and the interconnecting sheet 301b is adhered to the electrode 201b on the front surface of the first wafer 201. As shown in FIGS. 7B-1 to 7B-2, a first lead frame 100 having a plurality of pedestals 101 is mounted over a plurality of first wafers 201 so as to electrode pairs on the back side of each of the first wafers 201 The base is adhered to the back surface of a base 101 and electrically contacted with the base 101, thereby mounting a base 101 to a first wafer 201. As shown in FIGS. 7C-1 to 7C-2, a second wafer 202 is adhered to the front surface of each of the susceptors 101, and electrodes on the back surface of the second wafer 202 are adhered to the front surface of the susceptor 101 and electrically contacted with the susceptor 101. As shown in FIG. 7D, a third lead frame 400 having a plurality of interconnect sheets is mounted over the plurality of second wafers 202, that is, an interconnect sheet unit 401 is mounted over the second wafer 202 such that each second An interconnecting piece 401a is adhered to the electrode 202a on the front surface of the wafer 202, and an interconnecting piece 401b is adhered to the electrode 202b on the front surface of the second chip 202. For the convenience of observation, the structure including the first and second wafers and the lead frame (100, 300, 400) obtained in Fig. 7D may be flipped once, which is the structure shown in Fig. 2F (but there is substantially no need to flip) The subsequent steps are no different from the method flow shown in Figures 2G through 2I.

The positioning holes 105 provided at the edges of the first lead frame 100 have the same layout as the positioning holes 305 of the second lead frame 300 and the positioning holes 405 of the third lead frame 400. In order to enable precise alignment of the lead frames with the first lead frame 100 when the second and third lead frames are mounted, usually in a vertical direction, such as a predetermined positioning pin passes through The lead frames 100, 300, and 400 are aligned with each other in a direction in which they are aligned with each other in the vertical direction.

The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and modifications Any and all equivalent ranges and contents within the scope of the claims are intended to be within the spirit and scope of the invention.

101‧‧‧Base

101', 301', 401'‧‧‧ side margin

500‧‧‧plastic body

500A‧‧‧ top surface

500B‧‧‧ bottom

500C‧‧‧lateral side

555‧‧‧Power semiconductor device

Claims (22)

A power semiconductor device, comprising: a pedestal; and first and second wafers respectively adhered to the front and back sides of the pedestal; one or more interconnecting sheets disposed on the front surface of the first wafer; One or more interconnecting sheets on the front side of the two wafers; a molding body covering the first and second wafers, and the base and the interconnecting sheets are wrapped in such a manner that at least one side edge surface of each of the interconnecting sheets The side surface of the molded body is exposed. The power semiconductor device according to claim 1, wherein a side edge surface of the susceptor is coplanar with a side edge surface of each of the interconnecting sheets exposed to the molding body, and is also interconnected from the molding body for external exposure. The side edge surface of the sheet side edge surface is exposed. The power semiconductor device according to claim 1, wherein the susceptor is covered with the molded body without the side edge surface being exposed. The power semiconductor device of claim 1, wherein a top surface of the at least one interconnecting sheet disposed on the front surface of the first wafer is exposed from a top surface of the molding body. The power semiconductor device according to claim 1, wherein a top surface of each of the interconnecting sheets provided on the front surface of the first wafer is covered with a molding body. The power semiconductor device according to claim 1, wherein a top surface of the at least one interconnecting sheet provided on the front surface of the second wafer is exposed from a bottom surface of the molding body. The power semiconductor device according to claim 1, wherein a top surface of each of the interconnection sheets provided on the front surface of the second wafer is covered with a molding body. The power semiconductor device according to claim 1, wherein the electrodes on the front surfaces of the first and second wafers are respectively adhered to the interconnecting sheets, and the electrodes on the back surfaces of the first and second wafers are respectively adhered by the conductive materials. On the front and back of the base. The power semiconductor device according to claim 1, wherein the thickness of the main and sub-interconnect sheets provided on the two electrodes on the front surface of each of the first or second wafers is not equal, and the main interconnect sheet is substantially rectangular. And forming an L shape by each of the corners of the corner portion, the sub-interconnecting sheet is disposed in the slit, and the thickness of the main interconnecting sheet is greater than the thickness of the secondary interconnecting sheet. The power semiconductor device according to claim 9, wherein a top surface of the main interconnecting sheet disposed on the front surface of the first wafer is exposed from a top surface of the molding body, and is disposed on a top surface of the main interconnecting sheet on the front surface of the second wafer Exposed from the bottom surface of the molding body; and an L-shaped heat sink corresponding to the shape of the main interconnecting sheet is adhered on the top surface of the main interconnecting sheet so as to coincide with the main interconnecting sheet and on one side edge of the heat sink Extending a side flank perpendicular to the heat sink, the side edge of the heat sink is aligned with the side edge of the outer body of the molded body exposed interconnecting sheet. A method of fabricating a power semiconductor device, comprising the steps of: providing a first lead frame having a plurality of pedestals; attaching a first wafer to a front surface of each pedestal, and flipping the first lead frame after each a second wafer is adhered to the back of the base; a second lead frame provided with a plurality of interconnecting sheets is mounted on the plurality of first wafers so as to be aligned with each other on each of the electrodes on the front surface of each of the first wafers a third lead frame provided with a plurality of interconnecting sheets mounted on the plurality of second wafers for aligning and attaching one of the interconnecting sheets on each of the electrodes on the front surface of each of the second wafers; performing a molding process using the plastic seal Covering the first, second and third lead frames, and coating each of the first and second wafers; cutting a stack between adjacent pedestals, the stack comprising first, second and third Lead frame and molding compound; Each of the pedestals and the first and second wafers adhered thereon are covered by a molding body cut by a molding compound, and the molding body is further coated on the pedestal on the front side of the first wafer or And a plurality of interconnecting sheets and one or more interconnecting sheets covering the front surface of the second wafer on the base such that one side edge surface of each of the interconnecting sheets is exposed from a cutting side edge surface of the molding body. The method of claim 11, wherein the electrodes on the back sides of the first and second wafers are respectively adhered to the front and back sides of the susceptor by conductive materials. The method of claim 11, wherein each of the side edges of the interconnecting sheets on the first wafer on each of the pedestals is on the same common side as the side rim of the pedestal, the base A side edge surface of each of the interconnecting sheets on the second wafer is also located in the common surface; the laminate is cut along the common surface to form a cutting side edge surface of the molding body so that the base is in the common surface The side edge faces, and the side edge faces of any one of the interconnecting sheets in the common face, are exposed from one side edge face of the molded body obtained by cutting along the common face. The method of claim 11, wherein each of the side edges of the interconnecting sheets on the first wafer on each of the pedestals are on the same common surface, and the interconnecting sheets on the second wafer on the pedestal Each of the side edge faces is also located on the common face; the laminate is cut along the common face to form a cut side edge face of the molded body such that any one of the interconnected sheets has a side edge face in the common face The one side edge surface of the molded body obtained by performing the cutting is exposed. The method of claim 11, wherein the molding compound encapsulates the top surface of each of the interconnecting sheets, and after cutting to form the molded body, the top surface of each of the interconnecting sheets is molded. Wrapped inside. The method of claim 11, wherein the molding compound in the molding process exposes a top surface of the at least one interconnecting sheet disposed on the front surface of the first wafer from the molding compound, and cuts the shape After the plastic package is formed, a top surface of at least one of the interconnecting sheets disposed on the front surface of the first wafer is exposed from the top surface of the molding body. The method of claim 11, wherein the molding compound in the molding process exposes a top surface of the at least one interconnecting sheet disposed on the front surface of the second wafer from the molding compound, and after cutting to form the plastic sealing body, A top surface of at least one of the interconnecting sheets on the front side of the second wafer is exposed from the bottom surface of the molding body. The method of claim 11, wherein the thickness of the primary and secondary interconnecting sheets on the two electrodes on the front side of each of the first or second wafers is unequal, and the main interconnecting piece is substantially rectangular and The corner portion has an L-shape, and the sub-interconnect sheet is disposed in the slit, and the thickness of the main interconnect sheet is greater than the thickness of the sub-interconnect sheet. The power semiconductor device according to claim 18, wherein a top surface of the main interconnect sheet on the front surface of the first wafer is exposed from a top surface of the molding body, and a top surface of the main interconnect sheet on the front surface of the second wafer is provided from the plastic package The bottom surface of the body is exposed; and an L-shaped heat sink corresponding to the shape of the main interconnect sheet is adhered on the top surface of each main interconnect sheet so as to coincide with the main interconnect sheet and on one side edge of the heat sink A side flap extending perpendicularly to the heat sink is extended, and the side edge of the heat sink is aligned with the side edge surface of the molded body for exposing the interconnect sheet. A method of fabricating a power semiconductor device, comprising the steps of: providing a second lead frame having a plurality of interconnecting sheets, flipping the first wafer on the second lead frame, on the front side of each of the first wafers Attaching an interconnecting piece to each of the electrodes; mounting a first lead frame having a plurality of pedestals on the plurality of first dies to adhere the electrodes on the back surface of each of the first wafers to a pedestal a back side; a second wafer is attached to the front side of each of the bases; Providing a third lead frame having a plurality of interconnecting sheets mounted on the plurality of second wafers for aligning and attaching one of the interconnecting sheets on each of the electrodes on the front surface of each of the second wafers; performing a plastic sealing process using the plastic sealing package Overlying the first, second and third lead frames, and cladding each of the first and second wafers; cutting a stack between adjacent pedestals, the laminate comprising first, second and third lead frames And a molding compound; each of the pedestals and the first and second wafers adhered thereon are covered by a molding body cut by a molding compound, and the molding body is further coated on the pedestal on the first wafer One or more interconnecting sheets on the front surface and one or more interconnecting sheets covering the front surface of the second wafer on the base such that one side edge surface of each of the interconnecting sheets is from a cutting side edge surface of the molding body Be exposed. The method of claim 20, wherein each of the side edges of the interconnecting sheets on the first wafer on each of the pedestals is on the same common side as the side rim of the pedestal, the base A side edge surface of each of the interconnecting sheets on the second wafer is also located in the common surface; the laminate is cut along the common surface to form a cutting side edge surface of the molding body so that the base is in the common surface The side edge faces, and the side edge faces of any one of the interconnecting sheets in the common face, are exposed from one side edge face of the molded body obtained by cutting along the common face. The method of claim 20, wherein each of the side edges of the interconnecting sheets on the first wafer on each of the pedestals are on the same common surface, and the interconnecting sheets on the second wafer on the pedestal Each of the side edge faces is also located on the common face; the laminate is cut along the common face to form a cut side edge face of the molded body such that any one of the interconnected sheets has a side edge face in the common face The one side edge surface of the molded body obtained by performing the cutting is exposed.