TWI538155B - Multi-wafer laminated package structure and packaging method thereof - Google Patents

Description

Multi-wafer laminated package structure and packaging method thereof

The present invention relates to the field of semiconductors, and more particularly to a package structure of a multi-wafer stack and a method of packaging the same.

In a DC-DC converter, two MOSFETs (metal oxide semiconductor field effect transistors) are usually provided as switching switches, one is a high-side MOSFET (referred to as HS), and the other is a low-side MOSFET (referred to as a low-side MOSFET). LS). Wherein, the gate G1 of the HS and the gate G2 of the LS are connected to a controller (referred to as IC); the drain D1 of the HS is connected to the Vin terminal, the source S1 is connected to the drain D2 of the LS, and the source S2 of the LS is connected. The Gnd terminal is formed to form the DC-DC converter.

For the chip package structure in the DC-DC converter, it is desirable to package the high-side MOSFET chip and the low-side MOSFET chip and the controller chip in the same plastic package to reduce the number of peripheral components and improve the utilization efficiency of the power supply and the like. However, for a specific package structure, the high-side MOSFET chip and the low-side MOSFET chip and the controller chip can only be arranged in parallel on the same plane of the lead frame, so that the package is bulky; and, only by the lead wire Connecting the corresponding pins of the wafer (for example between the source S1 of the HS and the drain D2 of the LS) will increase the resistance and thermal resistance, affecting the performance of the finished component.

It is an object of the present invention to provide a multi-wafer stacked package structure and a method of packaging the same that can be stacked on a plane in which the high-side and low-side MOSFET wafers are placed by providing tabs, and The connection of the corresponding wafer pins is realized by the connecting piece, so that a plurality of semiconductor chips are packaged in the same semiconductor package, thereby reducing the number of components in the assembly of the DC-DC converter and reducing the size of the entire semiconductor package. And effectively improve the electrical performance and heat dissipation of the components.

In order to achieve the above object, a technical solution of the present invention provides a package structure of a multi-wafer stack, comprising: a lead frame provided with a first stage, a second stage and a plurality of pins spaced apart from each other The second stage is further provided with a first portion and a second portion spaced apart from each other; the first wafer has a back electrode disposed downwardly and electrically connected to the first stage; and the second wafer is flipped Having its front electrode disposed downwardly and electrically connected to the first portion and the second portion of the second stage, some of the front electrodes of the second wafer being connected to the first portion, wherein other front electrodes are connected to the a second portion; a connecting piece, the bottom surface of which is electrically connected to some of the front electrodes disposed upwardly of the first wafer, and the back electrode disposed upwardly of the second wafer; the third wafer having the back surface disposed downwardly and insulatively connected thereto a top surface of the connecting piece; a plastic body enclosing a third wafer, which is stacked in a multi-layer structure, and connected a chip, a first wafer and a second wafer, a lead frame, and a lead wire correspondingly connected between the wafer electrode and the wafer electrode or between the wafer electrode and the pin, and a portion connecting the pin to the external component and the first load At least a portion of the back of the stage and the second stage is exposed outside of the molded body.

In a specific application example, the first wafer is an HS wafer as a high-side MOSFET chip, the drain disposed on the back side is electrically connected to the first stage; and the second wafer is a low-side MOSFET chip. And the LS wafer of the wafer level package has a source disposed on the front side electrically connected to the first portion of the second stage, and a gate disposed on the front surface electrically connected to the second portion of the second stage; the connection The back side of the sheet is electrically connected to the source of the front surface of the HS wafer and the drain of the back surface of the LS wafer for electrically connecting the two electrodes; the third wafer is an IC as a controller a wafer whose bottom surface is insulatively connected to the top surface of the connecting sheet, and a plurality of electrodes on the top surface thereof are respectively connected to corresponding pins on the corresponding electrodes or lead frames on the other wafers by leads; the HS wafer front side Or a plurality of electrodes on the back side of the LS wafer that are not shielded by the connecting sheets are also respectively connected to corresponding pins on the other wafers or corresponding pins on the lead frame by the leads.

In one embodiment, the package structure is further provided with a heat dissipation plate before the molding body is formed, and the heat dissipation plate and the third wafer are respectively connected on the top surface of the connection piece to form the heat dissipation plate and the connection piece. The heat-conducting contact, thereby achieving heat dissipation by the surface of the heat sink exposed to the top surface of the molding body.

In another embodiment, the package structure is further provided with a heat dissipation plate after forming the plastic body; the top surface of the plastic sealing body is further formed with a notch, and the bottom of the heat dissipation plate is inserted The gap is inserted to connect to the top surface of the connecting piece, and the heat conducting contact between the heat dissipating plate and the connecting piece is formed, thereby dissipating heat by the top of the heat dissipating plate remaining outside the top surface of the laminating body.

The connecting piece is provided with a high-end connecting portion connected to the first wafer, and a low-end connecting portion connected to the second wafer; the high-end connecting portion and the low-end connecting portion of the connecting piece have the same or different thicknesses; In one embodiment, the sum of the thicknesses of the high-end connecting portion, the first wafer, and the first stage is equal to the sum of the thicknesses of the low-end connecting portion, the second wafer, and the second stage, thereby The top surface of the tab is connected to the rear to securely place the third wafer.

In still another embodiment, the third wafer is connected to a lower portion of the high-end connection portion or the low-end connection portion of the connection piece, and a portion of the high-end connection portion or the lower-end connection portion having a larger thickness The top surface is exposed to the outside of the molded body to achieve heat dissipation.

Preferably, a plurality of contacts for partially adjusting the thickness of the connecting piece are formed on the connecting piece, the contact is such that the top of the connecting piece is recessed downward to form a blind hole which does not penetrate and at the same time the bottom of the connecting piece faces The underlying structure.

The connecting piece is further provided with a lead connecting portion electrically connected to the interconnecting pin provided by the lead frame; the lead connecting portion, the high end connecting portion and the low end connecting portion are integrally formed or assembled by being connected To form the connecting piece; preferably, the lead connecting portion and the interconnecting pin are correspondingly provided with a locking mechanism for preventing a change in position of the connecting piece during assembly and packaging.

Preferably, between the first wafer and the first stage, between the second wafer and the second stage, the conductive between the connecting piece and the first and second wafers Connection by solder or conductive epoxy glue between interconnected surfaces The third wafer is insulatively connected to the connecting piece by a non-conductive adhesive disposed on the back surface of the third wafer.

Preferably the tab is a copper sheet.

Another technical solution of the present invention provides a method for packaging a multi-wafer stack, comprising: providing a lead frame provided with a first stage, a second stage and a plurality of pins spaced apart from each other The second stage is further provided with a first portion and a second portion spaced apart from each other; the back electrode of the first wafer is arranged downward and electrically connected to the first stage; the second wafer is turned over to be frontal The electrodes are arranged downwardly and electrically connected to the first portion and the second portion of the second stage, some of the front electrodes of the second wafer being connected to the first portion, and wherein the other front electrodes are connected to the second portion Connecting the bottom surface of the connecting sheet to be electrically connected to some of the front electrodes arranged upwardly of the first wafer, and the back electrodes arranged upwardly of the second wafer; and arranging the back surface of the third wafer downward and insulatingly connected to the connecting sheet a top surface; a third wafer, a connecting sheet, a first wafer and a second wafer, a lead frame, and a corresponding connection between the wafer electrode and the wafer After encapsulating the leads between the wafer electrodes and the leads, the molded body is cut to form a separate component; and the portion connecting the pins to the external components and the first stage and the second stage At least a portion of the back side is exposed outside of the molded body.

In one embodiment, the packaging method further connects a heat dissipating plate disposed on the top surface of the connecting piece before the plastic sealing, so that the heat dissipating plate forms a heat-conducting contact with the connecting piece, and the heat dissipating plate is further The surface exposed outside the top surface of the molded body is allowed to dissipate heat.

In another embodiment, the encapsulation method forms a notch on the top surface of the encapsulant formed by the package, and inserts a bottom of the disposed heat dissipation plate into the notch to be connected to the top surface of the connection piece, and forms the heat dissipation. The plate is in thermal contact with the connecting piece, and heat is dissipated by the top of the heat dissipating plate remaining outside the top surface of the molding body.

The connecting piece is provided with a high-end connecting portion connected to the first wafer, and a low-end connecting portion connected to the second wafer; the high-end connecting portion and the low-end connecting portion of the connecting piece have the same or different thicknesses; When the thicknesses of the two are different, the third wafer is connected to a portion of the high-end connecting portion or the low-end connecting portion of the connecting piece, and the thick portion of the high-end connecting portion or the low-end connecting portion is The top surface is exposed to the outside of the molded body to achieve heat dissipation.

Preferably, between the first wafer and the first stage, between the second wafer and the second stage, the conductive between the connecting piece and the first and second wafers The connection is achieved by solder or conductive epoxy glue disposed between the interconnected surfaces; the third wafer is insulatively connected to the connecting sheet by being disposed on the back surface of the third wafer Non-conductive adhesive is achieved.

In a preferred embodiment, a plurality of contacts for partially adjusting the thickness of the connecting piece are formed on the connecting piece, and the contact is formed by punching the top surface of the connecting piece to form a non-penetrating blind hole. At the same time, the bottom surface of the connecting piece protrudes downward.

In any of the above embodiments, the first wafer is formed by forming a plating layer on a surface of the ruthenium for connecting other components, performing wafer testing, wafer back grinding and back metallization to control the first The thickness of the wafer is formed to form a corresponding back electrode; the individual wafers are formed by dicing; and then the first wafer back side is connected down to the first stage.

The second wafer is formed by forming a plating layer on a surface of the cymbal for connecting other components; performing wafer testing and circuit pattern mapping; and implanting a ball at a corresponding position on the front side of the cymbal to form a corresponding front electrode; The wafer level package forms a package; the front side of the wafer is ground to expose the top of the ball to the outside of the top surface of the package; the front side of the wafer is pre-cut to form a scribe groove; the back side of the wafer is polished and the back surface is metallized to control the second wafer. The thickness is formed to form a corresponding back electrode; the individual wafers are formed by dicing; after that, the second wafer is turned over and then connected face down to the second stage.

The third wafer is formed by: back grinding of the wafer; coating the back side of the IC wafer with a non-conductive adhesive; cutting to form each of the independent third wafers; and then bonding the third wafer to the already connected a top surface of the connecting sheet on the first wafer and the second wafer; after the third wafer, the connecting sheet, the first wafer and the second wafer are stacked to form a multilayer structure, the following process is further performed: bonding the adhesive tape to perform curing; Corresponding between the wafer electrode and the wafer electrode, and between the wafer electrode and the lead are respectively formed to form a lead; forming a plastic body; forming a plating layer at a position exposed to the outside of the plastic package; and finally cutting to form each individual package component.

Compared with the prior art, the package structure of the multi-wafer stack of the present invention and the packaging method thereof have the advantages that the source and the LS wafer of the HS wafer are connected to each other by using a plurality of patches or bonded leads. The structure of the bungee, in the present invention, only one connecting piece is used for soldering or conducting at the same time. Adhered to the source of the HS wafer and the drain of the LS wafer, the two electrodes can be electrically connected. The process is simple and easy to implement, the conduction loss and switching loss are reduced, and the heat dissipation efficiency is enhanced. better.

Compared with the structure in which three wafers are originally discharged in the same plane, the IC chip of the present invention is insulatively connected to the connecting sheet so as to be stacked above the plane of the HS wafer and the LS wafer, so as to effectively reduce the package. Component size, saving packaging materials.

In the present invention, the bottom surfaces of the first stage and the second stage can be exposed to the outside of the plastic package to facilitate connection of the circuit board and heat dissipation. There are also three methods in the present invention, further forming a heat dissipating surface on the top surface of the molding body, that is, exposing a part of the surface of the connecting sheet not connected to the IC wafer to the outside of the plastic sealing body; or further connecting the heat dissipation plate on the connecting sheet, and A part of the surface of the heat sink is exposed to the outside of the plastic package; or the heat sink is inserted into a gap reserved by the plastic body to contact the connecting piece for heat dissipation.

The laminated structure of the present invention does not affect the bonding between the IC wafer and other wafers, and the bonding between the HS wafer or the LS wafer and the leads to form a connection. The thickness of the different positions in the package structure can be adjusted by providing the connecting pieces with different thicknesses of the respective portions or by the heat dissipating plates connected on the connecting pieces, so that the IC chip on the side of the package structure, the connecting piece portion under the package, and the HS wafer The overall thickness of the first stage and the corresponding lead is matched to the thicker portion of the tab on the other side of the package structure or the combination of the heat sink and the tab, the overall thickness of the LS wafer, and the second stage.

In the present invention, a plurality of contacts projecting downward on the bottom surface can be formed by punching holes in the connecting sheet, which can facilitate the local thickness adjustment of the connecting sheet conveniently and quickly, for example, after the bonding of the leads.

In the present invention, a locking mechanism is disposed on the connecting piece and the lead frame pin connected thereto to ensure that the position of the connecting piece does not change during assembly and packaging. In addition, the heat sink can also be fixed in position by providing a locking mechanism.

10‧‧‧ lead frame

100‧‧‧plastic body

101‧‧‧ gap

11‧‧‧First stage

12‧‧‧Part 1

13‧‧‧Part II

14‧‧‧ pin

15‧‧‧Interconnect pins

20‧‧‧HS wafer

30‧‧‧LS wafer

40‧‧‧Connecting piece

41‧‧‧High-end connection

411‧‧‧Bumps

42‧‧‧Low-end connection

421‧‧‧Bumps

43‧‧‧ pin connection

431‧‧‧ highlight

45‧‧‧Contacts

50‧‧‧ IC chip

60‧‧‧ lead

71, 72‧‧‧ heat sink

81‧‧‧Positioning holes

82‧‧‧ Positioning parts

91‧‧‧Epoxy Adhesive

92‧‧‧Adhesive

D1, D2‧‧‧ bungee

G1, G2‧‧‧ gate

S1, S2‧‧‧ source

1A is a perspective view of the chip package structure of the first embodiment of the present invention; FIG. 1B is a front perspective view of the chip package structure of the first embodiment of the present invention; FIG. 1C is a view of the present invention A side cross-sectional view of the chip package structure in an embodiment; FIGS. 1D and 1E are schematic views showing the structure of a preferred connecting piece in the chip package structure of the present invention; FIGS. 2A to 2G are A schematic diagram of a structure corresponding to each step of the wafer encapsulation method in the first embodiment; FIG. 3 is a flow chart of the wafer encapsulation method in the first embodiment of the present invention; FIGS. 4A to 4G are diagrams A schematic diagram of a structure corresponding to each step of the wafer encapsulation method in the second embodiment; FIG. 5 is a flow chart of the wafer encapsulation method in the second embodiment of the present invention; FIGS. 6A to 6H It is a schematic diagram of the structure corresponding to the steps of the wafer encapsulation method in the third embodiment of the present invention; and FIG. 7 is a flow chart of the wafer encapsulation method in the third embodiment of the present invention; 8A to 8F The figure is the fourth embodiment of the present invention Examples of the chip package and method, the steps corresponding to the schematic structural diagram; FIG. 9 is a flowchart of the method of the present invention is encapsulated in the third embodiment of the wafer.

DETAILED DESCRIPTION OF THE INVENTION Various preferred embodiments of the invention are described below in conjunction with the drawings.

Example 1

Referring to FIG. 1A to FIG. 1C, as shown in the figure, two MOSFET chips of the same type (two N-types or two P-types) are respectively used as high-side MOSFETs (referred to as HS wafers 20) and Low-side MOSFET wafer (referred to as LS wafer 30 for short). A controller wafer (abbreviated as IC wafer 50) is stacked on the same plane as the two MOSFET wafers by a connecting piece 40, and the IC wafer 50 and the corresponding electrodes of the LS wafer 30 and the HS wafer 20 are placed. The pins 14 are connected and packaged in the same molding body 100 to form a DC-DC converter.

The HS wafer 20 and the LS wafer 30 are respectively provided with a source and a gate on the front surface of the wafer, and a drain electrode on the back surface of the wafer; wherein the gate G1 of the HS wafer 20 and the gate G2 of the LS wafer 30 are both Connected to the control electrode on the IC chip 50; the drain D1 of the HS wafer 20 is connected to the Vin terminal, the source S1 is connected to the drain D2 of the LS wafer 30, and the source S2 of the LS wafer 30 is connected to the Gnd terminal to form the DC- DC converter. Other components such as capacitors and inductors can be placed between the two ends of the DC-DC converter of the DC-DC converter.

In the package structure provided in this embodiment, a lead frame 10 (see FIG. 2A) is provided, and the lead frame 10 is provided with the first stage 11 and the second stage which are separated from each other on the same plane, wherein The second stage is further provided with a first portion 12 and a second portion 13 which are separated from each other. The lead frame 10 is further provided with a plurality of mutually separated pins 14, including: a low-end source pin, a low-end gate pin, a high-end source pin, a high-side gate pin, and an interconnect pin. 15 and so on.

The pins 14 in this embodiment are distributed around the first stage 11 and the second stage, wherein the high-end drain pin is extended from the first stage 11, the low-end source The pins are extended from the first portion 12 of the second stage, the low-side gate pins are extended from the second portion 13 of the second stage; the other plurality of pins 14 are Separated from the first stage 11 or the second stage.

The HS wafer 20 is placed on the first stage 11, and a solder or conductive epoxy adhesive 91 or other conductive material is disposed between the back surface of the HS wafer 20 and the top surface of the first stage 11. The material is connected so that the drain S1 on the back side of the HS wafer 20 is electrically connected to the first stage 11, and can be connected to the external element through the high-end drain pin.

The wafer-level packaged LS wafer 30 is placed on the second stage after being flipped, and solder is disposed between the downward facing surface of the LS wafer 30 and the first portion 12 and the second portion 13 of the second stage. Conductive epoxy adhesive 91 or the like, so that the source of the front surface of the LS wafer 30 is electrically connected to the first portion 12 of the second stage, and can be connected to the external component through the low-end source pin; The gate G2 on the front side of the LS wafer 30 is electrically connected to the second portion 13 of the second stage, and can communicate with external components through the low-side gate pins.

The connecting piece 40 specially provided in the package structure provided by this embodiment is made of a conductive material, such as a copper piece. The connecting piece 40 is provided with a high-end connecting portion 41 and a low-end connecting portion 42 respectively, which are respectively adhered on the upward surface of the HS wafer 20 and the LS wafer 30 by soldering or conductive epoxy adhesive 91 or the like. The source S1 on the front side of the HS wafer 20 and the drain D2 on the back side of the LS wafer 30 (both of which are arranged upward) are electrically connected to respective positions of the bottom surface of the connecting piece 40, and the sources S1 and LS of the HS wafer 20 are realized. Electrical connection between the drains D2 of the wafer 30.

The thickness of the connecting piece 40 should be designed to satisfy the thickness of the high-end connecting portion 41 of the connecting piece 40 and the HS wafer 20 and the like below, which is equal to the low end of the connecting piece 40. The thickness of the connecting portion 42 and the lower LS wafer 30 and the like are added to ensure that the top surface of the entire connecting piece 40 is parallel to the plane in which the HS wafer 20 and the LS wafer 30 are located after bonding, so as to stably place the IC wafer 50 later. . For example, in a preferred embodiment, the thicknesses of the first stage 11 and the second stage are uniform; the HS wafer 20 and the LS wafer 30 are uniform in thickness, and are connected to the top surface of the two wafers after the lead frame 10; Further, the thickness of the position on the connecting piece 40 corresponding to the connection of the HS wafer 20 and the LS wafer 30 is made uniform, so that the top surface after being stacked on the two wafers is also horizontal.

With reference to FIGS. 1D to 1E, for example, the bumps 411 and 421 capable of adjusting the thicknesses of the high-end connecting portion 41 and the low-end connecting portion 42 can be formed at the bottom of the connecting piece 40, respectively. Moreover, in a preferred embodiment, a plurality of downwardly projecting contacts 45 may be formed at the locations of the bumps 411, 421 to further adjust the thickness of the portions of the tabs 40. These contacts 45 are formed by punching holes in the connecting piece 40 to form non-penetrating pits on the top surface of the connecting piece 40, and forming the contacts 45 at the bottom of the connecting piece 40. On one of the connecting pieces 40, the punching depths of the different position contacts 45 may be the same or different, depending on the specific thickness adjustment.

At the same time, the connecting piece 40 is further provided with a pin connecting portion 43 for electrically connecting with the interconnecting pin 15 at the periphery of the lead frame 10 to make the source S1 of the HS wafer 20 and the drain D2 of the LS wafer 30. And the connecting piece 40 can be further connected to the external component by the interconnecting pin 15. The thickness of the pin connecting portion 43 of the connecting piece 40, the thickness of the downward protruding portion 431, and the thickness of the interconnecting pin 15 connected to the protruding portion 431 should also satisfy the above-mentioned top surface of the connecting piece 40 after bonding. Designed in parallel with two MOSFET wafers.

In a preferred embodiment, a locking mechanism is further provided on the interconnecting pin 15 of the lead frame 10 and the pin connecting portion 43 of the connecting piece 40. At 1A In the exemplary structure of the figure, the locking mechanism on the interconnecting pin 15 is a plurality of positioning holes 81, and the locking mechanism of the connecting piece 40 is a positioning member 82 at a corresponding position at the bottom thereof. The illustrated positioning member 82 is equivalent. A structure extending downward or bent from the bottom surface of the connecting piece 40 can be correspondingly inserted into the positioning holes 81 to fix the position of the connecting piece 40 to ensure that the connecting piece 40 does not move during assembly and packaging. Moreover, when the above-described locking mechanism is provided, the thickness of the positioning member 82 on the connecting piece 40 is larger than the thickness of the pin connecting portion 43 to ensure that the positioning member 82 can be correspondingly inserted into the positioning hole 81 of the interconnecting pin 15. The present invention is not limited to the position in which the positioning hole 81 and the positioning member 82 are interchanged or the locking mechanism using other structures is used in other embodiments.

In the example structure of FIG. 1A, the surface shape of the connecting piece 40 and its size are designed such that the low-end connecting portion 42 of the connecting piece 40 substantially covers most of the area of the top of the LS wafer 30 below it, but the high-end connecting portion 41 does not completely cover the top of the HS wafer 20. Therefore, the source S1 and the gate G1 of the HS wafer 20, which are not shielded by the connecting sheet 40, may be directly connected to the leads 14 of the lead frame 10 or other wafers by a plurality of bonded leads 60, respectively (for example It is on the electrode of the IC chip 50); or, the lead 14 of the lead frame 10 is used as a relay, and a plurality of separately-bonded leads 60 are provided to indirectly connect to corresponding electrodes on other wafers (for example, the IC wafer 50). The present invention is not limited to the use of the tab 40 of other structures in other embodiments, for example, a structure that does not completely cover the LS wafer 30; or, the tab 40 is not integrally formed, but is composed of a plurality of small connections. Components are connected or assembled to each other, and the like.

The IC chip 50 of the present invention is adhesively disposed on the top surface of the connecting piece 40 by a non-conductive adhesive 92 or other insulating fixed connection, so that the IC chip 50, the connecting piece 40, and the HS are provided. The wafer 20 and the LS wafer 30 are formed as a multilayer structure stacked from top to bottom, and the IC wafer 50 and the electrodes of the HS wafer 20 and the LS wafer 30 are not electrically connected by the connecting sheet 40.

In the example structure of FIG. 1A, the IC wafer 50 is located above the high-end connection portion 41 of the connection piece 40, that is, at a position above the HS wafer 20; and in other examples not shown, the IC wafer 50 may be It is located at the other position on the top surface of the connecting piece 40. The plurality of electrodes on the IC wafer 50 can be electrically connected to the corresponding leads 14 on the periphery of the lead frame 10 or the corresponding electrodes of other wafers (for example, the HS wafer 20) by the bonded leads 60, respectively.

The package structure of the present embodiment further includes a molding body 100, and the stacked IC chip 50, the connecting piece 40, the HS wafer 20 and the LS wafer 30 and the lead wires 60 connected to the corresponding electrodes are packaged to form one component. Portions of the respective leads 14 connected to the external components are exposed, and the bottom surfaces of the first stage 11 and the second stage (for example, the first portion 12 thereof) on the lead frame 10 are exposed outside the molding body 100, Used to connect boards or help dissipate heat.

Hereinafter, please refer to the structure shown in FIGS. 2A to 2G and the flow shown in FIG. 3 to describe the method of packaging the wafer according to the embodiment: that is, see FIG. 2A, a lead frame 10 is provided, including The first stage 11 spaced apart from each other, the second stage of the first portion 12 and the second portion 13, and a plurality of pins 14.

Referring to FIG. 2B, a MOSFET wafer is disposed as an HS wafer 20, which is fixedly coupled to the first stage 11 and electrically connected to the first stage 11 of the drain D1 on the back side of the HS wafer 20.

Referring to FIG. 2C, the MOSFET wafer of another wafer level package is set as the LS wafer 30, which is flipped over and fixedly connected to the second stage and the source S1 and the second stage of the front surface of the LS wafer 30 are replaced. A portion 12 is electrically connected, and the gate G2 on the front side of the LS wafer 30 is electrically connected to the second portion 13 of the second stage.

Referring to FIG. 2D, a connecting piece 40 is disposed, and the high-end connecting portion 41 of the connecting piece 40 is connected to the top surface of the HS wafer 20 by a solder or conductive epoxy adhesive 91 or the like on the back side thereof. The low-side connection portion 42 is connected to the top surface of the LS wafer 30, and the pin connection portion 43 is connected to the interconnection pin 15 of the lead frame 10 such that the source S1 of the front surface of the HS wafer 20 and the back surface of the LS wafer 30 are back D2 and The interconnect pins 15 are electrically connected to each other.

Referring to FIG. 2E, the IC wafer 50 is fixedly disposed on the top surface of the connecting sheet 40 by a non-conductive adhesive 92 to form a multilayer structure in which the IC wafer 50, the connecting sheet 40, the HS wafer 20 and the LS wafer 30 are stacked. . Further, a gate electrode G1 and a source S1 which are not shielded by the connection piece 40 on the front side of the HS wafer 20, a plurality of electrodes of the IC wafer 50, and a plurality of pins 14 of the lead frame 10 are mutually connected by a lead wire 60. Corresponding connection.

As shown in the front and back sides of the 2F and 2G drawings, the molded body 100 is provided with the IC wafer 50, the connecting sheet 40, the multilayer structure in which the HS wafer 20 and the LS wafer 30 are stacked, and the leads 60, etc., so as to be The position of the pin 14 for connecting the external component and the back of the first stage 11 and the second stage are exposed.

Referring to FIG. 3 again, when an LS wafer 30 is disposed, the following steps are performed: a surface for subsequent bonding and fixing on the LS wafer 30 is formed with a plating layer, for example, a Ni/Au plating layer; Circuit pattern mapping; ball placement at corresponding positions on the front side of the wafer to form corresponding electrodes. Wafer-level packaging; grinding the front side of the wafer to expose the top of the ball to the outside of the top surface of the package; for example, the exposed top surface of the ball can be flush with the top surface of the package after grinding, and the like. The front side of the wafer is pre-cut to form a scribe groove. The wafer is back-grinded and back-metallized to form a corresponding electrode; for example, in a specific example, after back-grinding and back-metallization, the thickness is 6 mils, wherein the thickness of the ruthenium is 3 mils, and the thickness of the package above the cymbal is 3mil. After that, the cutting forms individual LS wafers 30, and then flips It is electrically connected to the second stage in a face-down and back-up manner.

When an HS wafer 20 is disposed, the following steps are performed: a surface for subsequent bonding and fixing on the HS wafer 20 is formed with a plating layer, such as a Ni/Pd/Au plating layer; a wafer test; a wafer back grinding and a back surface. Metallization, for example, as described in the above specific example, the thickness of the HS wafer 20 and the LS wafer 30 after the back surface polishing and the back surface metallization are 6 mils. The individual HS wafers 20 are cut to form face up, and the back side is connected downward to the first stage 11.

When an IC chip 50 is disposed, the following steps are performed: the IC wafer 50 is back-grinded, for example, 6 mils. A non-conductive adhesive 92 is applied to the back side of the IC wafer 50. Each individual IC wafer 50 is cut and formed on the top surface of the cleaned connection piece 40.

After the IC chip 50, the connecting piece 40, the HS wafer 20 and the LS wafer 30 are stacked and connected, an adhesive tape is specifically provided for curing; and the connected leads 60 are formed by bonding between the electrodes and the leads 14 of the corresponding wafer; The molding body 100; forming a plating layer at an exposed position; cutting a plurality of steps of forming individual packaging components by sawing or stamping or the like.

Example 2

4A to 4G are diagrams showing the structure of the steps of the wafer package in the present embodiment, and FIG. 5 is a flow chart showing the packaging method in the embodiment. The structure of the present embodiment is briefly described as follows, that is, a lead frame 10 (FIG. 4A) is provided, including a first stage 11 for fixedly connecting the HS wafer 20 and electrically connecting with the back surface drain D1 thereof ( 4B)) further comprising a second stage, provided with a first portion 12 and a second portion 13 for fixing the packaged LS wafers 30 connected in turn and electrically connected to the source S2 and the gate G2 of the front surface thereof, respectively. (Fig. 4C). A connecting piece 40 is electrically connected to the HS wafer 20 and the LS wafer 30, so that the high-end connecting portion 41 of the connecting piece 40 is electrically connected to the HS crystal. The source S1 of the front side of the sheet 20 is electrically connected to the back surface drain D2 of the LS wafer 30, and is electrically connected by the pin connection portion 43 of the connecting sheet 40. The interconnection pin 15 to the lead frame 10 (Fig. 4D); the difference from the embodiment 1 is that in the embodiment, the IC wafer 50 and a heat dissipation plate 71 are simultaneously disposed on the connection piece 40, for example, The heat dissipation plate 71 is made of a copper plate or the like having good thermal conductivity. For example, the heat dissipation plate 71 is disposed on the top surface of the low-end connection portion 42 of the connection piece 40 to form a good thermal contact (FIG. 4E), and the IC wafer 50 is insulatively bonded to the high-end connection of the connection piece 40. Part 41 (Fig. 4F). Then, a multilayer structure in which the IC wafer 50 and the heat dissipation plate 71, the connection sheet 40, the HS wafer 20, and the LS wafer 30 are stacked is formed, and the thickness of the heat dissipation plate 71 is designed to be compatible with the IC wafer 50 and the HS wafer 20 or the lead 14 The thickness after connecting a plurality of leads 60 is substantially equivalent. The above-mentioned multi-layer structure is encapsulated in the molding body 100, and the portions of the first stage 11 and the second stage are exposed to the outside of the bottom surface of the molding body 100, respectively. Exposing the top surface of the heat sink 71 to the outside of the top surface of the molding body 100 further helps to dissipate heat.

Referring to FIG. 5, the process of providing the lead frame 10, the HS wafer 20, the LS wafer 30, and the IC chip 50 in this embodiment is basically the same as that in the first embodiment. The difference is mainly that the heat dissipation plate 71 needs to be disposed, and After the bonding sheet 40 is bonded to the HS wafer 20 and the LS wafer 30, it is necessary to increase the step of connecting the heat dissipation plate 71 to the top surface of the connecting sheet 40 before cleaning the connecting sheet 40 to set the IC wafer 50.

Example 3

6A to 6G are diagrams showing the structure of the steps of the wafer package in the present embodiment, and Fig. 7 is a flow chart showing the packaging method in the embodiment. The structure of the present embodiment is briefly described as follows, that is, a lead frame 10 (FIG. 6A) is provided, including a first stage 11 for fixedly connecting the HS wafer 20 and electrically connecting with the back surface D1 of the back surface thereof. (Fig. 6B); further comprising a second stage, provided with a first portion 12 and a second portion 13 for fixing the flipped package LS wafer 30 and forming electrical properties with the front source S2 and the gate G2, respectively Connection (Fig. 6C). A connecting piece 40 is electrically connected to the HS wafer 20 and the LS wafer 30, so that the high-end connecting portion 41 of the connecting piece 40 is electrically connected to the source S1 of the front surface of the HS wafer 20, and the low-end connection of the connecting piece 40 is connected. The portion 42 is electrically connected to the upward back drain D2 of the LS wafer 30, and is further electrically connected to the interconnect pin 15 of the lead frame 10 by the pin connection portion 43 of the connecting piece 40 (FIG. 6D). An IC chip 50 is insulatively bonded to the high-side connecting portion 41 of the connecting piece 40, and a lead 60 connection between the IC chip 50, the HS wafer 20 and the lead 14 is formed (FIG. 6E); and in Embodiment 1 The difference is that in the present embodiment, when the multilayer structure of the IC wafer 50, the connecting sheet 40, the HS wafer 20 and the LS wafer 30 is stacked together using the molding body 100, the exposed structure of the bottom surface of the molding body 100 is unchanged. Instead, a notch 101 is formed on the top surface of the molding body 100 such that a portion of the low-end connecting portion 42 on the connecting piece 40 is exposed from the notch 101 (Fig. 6F). A heat dissipating plate 72 is provided, for example, a copper plate or the like which has good thermal conductivity. The bottom of the heat dissipating plate 72 is provided with a protruding member (FIG. 6G) which can be inserted into the notch 101 of the molding body 100. And having sufficient thickness to connect to the tab 40 to form a thermally conductive contact. The top of the heat dissipation plate 72 is left on the top surface (6H) of the molding body 100, so that the heat dissipation area can be set as large as possible without exceeding the area of the molding body 100 to improve the heat dissipation effect.

Referring to FIG. 7 , the process of providing the lead frame 10 , the HS wafer 20 , the LS wafer 30 , and the IC chip 50 in this embodiment is basically the same as that in Embodiment 1. The difference is mainly that the heat dissipation plate 72 needs to be disposed, and After the packaged multilayer structure forms the molded body 100 with the notches 101, it is necessary to increase the step of inserting the protruding members of the heat dissipation plate 72 into the notch 101 and the top surface of the connecting piece 40 therein to achieve connection and thermal contact.

Example 4

8A to 8G are diagrams showing the structure in the respective steps of the wafer package in the present embodiment, and FIG. 9 is a flow chart showing the packaging method in the present embodiment. The structure of the present embodiment is briefly described as follows, that is, a lead frame 10 (FIG. 8A) is provided, including a first stage 11 for fixedly connecting the HS wafer 20 and electrically connecting with the back surface D1 of the back surface ( 8B)) further comprising a second stage, provided with a first portion 12 and a second portion 13 for fixing the packaged LS wafer 30 connected to the flip and electrically connected to the source S2 and the gate G2 of the front surface thereof respectively (Fig. 8C). A connecting piece 40 is electrically connected to the HS wafer 20 and the LS wafer 30, so that the high-end connecting portion 41 of the connecting piece 40 is electrically connected to the source S1 of the front surface of the HS wafer 20, and the low-end connection of the connecting piece 40 is connected. The portion 42 is electrically connected to the upper back drain D2 of the LS wafer 30, and is further electrically connected to the interconnect pin 15 of the lead frame 10 by the pin connection portion 43 of the connecting piece 40 (Fig. 8D); The difference in Example 1 is that the connecting piece 40 in this embodiment has a different structure in which the thickness of the high-end connecting portion 41 (and the pin connecting portion 43) is smaller than the thickness of the low-end connecting portion 42 (Fig. 8D). The thickness of the low-side connecting portion 42 is designed to insulably bond the IC wafer 50 to the high-end connecting portion 41 of the connecting piece 40, and connect a plurality of the IC wafer 50 and the HS wafer 20 or the lead 14. The thickness after the lead 60 is substantially equal (Fig. 8E). Then, after the plastic package 100 encapsulates the above-mentioned IC chip 50, the connection piece 40, the HS wafer 20 and the LS wafer 30, the exposed portion of the bottom surface of the plastic package 100 is unchanged, and the connection piece 40 is also made. The top surface of the lower end connecting portion 42 is exposed outside the top surface of the molding body 100 to further assist in heat dissipation. The three portions of the connecting piece 40 in this embodiment may be integrally formed or formed by being assembled or joined.

Referring to FIG. 9, the process of providing the lead frame 10, the HS wafer 20, the LS wafer 30, and the IC chip 50 in the present embodiment and packaging the same is basically the same as in the first embodiment. Consistently, the main difference is that the top surface of the high-end connecting portion 41 of the connecting piece 40 needs to be covered with tape or the like before packaging, so that it can be exposed after being packaged.

The fabrication process of each of the wafers in the present invention can be carried out according to the usual means in the art. In the present invention, the package structure and the packaging method in which the multi-chips are stacked and connected by the connecting sheets 40 can be applied to other component packages in addition to the two MOSFET chips and one IC chip 50 described above. For example, packaging high voltage IGBT wafers (insulated gate bipolar transistors), high voltage controllers, or for packaging a greater number of wafers or more wafer stacks, and the like.

Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the description Various modifications and alterations of the present invention will become apparent to those skilled in the <RTIgt; Therefore, the scope of the invention should be limited by the scope of the appended claims.

10‧‧‧ lead frame

14‧‧‧ pin

20‧‧‧HS wafer

30‧‧‧LS wafer

40‧‧‧Connecting piece

50‧‧‧ IC chip

60‧‧‧ lead

Claims (19)

A package structure of a multi-wafer stack, comprising: a lead frame provided with a first stage, a second stage and a plurality of pins spaced apart from each other, the second stage further being separated from each other a first portion and a second portion; a first wafer having a back electrode disposed downwardly and electrically connected to the first stage; and a second wafer having a front electrode disposed downwardly and electrically connected to the second On the first portion and the second portion of the stage, some of the front electrodes of the second wafer are connected to the first portion, and some of the front electrodes are connected to the second portion; the connecting piece has a bottom surface that is electrically connected to the first a plurality of front electrodes disposed upwardly of the wafer, and a back electrode disposed upwardly of the second wafer; a third wafer having a back surface disposed downwardly and insulatively coupled to a top surface of the connecting sheet; and a plastic package stacked in sequence a third wafer of a multilayer structure, a tab, a first wafer and a second wafer, a lead frame, and a lead wire correspondingly connected between the wafer electrode and the wafer electrode or between the wafer electrode and the lead, And the pin portion and a first external element the stage the stage and a second back surface is exposed outside at least a portion of the plastic body. The package structure of the multi-wafer stack according to claim 1, wherein: the first wafer is an HS wafer as a high-side MOSFET chip, and a drain disposed on a back surface thereof is electrically connected to the first stage; The second wafer is a LM wafer that is a low-end MOSFET wafer and is wafer-level packaged. The front surface of the LSI wafer is electrically connected to the first portion of the second wafer stage, and the gate electrode is electrically connected to the front surface of the second wafer. On the second portion of the second stage; the bottom surface of the connecting piece is electrically connected to the source of the front surface of the HS wafer and the drain of the back surface of the LS chip for electrically connecting the two electrodes; The third wafer is an IC chip as a controller, the bottom surface of which is insulatedly connected to the top surface of the connecting sheet, and the plurality of electrodes on the top surface of the third wafer are respectively connected to corresponding electrodes on other wafers by wires. Or a corresponding pin on the lead frame; a plurality of electrodes on the front side of the HS wafer or on the back side of the LS wafer that are not shielded by the connecting piece, and are also respectively connected to corresponding pins on the other electrodes or corresponding pins on the lead frame by leads . The package structure of the multi-wafer stack according to claim 1, wherein the package structure is further provided with a heat dissipation plate before the molding body is formed, and the heat dissipation plate and the third wafer are respectively connected to the top surface of the connection piece. Above, the heat dissipation plate is in thermal contact with the connecting piece, and heat is dissipated by the surface of the heat dissipation plate exposed outside the top surface of the molding body. The package structure of the multi-wafer stack according to claim 1, wherein the package structure is further provided with a heat dissipation plate after forming the plastic package; the top surface of the plastic package is further formed with a notch, the heat dissipation plate a bottom portion is inserted into the notch to be connected to a top surface of the connecting piece, and the heat dissipating plate and the connecting piece are formed The heat-conducting contact further dissipates heat by the top of the heat-dissipating plate remaining outside the top surface of the molding body. The package structure of the multi-wafer stack according to any one of claims 1 to 4, wherein the connecting piece is provided with a high-end connection portion connected to the first wafer, and is connected to the second wafer. a low-end connecting portion; the high-end connecting portion and the low-end connecting portion of the connecting piece have the same or different thickness; the sum of the thickness of the high-end connecting portion, the first wafer, and the first stage, and the low-end connecting portion, The sum of the thicknesses of the second wafer and the second stage is equal, so that the top surface of the connecting sheet is horizontally connected to stably place the third wafer. The package structure of the multi-wafer stack according to claim 5, wherein the third wafer is connected to the upper end portion of the connecting piece or the lower portion of the low-end connecting portion, and the high-end connecting portion Or the top surface of the thicker portion of the lower end connecting portion is exposed outside the molded body to achieve heat dissipation. The package structure of the multi-wafer stack according to claim 6, wherein: a plurality of contacts for partially adjusting the thickness of the connecting piece are formed on the connecting piece, and the contact is formed by recessing the top surface of the connecting piece A structure that does not penetrate the blind hole and at the same time causes the bottom surface of the connecting piece to protrude downward. The package structure of the multi-wafer stack according to claim 5, wherein: The connecting piece is further provided with a lead connecting portion electrically connected to the interconnecting pin provided by the lead frame; the lead connecting portion, the high end connecting portion and the low end connecting portion are formed by integral molding or by assembling the connection The connecting piece of the connecting piece and the connecting pin are correspondingly provided with a locking mechanism for preventing a change in position of the connecting piece during assembly and packaging. The package structure of the multi-wafer stack according to claim 1, wherein: between the first wafer and the first stage, between the second wafer and the second stage, the connecting piece and The conductive connection between the first wafer and the second wafer is achieved by solder or conductive epoxy glue disposed between the interconnected surfaces; the third wafer is insulatively connected to the connecting piece, It is realized by a non-conductive adhesive glue disposed on the back surface of the third wafer. The package structure of the multi-wafer stack according to claim 1, wherein the connecting piece is a copper piece. A multi-wafer stack packaging method comprising the steps of: providing a lead frame provided with a first stage, a second stage and a plurality of pins spaced apart from each other, the second stage being further provided a first portion and a second portion spaced apart from each other; the back electrode of the first wafer is disposed downwardly and electrically connected to the first stage; the second wafer is inverted such that the front electrode is disposed downwardly and electrically connected On the first portion and the second portion of the second stage, the second wafer is Some front electrodes are connected to the first portion, and some of the front electrodes of the second wafer are connected to the second portion; the bottom surface of the connecting sheet is simultaneously electrically connected to some of the front electrodes arranged upwardly of the first wafer, and the second wafer is arranged upward On the back electrode; the back surface of the third wafer is arranged downwardly and insulatively connected to the top surface of the connecting sheet; and the third wafer, the connecting sheet, the first wafer and the first layer which are stacked in a multilayer structure are formed After the two wafers, the lead frame, and the corresponding leads connected between the wafer electrodes and the wafer electrodes or between the wafer electrodes and the leads are packaged, the molded body is cut to form a separate component; and the pins are connected to the external components. The portion and at least a portion of the first stage and the second stage back are exposed to the outside of the molding. The method of packaging a multi-wafer stack according to claim 11, wherein: the packaging method further connects a heat sink disposed on the top surface of the connecting sheet before the molding, so that the heat sink Forming a heat-conducting contact with the connecting piece, thereby dissipating heat by the surface of the heat-dissipating plate exposed outside the top surface of the molding body. The method of packaging a multi-wafer stack according to claim 11, wherein: the packaging method forms a notch on a top surface of the package formed by the package, and inserts a bottom of the disposed heat dissipation plate into the gap To connect to the top surface of the connecting piece and form a heat-conducting contact between the heat-dissipating plate and the connecting piece, thereby dissipating heat by the top of the heat-dissipating plate remaining outside the top surface of the molding body. A method of packaging a multi-wafer stack according to claim 11 of the patent application, Medium: the connecting piece is provided with a high-end connecting portion connected to the first wafer, and a low-end connecting portion connected to the second wafer; the high-end connecting portion and the low-end connecting portion of the connecting piece have the same or different thickness; When the thickness of the high-end connecting portion and the low-end connecting portion of the connecting piece are different, the third wafer is connected to the high-end connecting portion or the lower-end connecting portion of the connecting piece, the high-end connecting portion or the low end. The top surface of the thicker portion of the connecting portion is exposed outside the molded body for heat dissipation. The method of packaging a multi-wafer stack according to claim 11, wherein: between the first wafer and the first stage, between the second wafer and the second stage, the connecting piece and The conductive connection between the first wafer and the second wafer is achieved by solder or conductive epoxy glue disposed between the interconnected surfaces; the third wafer is insulatively connected to the connecting piece, It is realized by a non-conductive adhesive glue disposed on the back surface of the third wafer. The method of packaging a multi-wafer stack according to claim 11, wherein: a plurality of contacts for partially adjusting the thickness of the connecting piece are formed on the connecting piece, and the connecting piece is formed by punching The top surface is recessed downward to form a blind hole that does not penetrate and at the same time causes the bottom surface of the connecting piece to protrude downward. The method of encapsulating a multi-wafer stack according to any one of claims 11 to 16, wherein: The first wafer is formed by forming a plating layer on the surface of the wafer for connecting other components, performing wafer testing, wafer back grinding and back metallization to control the thickness of the first wafer and forming a corresponding back surface. An electrode; cutting forms a separate first wafer; thereafter, connecting the first wafer back side to the first stage. The method of packaging a multi-wafer stack according to claim 17, wherein the second wafer is formed by forming a plating layer on a surface of the ruthenium for connecting other components; performing wafer testing and Circuit pattern mapping; ball placement at corresponding positions on the front side of the cymbal to form corresponding front electrodes; wafer level packaging to form a package; grinding on the front side of the wafer to expose the top of the ball to the outside of the package; pre-cutting of the front side of the wafer Forming a dicing groove; wafer back grinding and back metallization to control the thickness of the second wafer and forming a corresponding back electrode; cutting to form each individual second wafer; thereafter, flipping the second wafer to face down Connected to the second stage. The method of encapsulating a multi-wafer stack according to claim 18, wherein: the third wafer is formed by: back grinding of the wafer; coating the back side of the IC wafer with a non-conductive adhesive; cutting forming Each of the independent third wafers; thereafter, the third wafer is bonded to the top surface of the connecting sheet that has been connected to the first wafer and the second wafer; and the third wafer, the connecting sheet, the first wafer, and the second wafer stack After forming the multilayer structure, the following process is further performed: bonding the tape, curing; between the corresponding wafer electrode and the wafer electrode, and between the wafer electrode and the lead Bonding to form leads; forming a plastic body; forming a plating layer at a position exposed to the outside of the plastic package; and finally cutting to form individual package components.