TWI546969B - Semiconductor device having deep implantation region and method of fabricating same - Google Patents

Description

Semiconductor device having deep implanted region and method of fabricating the same

The present disclosure relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a deep implant region and a method of fabricating the same.

A Lateral Diffused Metal-Oxide-Semiconductor (LDMOS) device is a high voltage device widely used in display devices, portable devices, and most other applications. The design goals of the LDMOS device include a high breakdown voltage and a low specific on-resistance.

The specific on-resistance of the LDMOS device is limited by one of the doping concentrations of one of the grade regions of the device. As the doping concentration of the graded region decreases, the specific on-resistance increases.

According to an embodiment of the present disclosure, a semiconductor device includes: a substrate having a first conductivity type; a high voltage well having a second conductivity type disposed in the substrate; and a source well having the first Conductive and configured in a high voltage well; a drift region disposed in a high voltage well and separated from the source well; and a deep implanted region having a first conductivity type and located in a high voltage well located Between the source well and the drift region.

According to another embodiment of the present disclosure, a method of fabricating a semiconductor device includes: providing a substrate having a first conductivity type; forming a high voltage well having a second conductivity type in the substrate; forming a first The source of the conductivity type is in the high voltage well; forming a drift region in the high voltage well, and the drift region is separated from the source well; and forming a deep implant region having the first conductivity type in the high voltage well, and Between the source well and the drift region.

Reference will now be made in detail to the embodiments, examples of which are illustrated in the drawings. Where possible, the drawings will use the same reference numerals to refer to the same or similar parts.

FIG. 1A schematically shows a top view of an LDMOS device 10 in accordance with an embodiment. Fig. 1B is a cross-sectional view of the LDMOS device 10 taken along line BB' of Fig. 1A. Fig. 1C is a cross-sectional view of the LDMOS device 10 taken along line C-C' of Fig. 1A.

As shown in FIG. 1A-1C, the LDMOS device 10 includes: a P-type substrate 100; a high-voltage N-well (HVNW) 105 formed in the substrate 100; a first P-well 110, Formed in the HVNW 105; a second P-well 115 formed outside of the HVNW 105 and adjacent to the HVNW 105; a drift region 120 formed in the HVNW 105 on one side of the first P-well 110 (eg, the right side) And being separated from the first P well 110; a P-type deep implant region 125, formed in the HVNW 105, between the first P well 110 and the drift region 120; and an insulating layer 130 disposed on the substrate 100 on. The drift region 120 includes a plurality of first segments 120a and a second segment 120b that are alternately arranged. Each of the first sections 120a includes a P top end area 122 and an N staging area 124 disposed on the P top end area 122. Each second section 120b includes an N staging area 124. The insulating layer 130 may be composed of a field oxide (FOX). Hereinafter, the insulating layer 130 is referred to as an FOX layer 130. The FOX layer 130 includes a first FOX portion 131 spaced apart from the drift region 120, a second FOX portion 132 covering the drift region 120, and an HVNW 105 covering the first P well 110 and the second P well 115. A portion of the third FOX portion 133, and a fourth FOX portion 134 that covers a side (eg, left side) edge portion of the second P-well 115.

The LDMOS device 10 also includes a gate oxide layer 140 disposed between the edge portion of the substrate 100 on the side (ie, the right side) of the first P well 110 and the edge portion (eg, the left side) of the second FOX portion 132. a gate layer 145 disposed on the gate oxide layer 140; a plurality of spacers 150 disposed on sidewalls of the gate layer 145; a first N ⁺ region 155 formed in the HVNW 105, located at the first between FOX FOX portion 131 and the second portion 132; a second N ⁺ region 160 is formed on the side of a gate layer 145 (e.g. left) edge of the first portion adjacent to the P-well 110; and a first P ⁺ a region 165 formed in the first P well 110 adjacent to the second N ⁺ region 160; and a second P ⁺ region 170 formed in the second P well 115 at the third FOX portion 133 and the fourth FOX Between the sections 134. The gate layer 145 includes a polysilicon layer 146 and a tungsten germanium layer 147 formed on the polysilicon layer 146. The first N ⁺ region 155 constitutes a drain region of an LDMOS device 10. The second N ⁺ region 160 and the first P ⁺ region 165 constitute a source region of an LDMOS device 10. The second P ⁺ region 170 constitutes a body region of an LDMOS device 10. The first P well 110 constitutes a source well of an LDMOS device 10. The second P well 115 constitutes a body well of an LDMOS device 10.

The LDMOS device 10 further includes an interlayer dielectric (ILD) layer 180 formed on the substrate 100, and a contact layer 190 formed on the ILD layer 180. The contact layer 190 includes a plurality of isolated contacts for conductively contacting different portions of the structure formed in the substrate 100 via different openings formed in the ILD layer 180.

In the LDMOS device 10 according to the present embodiment, a P-type deep implant region 125 is formed in a region between the first P well 110 and the drift region 120 to assist in the formation of an all-vacancy region. Therefore, the doping concentration in the P top region 122 can be reduced, or the doping concentration in the N staging region 124 can be increased, which has the effect of lowering the specific on-resistance of the LDMOS device 10.

2A-14B schematically show the manufacturing process of the LDMOS device 10 according to the 1A-1C diagram of an embodiment. 2A, 3A, 4A, ..., 14A schematically show a partial cross-sectional view of the LDMOS device 10 along the line BB' of Fig. 1A during the steps of the manufacturing process of the LDMOS device 10. 2B, 3B, 4B, ..., 14B schematically show a partial cross-sectional view of the LDMOS device 10 along the line C-C' of Fig. 1A during the steps of the manufacturing process of the LDMOS device 10.

First, referring to FIGS. 2A and 2B, a substrate 200 having a first conductivity type is provided, and a deep well 205 having a second conductivity type is formed in the substrate 200 and extends downward from the upper surface of a substrate 200. In the embodiment shown, the first conductivity type is P-type and the second conductivity type is N-type. Hereinafter, the deep well 205 is referred to as a high voltage N well (HVNW) 205. The substrate 200 may be composed of a P-type body germanium material, a P-type epitaxial layer or a P-type silicon-on-insulator (SOI) material. The HVNW 205 can be formed by a photolithography process defining a region where the HVNW 205 is to be formed; an ion implantation process for implanting an N-type at a concentration of about 10 ¹¹ to 10 ¹³ atoms/cm ² . The dopant (e.g., phosphorus or arsenic) is in a defined region; and a heating process drives the implanted dopant to a predetermined depth.

Referring to FIGS. 3A and 3B, a first P well 210 is formed in the HVNW 205 near the edge portion of an HVNW 205. A second P well 215 is formed in the substrate 200 outside the edge portion of the HVNW 205 and adjacent to the edge portion of the HVNW 205. The first P well 210 and the second P well 215 can be formed by a lithography process defining an area where the first P well 210 and the second P well 215 are to be formed; an ion implantation process to approximately At a concentration of 10 ¹² to 10 ¹⁴ atoms/cm ² , a P-type dopant (for example, boron) is implanted in a defined region; and a heating process drives the implanted dopant to a predetermined depth.

Referring to Figures 4A and 4B, a P-top implant region 222' is formed in HVNW 205 in a region corresponding to the first segment 120a shown in Figure 1A. No P top implant region 222' is formed in the region corresponding to the second segment 120b shown in FIG. 1A. The P top implant region 222' can be formed by a photolithography process defining a first segment 120a; and an ion implantation process at a concentration of about 10 ¹¹ to 10 ¹⁴ atoms/cm ² . A P-type dopant (e.g., boron) enters the first section 120a.

Referring to Figures 5A and 5B, an N-graded implant region 224' is formed in HVNW 205 in a region corresponding to both the first segment 120a and the second segment 120b shown in Figure 1A. The N-graded implanted region 224' can be formed by a lithography process defining a first segment 120a and a second segment 120b; and an ion implantation process to be about 10 ¹¹ to 10 ¹⁴ atoms/ At a concentration of cm ² , an N-type dopant (e.g., phosphorus or arsenic) is implanted in the first section 120a and the second section 120b.

Referring to FIGS. 6A and 6B, a P-type implant region 225' is formed in the HVNW 205 near the right edge of a first P-well 210. The P-type implant region 225' can be formed by a photolithography process defining a region where the P-type implant region 225' is to be formed; and an ion implantation process to be approximately 10 ¹² to 10 ¹⁴ atoms At a concentration of /cm ² , a P-type dopant (for example, boron) is implanted in a defined region. The implantation energy of the ion implantation process for forming the P-type implant region 225' is greater than the implantation energy of the ion implantation process for forming the P-top implant region 222', and is used to form the N-level implant. The energy of the ion implantation process of region 224'.

Referring to Figures 7A and 7B, an insulating layer in the form of a field oxide (FOX) layer 230 is formed on the upper surface of the substrate 200. The FOX layer 230 includes a first FOX portion 231 covering a right edge portion of a HVNW 205, and a second FOX portion 232 covering a P top implant region 222' and an N graded implant region 224'; a third FOX portion 233, covering a left edge portion of an HVNW 205 between the first P well 210 and the second P well 215; and a fourth FOX portion 234 covering a left edge portion of the second P well 215.

The FOX layer 230 can be formed by a deposition process for depositing a tantalum nitride layer, a photolithography process for defining a region where the FOX layer 230 is to be formed, and an etching process for removing nitrogen in a defined region. a ruthenium layer; and a thermal oxidation process to form the FOX layer 230 in a defined region. During the thermal oxidation process used to form the FOX layer 230, the P-type dopant in the P-top implant region 222', the P-type dopant in the P-type implant region 225', and the N-graded implant region 224' The N-type dopants are driven to a predetermined depth in the HVNW 205 to form a P-tip region 222, a P-type deep implant region 225, and an N-gradation region 224, respectively. The depth of the P tip region 222 may be approximately 0.5 μm to 3 μm. The depth of the N staging area 224 may be approximately 0.1 μm to 1 μm. The width and depth of the P-type deep implanted region 225, the doping concentration in the P-type deep implanted region 225, the distance between the P-type deep implanted region 225 and the first P-well 210, and the P-type deep implanted region. The distance between 225 and P top region 222 and N staging region 224 is a variable determined in view of various design considerations, such as P top region 222, N graded region 224, and doping concentration in HVNW 205, and LDMOS device 10 Structure and / or application.

Referring to Figures 8A and 8B, a gate oxide layer 240 is formed on the surface portion of the structures of Figures 7A and 7B which are not covered by the FOX layer 230. That is, the gate oxide layer 240 is formed between the first FOX portion 231 and the second FOX portion 232, between the second FOX portion 232 and the third FOX portion 233, and at the third FOX portion 233 and the fourth portion. Between the FOX section 234. The gate oxide layer 240 can be formed by a sacrificial oxidation process for forming a sacrificial oxide layer, a clean process for removing the sacrificial oxide layer, and an oxidation process for forming a gate oxide. Layer 240.

Referring to FIGS. 9A and 9B, a gate layer 245 is formed on the gate oxide layer 240 to cover a left portion of a second FOX portion 232 and a right portion of a first P well 210. The gate layer 245 can include a polysilicon layer 246 and a tungsten germanium layer 247 formed on the polysilicon layer 246. The thickness of the gate layer 245 may be approximately 0.1 μm to 0.7 μm. The gate layer 245 can be formed by a deposition process for depositing a polysilicon layer and a tungsten germanium layer on the entire substrate; a photolithography process defining an area where the gate layer 245 is to be formed; The etching process removes the polysilicon layer and the tungsten germanium layer outside the defined area.

Referring to FIGS. 10A and 10B, a plurality of spacers 250 are formed on both sides of the gate layer 245. The spacer 250 may be a tetraethoxy decane (TEOS) oxide film. The spacer 250 can be formed by a deposition process for depositing a TEOS oxide film, a photolithography process for defining a region of the spacer 250 to be formed, and an etching process for removing TEOS oxidation outside the defined region. membrane. After the spacers 250 are formed, the gate oxide layer 240 except for portions under the gate layer 245 and the spacers 250 is removed by etching.

Referring to FIGS. 11A and 11B, a first N ⁺ region 255 is formed in the HVNW 205 between the first FOX portion 231 and the second FOX portion 232, and a second N ⁺ region 260 is formed in the first The P well 210 is adjacent to the left edge portion of a gate layer 245 and below a left spacer 250. The first N ⁺ region 255 and the second N ⁺ region 260 may be formed by a photolithography process defining a region where the first N ⁺ region 255 and the second N ⁺ region 260 are to be formed; and an ion cloth The implant process implants an N-type dopant (e.g., phosphorus or arsenic) in a defined region at a concentration of about 10 ¹⁵ to 10 ¹⁶ atoms/cm ² .

Referring to FIGS. 12A and 12B, a first P ⁺ region 265 is formed in the first P well 210 adjacent to the second N ⁺ region 260, and a second P ⁺ region 270 is formed in the second P well 215. Located between the third FOX portion 233 and the fourth FOX portion 234. The first P ⁺ region 265 and the second P ⁺ region 270 may be formed by a photolithography process defining an area where the first P ⁺ region 265 and the second P ⁺ region 270 are to be formed; and an ion cloth The implant process implants a P-type dopant (e.g., boron) in a defined region at a concentration of about 10 ¹⁵ to 10 ¹⁶ atoms/cm ² .

Referring to Figures 13A and 13B, an InterLayer Dielectric (ILD) layer 280 is formed on the entire surface of the structure of Figures 12A and 12B. The ILD layer 280 includes: a first opening portion 281 vertically aligned with the first N ⁺ region 255; a second opening portion 282 vertically aligned with the gate layer 245; and a third opening portion 283 vertically Aligned with the second N ⁺ region 260; a fourth opening portion 284 that is vertically aligned with the first P ⁺ region 265; and a fifth opening portion 285 that is vertically aligned with the second P ⁺ region 270. The ILD layer 280 may include Undoped Silicate Glass (USG) and/or Borophosphosilicate glass (BPSG). The thickness of the ILD layer 280 may be from 0.5 μm to 2 μm. The ILD layer 280 can be formed by a deposition process of depositing a layer of USG and/or BPSG, a photolithography process defining an area in which the ILD layer 280 is to be formed, and an etching process to remove the defined area. The USG and/or BPSG of this layer are externally formed to form openings 281 to 285.

Referring to Figures 14A and 14B, a contact layer 290 is formed on the structures of Figures 13A and 13B. The contact layer 290 includes: a first contact portion 291 contacting the first N ⁺ region 255; a second contact portion 292 contacting the gate layer 245; a third contact portion 293 contacting the second N ⁺ region 260 and the first Both P ⁺ regions 265; and a fourth contact portion 294 that contacts the second P ⁺ region 270. Contact layer 290 can be comprised of any conductive metal such as aluminum, copper, or aluminum copper alloy. The contact layer 290 can be formed by a deposition process for depositing a metal layer, a photolithography process for defining a region where the contact layer 290 is to be formed, and an etching process for removing a metal layer outside the defined region. .

Fig. 15 is a diagram showing the characteristics of the LDMOS device 10 having the P-type deep implant region 125 as shown in Figs. 1A-1C and the conventional device constructed as a comparative example. Conventional devices do not include a P-type deep implant region 125. In Fig. 15, a drain-source voltage V _{DS is} changed from 0 to 800 V, and a gate-source voltage V _GS and a body-source voltage V _BS are maintained at 0V. As shown in Fig. 15, the off-breakdown voltage of both the LDMOS device 10 and the conventional device exceeds 700V. Therefore, the LDMOS device 10 has the same cut-off voltage as that of the conventional device.

Fig. 16 is a diagram showing the characteristics of the LDMOS device 10 and the conventional device. In Fig. 16, V _{DS is} changed from 0 to 2V, and V _GS is maintained at 20V. As shown in Fig. 16, for the same value of V _DS , one of the drain-source current I _DS of the LDMOS 10 is higher than that of the conventional device. Thus, LDMOS 10 has a lower on-resistance than conventional devices, while having the same cut-off voltage as conventional devices.

Although the above embodiments are directed to the N-type LDMOS device 10 and the second A-13B shown in FIGS. 1A and 1B, the skilled person will now understand that the disclosed concept is equally suitable. A P-type LDMOS device. Those skilled in the art will also appreciate that the disclosed concepts are suitable for other semiconductor devices and methods of fabricating the same, such as insulated gated dual carrier transistor (IGBT) devices and diodes.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

B-B'‧‧‧ line
C-C'‧‧‧ line
I _DS ‧‧‧汲-source current
V _BS ‧‧‧ body-source voltage
V _DS ‧‧‧汲-source voltage
V _GS ‧‧ ‧ gate-source voltage
10‧‧‧LDMOS device/LDMOS
100‧‧‧Substrate
105‧‧‧High Voltage N Well (HVNW)
110‧‧‧First P well
115‧‧‧Second P well
120‧‧‧ Drift area
120a‧‧‧First section
120b‧‧‧second section
122‧‧‧P top area
124‧‧‧N graded area
125‧‧‧P type deep planting area
130‧‧‧FOX layer / insulation
131‧‧‧First FOX Department
132‧‧‧The second FOX department
133‧‧‧ Third FOX Department
134‧‧‧Fourth FOX Department
140‧‧‧ gate oxide layer
145‧‧ ‧ gate layer
146‧‧‧Polysilicon layer
147‧‧‧twinned tungsten layer
150‧‧‧ spacer
155‧‧‧First N ⁺ area
160‧‧‧Second N ⁺ area
165‧‧‧First P ⁺ area
170‧‧‧Second P ⁺ area
180‧‧‧Interlayer dielectric (ILD) layer
190‧‧‧Contact layer
200‧‧‧Substrate
205‧‧‧High Voltage N Well (HVNW) / Deep Well
210‧‧‧First P Well
215‧‧‧Second P well
222‧‧‧P top area
222'‧‧‧P top planting area
224‧‧‧N graded area
224'‧‧‧N graded planting area
225‧‧‧P type deep planting area
225'‧‧‧P type planting area
230‧‧‧ Field oxide (FOX) layer
231‧‧‧First FOX Department
232‧‧‧Second FOX Department
233‧‧‧ Third FOX Department
234‧‧‧Fourth FOX Department
240‧‧ ‧ gate oxide layer
245‧‧ ‧ gate layer
246‧‧‧ Polycrystalline layer
247‧‧‧Tungsten-tungsten layer
250‧‧‧left spacer
250‧‧‧ spacer
255‧‧‧First N ⁺ area
A second N ⁺ region 260‧‧‧
265‧‧‧First P ⁺ area
270‧‧‧Second P ⁺ area
280‧‧‧Interlayer dielectric (ILD) layer
281‧‧‧ first opening
282‧‧‧second opening
283‧‧‧The third opening
284‧‧‧fourth opening
285‧‧‧ fifth opening
290‧‧‧Contact layer
291‧‧‧First contact
292‧‧‧Second contact
293‧‧ Third contact
294‧‧‧Fourth Contact

Figure 1A is a top plan view of an LDMOS device in accordance with an embodiment. Fig. 1B is a cross-sectional view of the LDMOS device taken along line B-B' of Fig. 1A. Fig. 1C is a cross-sectional view of the LDMOS device taken along line C-C' of Fig. 1A. 2A-14B schematically shows the manufacturing process of the LDMOS device according to the 1A-1C diagram of an embodiment. Fig. 15 is a diagram showing the characteristics of the LDMOS device of Fig. 1A-1C and the conventional device constructed as a comparative example. Fig. 16 is a diagram showing the characteristics of the LDMOS device of Fig. 1A-1C and the conventional device constructed as a comparative example.

B-B'‧‧‧ line

C-C'‧‧‧ line

10‧‧‧LDMOS device/LDMOS

105‧‧‧High Voltage N Well (HVNW)

110‧‧‧First P well

115‧‧‧Second P well

120‧‧‧ Drift area

120a‧‧‧First section

120b‧‧‧second section

125‧‧‧P type deep planting area

155‧‧‧First N ⁺ area

Claims (18)

A semiconductor device comprising: a substrate having a first conductivity type; a high voltage well having a second conductivity type disposed in the substrate; a source well having the first conductivity type and disposed in a high voltage well; a drift region disposed in the high voltage well and spaced apart from the source well; and a deep implant region having the first conductivity type and disposed in the high voltage well at The source well is between the drift region. The semiconductor device of claim 1, wherein the drift region comprises a plurality of alternately arranged first and second segments, each of the first segments comprising a top region having the first conductivity type And a gradation area having the second conductivity type formed on the top end of the top end region, and each of the second sections includes only the gradation area. The semiconductor device according to claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The semiconductor device according to claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type. The semiconductor device of claim 1, wherein the source well is disposed adjacent to an edge portion of the high voltage well, and the device further includes a body well having the first conductivity type, the body well It is disposed outside the high voltage well and is adjacent to the edge portion of the high voltage well. The semiconductor device of claim 5, further comprising an insulating layer disposed on the substrate, the insulating layer comprising: a first insulating portion spaced apart from the drift region; a second insulating portion, Covering the drift region; a third insulating portion covering the edge portion of the high voltage well; and a fourth insulating portion covering an edge portion of the body well. The semiconductor device of claim 6, further comprising: a gate oxide layer disposed on the substrate between the source well and the second insulating portion; and a gate layer, configured On the gate oxide layer. The semiconductor device of claim 7, further comprising: a source region disposed in the source well; a drain region disposed in the high voltage well and spaced apart from the drift region; A body region disposed in the body well. The semiconductor device of claim 8, further comprising: an interlayer dielectric layer disposed on the substrate; and a contact layer disposed on the interlayer dielectric layer. A method of fabricating a semiconductor device, the method comprising: providing a substrate having a first conductivity type; forming a high voltage well having a second conductivity type in the substrate; forming a source having the first conductivity type a well in the high voltage well; forming a drift region in the high voltage well, and the drift region is spaced apart from the source well; and forming a deep implant region having the first conductivity type in the high voltage well, And between the source well and the drift region. The method of claim 10, wherein the first conductivity type is a P type and the second conductivity type is an N type. The method of claim 10, wherein the first conductivity type is an N type and the second conductivity type is a P type. The method of claim 10, wherein the drift region comprises a plurality of alternately arranged first and second segments, and wherein the step of forming the drift region in the high voltage well comprises: only Forming a top end region having the first conductivity type in the first segment; and forming a classification region having the second conductivity type in both the first segment and the second segments, A graded region is formed on the top end of the top end region in each of the first segments. The method of claim 10, wherein the source well is formed adjacent to an edge portion of the high voltage well, and the method further comprises: forming a body well having the first conductivity type, The edge portion of the high voltage well is external to the edge portion of the high voltage well. The method of claim 14, further comprising forming an insulating layer disposed on the substrate, comprising: forming a first insulating portion spaced apart from the drift region; forming a portion covering the drift region a second insulating portion; a third insulating portion covering the edge portion of the high voltage well; and a fourth insulating portion covering an edge portion of the body well. The method of claim 15, further comprising: forming a gate oxide layer on the substrate between the source well and the second insulating portion; and forming a gate layer at the gate On the pole oxide layer. The method of claim 16, further comprising: forming a source region in the source well; forming a drain region in the high voltage well, and separating the drain region from the drift region; And forming a body region disposed in the body well. The method of claim 17, further comprising: forming an interlayer dielectric layer on the substrate; and forming a contact layer on the interlayer dielectric layer.