TWI517295B - Semiconductor device having P top layer and N energy level and manufacturing method thereof - Google Patents

Description

Semiconductor device having P top layer and N energy level and manufacturing method thereof

Embodiments of the present invention relate to a semiconductor device, and more particularly to a metal oxide semiconductor device and a method of fabricating the same.

A diffused metal oxide semiconductor (DMOS) device is characterized by a source region and a rear gate region that are simultaneously diffused. The transistor channel is formed by the difference in the two diffusions and is not implanted separately, which results in a shortened channel length. Shorter channels allow for low power consumption and high speed capability.

A laterally diffused metal oxide semiconductor (LDMOS) device has a source and a drain that cause lateral current on its wafer surface. Two important parameters for designing an LDMOS device are the breakdown voltage and on-resistance. Preferably, the high breakdown voltage and low on-resistance allow the device to have relatively low power consumption at high voltage operation. In addition, the low on-resistance provides a higher drain current when the device is saturated, which improves the operating speed of the device.

The first figure is a top view of the drift zone of a conventional LDMOS device. The LDMOS device of the first figure has an LDMOS region 10, which is indicated by a square. The LDMOS device 1 includes a source side 20 and a drain side 30.

The second figure is a top view of the LDMOS region 10 indicated in the first figure. Figure. The LDMOS region 10 has a plurality of P-type diffusion layers or P-top regions 40 extending continuously from the source side 20 to the drain side 30, wherein the P-top region 40 is disposed in a high voltage N-type well (HVNW). Therefore, the conventional LDMOS region 10 includes an N-type energy level or N-energy level region 50 portion disposed above the P top end region 40, wherein the P top region 40 is separated by the N energy level region 50 and the N energy level region 50 is not disposed. Above any P top layer (P-TOP).

Fig. 3A is a cross-sectional view along the line AA' in the second figure. The conventional LDMOS in this representation has a P substrate 60 in the HVNW 70 provided. A first P well 80 is formed in the P substrate 60, and a second P well 90 is formed in the HVNW 70, wherein the first P well 80 has a P ⁺ doped region 100 and the second P well 90 has another P ⁺ doping Region 110 is adjacent to N ⁺ doped source region 120. The N ⁺ doped drain region 130 is formed in the HVNW 70. A portion of the LDMOS region 10 is represented by an N energy level region 50 disposed over the P top region 40 therein. The etch field oxide isolation region 140 substantially separates the doped regions 100, 110, 120, and 130.

Any conventional control gate structure 150 can be used in an LDMOS device. For example, the control gate structure 150 includes a conductive layer disposed on the dielectric layer. The control gate structure 150 further includes a dielectric sidewall spacer. An etched interlayer dielectric (ILD) layer 160 is disposed over the structure. The first etched metal layer 170 has a network that is in contact through the ILD layer 160. The conventional LDMOS example of FIG. 3A has an interfacial metal dielectric (IMD) layer 180 disposed over a second etched metal layer 190 that provides a network that is in contact through the ILD layer 180.

Fig. 3B is a cross-sectional view along the line BB' in the second figure. The cross-sectional view of the conventional LDMOS has the same structure as that of the third embodiment, except that the P top layer is not disposed in the HVNW 70.

High voltage LDMOS devices have different uses in semiconductors. E.g, The LDMOS device can be used to convert a relatively high voltage to a relatively low voltage or as a switching power transistor that is configured to drive a load. However, since the N-level region and the P-type fully doped region interact with each other, the dedicated on-resistance of the conventional high-voltage LDMOS is still too high. There is still a need in the art to improve LDMOS devices, especially high voltage LDMOS devices with lower dedicated on-resistance.

Embodiments of the present invention provide semiconductor devices, particularly metal oxide semiconductor (MOS) devices.

One aspect of the present invention is directed to a semiconductor, such as a metal oxide semiconductor (MOS) device, comprising a P substrate, a high voltage N well (HVNW) disposed in a P substrate, and a first P well formed in a first P ⁺ doping In the P substrate of the region, the second P well is formed in the HVNW having the second P well adjacent to the N ⁺ doped source region, the separated N energy level, and the separated P top region formed in the HVNW. The separated N energy level and the P top region have at least one or more layers, wherein each layer includes a plurality of P top regions interspersed between the plurality of N energy level segments.

In the embodiment of the present invention, the separated N-level and P-top regions comprise two or more layers, and the plurality of P-top segments and the plurality of N-energy segments are subjected to a criss-cross adjustment.

In accordance with an embodiment of the present invention, a plurality of separate P-top segments have a depth at the HVNW to define a plurality of depths; a width to define a plurality of widths; and a separation distance from a vertically adjacent N-energy segment to define a complex number Separation distance. In some embodiments of the invention, the plurality of depths may be the same, and in other embodiments of the invention, the plurality of depths are incremented.

According to an embodiment of the invention, the semiconductor may be laterally diffused metal oxygen Semiconductor semiconductor (LDMOS). In some embodiments of the present invention, each depth between the P top segments, the width of the P top segment, and the separation distance compared to other LDMOS devices having a continuous P top region disposed under the continuous N energy level region Its on-resistance at the drain voltage of 1 volt is reduced by approximately 11.6%. According to an embodiment of the invention, the breakdown voltage of the LDMOS device is the same as the breakdown voltage of an LDMOS device having a continuous P top region.

In some embodiments of the present invention, a plurality of separate N energy level segments have depth at the HVNW to define a plurality of depths compared to other LDMOS devices having a continuous P top region disposed under a continuous N energy level region. Width to define a plurality of widths; a separation distance selected from vertically adjacent N-energy segments to define a plurality of separation distances such that the on-resistance at a drain voltage of 1 volt is reduced by about 11.6%.

In an embodiment of the invention, the MOS device is an LDMOS device and the HVNW has an N ⁺ doped drain region.

The MOS device may further include a field oxide isolation region to isolate the first P ⁺ doped region from the second P ⁺ doped region, wherein the second P ⁺ doped region is adjacent to the N ⁺ doped source region of the HVNW and doped Area. For example, the field oxide isolation region LDMOS device isolates the first P ⁺ doped region from the second P ⁺ doped region, wherein the second P ⁺ doped region is adjacent to the N ⁺ doped source region of the HVNW and the N ⁺ doping Bungee area.

The MOS structure further includes a gate structure disposed between the N ⁺ doped source region and the doped region of the HVNW. For example, the LDMOS device includes a gate structure disposed between the N ⁺ doped source region of the HVNW and the N ⁺ doped drain region.

In some embodiments of the invention, the MOS device can be an insulated gate bipolar transistor with a third P ⁺ doped region disposed in the HVNW. In certain embodiments of the present invention, the MOS device may be a diode, wherein the N ⁺ doped drain region is disposed in the HVNW.

One aspect of the present invention is directed to a method of fabricating a MOS device, comprising The following steps: providing a P-type substrate; forming a high-voltage N-type well (HVNW) in the P-type substrate; forming a first P-type well in the P-type substrate; forming a second P-type well in the HVNW; forming a separation in the HVNW N energy level and separate P top regions, wherein the separated N energy levels and the separated P top regions have at least one layer, and each layer includes a plurality of separate P top segments dispersed in a plurality of separate N energy levels of the HVNW In the section.

The method of fabricating a MOS device further includes forming a field oxide isolation region. The field oxide isolation region has a first field structure overlapping the first P-type well and the second P-type well, and the second field oxidation structure is overlapped with the N energy level region.

The method of fabricating a MOS device further includes forming a gate structure. For example, the gate structure is formed by using a gate oxidation method, forming a polysilicon layer, and forming a spacer surrounding the gate structure.

The method of fabricating a MOS device further comprises the steps of: forming an N ⁺ doped source region in a second P-type well adjacent to the gate structure; forming a first P ⁺ doped region in the first P-type well; and forming a first P ⁺ doped region in the first P-type well; Forming a second P ⁺ doped region in the well and forming a doped region adjacent to the second field oxide structure in the HVNW.

In some embodiments of the invention, the doped region can be an N ⁺ doped drain region and the MOS device can be an LDMOS device or a diode. In other embodiments of the invention, the doped regions may be other P ⁺ doped regions and the MOS device may be insulated gate bipolar transistors.

In the case of the LDMOS device, the number of P top sections, the width of the P top section, the distance from each P top section to the N energy level zone, and the separation distance between the P top sections, and other continuous P Compared to the LDMOS device in the top region, the drain voltage is reduced by at least 15%, about 1 volt.

Another aspect of the invention further includes a product manufactured by the method of the invention Product.

The embodiments of the present invention will be apparent from the following description, taken in conjunction with the appended claims,

1‧‧‧LDMOS device

10‧‧‧LDMOS area

20‧‧‧Source side

30‧‧‧汲polar side

40‧‧‧P top area

50‧‧‧N energy level zone

60‧‧‧P substrate

70‧‧‧HVNW

80‧‧‧First P well

90‧‧‧Second P well

100‧‧‧P ⁺ doped area

110‧‧‧P ⁺ doped area

120‧‧‧N ⁺ doped source region

130‧‧‧N ⁺ doped bungee zone

140‧‧ ‧ field oxidation isolation zone

150‧‧‧Control gate structure

160‧‧‧Interlayer dielectric (ILD) layer

170‧‧‧First etched metal layer

180‧‧‧Interfacial Metal Dielectric (IMD) layer

190‧‧‧Second etched metal layer

210‧‧‧LDMOS area

220‧‧‧ source extreme

230‧‧‧汲 extreme

240‧‧‧Separated N-level and separated P-top

255‧‧‧N energy level zone

245‧‧‧Separated P-top section

260‧‧‧P substrate

270‧‧‧HVNW

280‧‧‧First P well

290‧‧‧Second P well

300‧‧‧P ⁺ doped area

310‧‧‧P ⁺ doped area

320‧‧‧N ⁺ doped source region

330‧‧‧N ⁺ doped bungee zone

340‧‧‧Field Oxidation Isolation Area

350‧‧‧Control gate structure

345‧‧ ‧ gate oxide layer

355‧‧‧ spacer

360‧‧‧Interlayer dielectric (ILD) layer

370‧‧‧First metal layer

365‧‧‧First core area

375‧‧‧Insulated area

380‧‧•Metal dielectric (IMD) layer

390‧‧‧Second metal layer

400‧‧‧ dielectric layer

410‧‧‧第18A图块

420‧‧‧The point shown in Figure 18B

430‧‧‧第19A图块

440‧‧‧The point shown in Figure 19B

450‧‧‧第20A图块

460‧‧‧Fig. 20B shows the line

470‧‧‧第21A图块

480‧‧‧The line shown in Figure 21B

490‧‧‧第22A图块

500‧‧‧The point shown in Figure 22B

510‧‧‧第23A图块

520‧‧‧The point shown in Figure 23B

530‧‧‧Using LDMOS devices

540‧‧‧LDMOS device

550‧‧‧Maximum breakdown voltage

560‧‧‧Using LDMOS devices

570‧‧‧LDMOS device

580‧‧‧ On-resistance

600‧‧‧LDMOS device

Framed part of 610‧‧600

620‧‧‧Separated P top section

630‧‧‧Separated N-level segments

700‧‧‧P substrate

710‧‧‧HVNW

720‧‧‧First P well

725‧‧‧Second P well

730‧‧‧First P ⁺ doped area

735‧‧‧Second P ⁺ doped area

740‧‧‧N ⁺ doped source region

745‧‧‧N ⁺ doped bungee zone

760‧‧‧Separated N-level and separated P-top

770‧‧ Field Oxidation Isolation Area

780‧‧‧Control gate structure

785‧‧‧Interlayer dielectric layer

790‧‧‧ Conductive layer

800‧‧‧P substrate

810‧‧‧HVNW

820‧‧‧First P well

825‧‧‧Second P well

830‧‧‧First P ⁺ doped area

835‧‧‧Second P ⁺ doped area

840‧‧‧N ⁺ doped area

845‧‧‧ Third P ⁺ doped area

860‧‧‧Separated N-level and separation P top area

870‧‧ ‧ field oxidation isolation zone

880‧‧‧Control gate structure

885‧‧‧Interlayer dielectric layer

890‧‧‧ Conductive layer

900‧‧‧P substrate

910‧‧‧HVNW

920‧‧‧First P well

925‧‧‧Second P well

930‧‧‧First P ⁺ doped area

935‧‧‧Second P ⁺ doped area

940‧‧‧N ⁺ doped source region

945‧‧‧N ⁺ doped bungee zone

960‧‧‧Separated N-level and separated P-top

970‧‧ ‧ field oxidation isolation zone

980‧‧‧Control gate structure

985‧‧‧Interlayer dielectric layer

990‧‧‧ Conductive layer

1000‧‧‧LDMOS device

1050‧‧‧HVNW

1060‧‧‧Field Oxidation Isolation Zone

1070‧‧‧gate oxidation

1080‧‧‧Polysilicon layer

1090‧‧‧ spacer

1100‧‧‧Second P well and HVNW

1110‧‧‧First P well and second P well

1120‧‧‧Interlayer dielectric layer

1130‧‧‧Interlayer dielectric layer

The present invention has been described with reference to the accompanying drawings, which are not necessarily to scale, and wherein: FIG. 1 is a top view of the LDMOS device; FIG. 2 is a top view of the LDMOS region; A cross-sectional view of the LDMOS region along the AA' segment line in FIG. 2 is disclosed; FIG. 3B is a cross-sectional view showing the LDMOS region along the BB' segment line in FIG. 2; A top view of an LDMOS region of an embodiment of the invention; FIG. 5A is a cross-sectional view of the LDMOS region along the AA' segment line in FIG. 4 in accordance with an embodiment of the present invention; and FIG. 5B discloses a first embodiment of the present invention. 4 is a cross-sectional view of the LDMOS region along the BB' segment line; FIGS. 6A and 6B are diagrams showing a high voltage N well formed in the P substrate, along the AA in FIG. 4, in accordance with an embodiment of the present invention. A cross-sectional view of the respective LDMOS regions of the 'and BB' segment lines; and FIGS. 7A and 7B are diagrams showing that after the first P well is formed in the P substrate and the second P well is formed in the HVNW, in accordance with an embodiment of the present invention Figure 4 is a cross-sectional view of the LDMOS region along the AA' and BB' segment lines; Figures 8A and 8B are revealed According to an embodiment of the present invention, after forming the first separated N well region and the first separated P top region in the HVNW, the cross-sectional views of the respective LDMOS regions along the AA' and BB' segment lines in FIG. 4; FIG. 9A A cross-sectional view of the LDMOS region along the AA' segment line in FIG. 4 after the second separated P top region and the second separated N well region are disposed in the HVNW according to an embodiment of the present invention; FIG. 9B reveals In accordance with an embodiment of the present invention, a cross-sectional view of the LDMOS region along the BB' segment line in FIG. 4 after the N energy level region is disposed in the HVNW; FIGS. 10A and 10B are diagrams showing the formation of the field in accordance with an embodiment of the present invention. After oxidizing the isolation region, a cross-sectional view of each of the LDMOS regions along the AA' and BB' segment lines in FIG. 4; and FIGS. 11A and 11B are diagrams showing the fourth embodiment after performing the gate oxidation method according to an embodiment of the present invention. A cross-sectional view of each of the LDMOS regions along the AA' and BB' segment lines; FIGS. 12A and 12B are diagrams showing the formation of a polysilicon layer under the control gate structure, in FIG. 4, in accordance with an embodiment of the present invention. Cross-sectional views of respective LDMOS regions of the AA' and BB' segment lines; Figures 13A and 13B show the formation of packages in accordance with an embodiment of the present invention A cross-sectional view of each of the LDMOS regions along the AA' and BB' segment lines in FIG. 4 after controlling the spacers of the gate structure; FIGS. 14A and 14B are diagrams showing N ⁺ doping in accordance with an embodiment of the present invention. After the source region is formed in the second P well and the N ⁺ -doped drain region is formed in the HVNW, the cross-sectional views of the respective LDMOS regions along the AA' and BB' segment lines in FIG. 4; FIGS. 15A and 15B It is disclosed that along the AA' and BB' section lines in FIG. 4, after the P ⁺ doped region is formed in the first P well and the other P ⁺ doped region is formed in the second P well, in accordance with an embodiment of the present invention. Cross-sectional views of respective LDMOS regions; FIGS. 16A and 16B are cross-sectional views showing respective LDMOS regions along the AA' and BB' segment lines in FIG. 4 after forming an interlayer dielectric layer in accordance with an embodiment of the present invention. 17A and 17B are cross-sectional views showing respective LDMOS regions along the AA' and BB' segment lines in FIG. 4 after forming the first metal layer; FIGS. 18A and 18B are diagrams. TCAD simulation diagram showing the impact generation rate of a conventional LDMOS device at the time of collapse; 19A and 19B are TCAD modes according to an embodiment of the present invention The figure shows the rate of impact generation of the LDMOS device at the time of collapse; the 20A and 20B diagrams are TCAD simulation diagrams, which reveal the potential profile of the conventional LDMOS device at the time of collapse; the 21A and 21B diagrams are in accordance with this TCAD simulation diagram of an embodiment of the invention, which reveals the potential potential of the LDMOS device at the time of collapse; 22A and 22B are TCAD simulation diagrams showing the electric field of the conventional LDMOS device at the time of collapse; 23A and 23B The figure is a TCAD simulation diagram according to an embodiment of the present invention, which discloses an electric field of an LDMOS device at the time of collapse; FIG. 24A is a diagram showing a drain voltage of a conventional LDMOS device according to an embodiment of the present invention and the LDMOS device of the present invention. FIG. 24B is another illustration of a threshold voltage versus a drain current of a conventional LDMOS device and an LDMOS device of the present invention; FIG. 25 is an embodiment of the present invention. Sectional view of the LDMOS device; Fig. 26 is a cross-sectional view showing the portion of the frame line in the LDMOS device of the 25th embodiment of the present invention, which discloses the division of the first separated P top region and the second separated P top region. FIG. 27 is a cross-sectional view showing a portion of a frame line in an LDMOS device according to a 25th embodiment of the present invention, which discloses a first separated P top region, a second separated P top region, and a first separated N energy. a variation of the spacing between the separation elements of the step region and the second separated N energy level region; and FIG. 28 is a cross-sectional view showing the portion of the frame line of the LDMOS device of FIG. 25 according to an embodiment of the present invention, which discloses the first separation N energy The width variation of the separation element of the step region and the second separated N energy level region; FIG. 29 is a cross-sectional view showing the frame line portion of the LDMOS device according to the 25th embodiment of the present invention, which discloses the first separated N energy level region. a variation between the separation elements of the second separated N energy level region, the first separated P top region, and the second separated P top region; and FIG. 30 illustrates a frame line of the LDMOS device according to the 25th embodiment of the present invention. a partial cross-sectional view showing a change in depth between the first separated P top region and the separated elements of the second separated P top region; and FIG. 31 is a view showing a portion of the frame line in the LDMOS device according to the 25th embodiment of the present invention. a cross-sectional view showing the first separated N energy level region and the second Depth variation between discrete elements from the N energy level region; FIG. 32A is a cross-sectional view showing an N-channel metal oxide semiconductor device having multiple separations in accordance with an embodiment of the present invention An N-level segment and a plurality of separate P-top segments; FIG. 32B discloses an N-channel MOS device having no separated N-level segments and separated N-level P-top segments in accordance with an embodiment of the present invention A cross-sectional view of an N-energy step; FIG. 33A is a cross-sectional view showing an insulated gate bipolar transistor having a plurality of discrete N-level segments and a plurality of discrete P-top segments in accordance with an embodiment of the present invention; Figure 33B is a cross-sectional view showing an N-energy step of an insulated gate bipolar transistor having no separated N-level segments and separated N-level P-top segments in accordance with an embodiment of the present invention; A cross-sectional view of a diode according to an embodiment of the present invention having a plurality of discrete N-energy segments and a plurality of separate P-top segments; and FIG. 34B discloses a non-separating N-energy segment in accordance with an embodiment of the present invention And separating the N-level P top section A cross-sectional view of a N-energy step of the body; and a 34B-throw showing an N-energy step of the dipole without separating the N-energy segment and separating the N-level P-top segment in accordance with an embodiment of the present invention Sectional view.

Figure 35 is a flow chart of a method of fabricating an LDMOS device in accordance with an embodiment of the present invention.

Some embodiments of the present invention will now be described fully below with reference to the accompanying drawings, but not all embodiments of the invention The embodiments may be embodied in many different forms and should not be construed as being limited to the embodiments. Instead, these embodiments are provided so that this disclosure will satisfy the applicable legal.

The singular forms "a", "the", "the" and "the" are used in the <Desc/Clms Page number> P top section.

Certain terms used in the present disclosure are used in the generic and descriptive concepts only and not for the purpose of limitation, all terms, including technical and scientific terms, unless the context clearly The same meanings are generally understood by those of ordinary skill in the art; further, as defined in commonly used dictionaries, should be interpreted as having a meaning as commonly understood by those of ordinary skill in the art to which the invention pertains. And, as defined in commonly used dictionaries, should be interpreted as having meaning consistent with their meaning in the relevant art and the context of the disclosure, such commonly used terms will not be interpreted as excessively ideal or rigid. Concept, unless the context clearly defines otherwise.

As used herein, "MOS device" means a metal oxide semiconductor device such as a laterally diffused metal oxide semiconductor (LDMOS), an N-channel metal oxide semiconductor (NMOS), an insulated gate bipolar transistor (IGBT), and a diode. . The device can be arranged to be suitable for high voltages or even ultra-high voltages relative to other semiconductor devices.

As used herein, "LDMOS device" means a metal oxide semiconductor field effect transistor (MOSFET) having parallel source and drain regions. In accordance with certain embodiments of the present invention, the LDMOS device of the present invention is characterized by a high breakdown voltage and a low on-resistance. The LDMOS device of the present invention and the method of fabricating the same can cause the LDMOS device to have a relatively high breakdown voltage. Further, the LDMOS device of the present invention and the method of manufacturing the same The LDMOS device can be made to have a lower on-resistance than other conventional LDMOS devices.

Figure 4 is a top plan view of an LDMOS region 210 in accordance with an embodiment of the present invention. The LDMOS region 210 has a plurality of discretely disposed N-level diffusion segments interposed in a plurality of separate P-type diffusion segments, which are also separated N-levels and separated P-top regions 240. The split N level and the split P top region 240 extend from the source terminal 220 of the LDMOS region 210 to the drain terminal 230. The separated N energy level and the separated P top region 240 are disposed in a high voltage N-type well (HVNW). Therefore, in accordance with an embodiment of the present invention, LDMOS region 210 is defined as a multiplexed and separated N level and a separate P top region 240, wherein each region is separated by a non-separated and set N energy level region 255, which does not include a complex number Separate and set N-level segments or any separate P-top segments.

Figure 5A is a cross-sectional view showing the LDMOS region along the AA' segment line in Figure 4 in accordance with an embodiment of the present invention. Implementations of LDMOS devices in accordance with embodiments of the present invention have a P-type semiconductor substrate or P-substrate 260 that may form a P-type layer, such as a P-type epitaxial layer, in all or part of the manner in which HVNW 270 has been disposed. A first P well 280 is formed in the P substrate 260 and a second P well 290 is formed in the HVNW 270, wherein the first P well 280 has a P ⁺ doped region 300 and the second P well 290 has another P ⁺ doped region. 310 is adjacent to the N ⁺ doped source region 320. The N ⁺ doped drain region 330 has been formed in the HVNW 270. The LDMOS region 210 includes a separate N-level and a separate P-top region 240 having a plurality of discrete N-level segments 250 interposed in a plurality of separate P-top segments 245. Field oxide isolation region 340 separates doped regions 300, 310, 320, and 330.

Any conventional control gate structure 350 can be used for the LDMOS device. For example, the control gate structure 350 can include a conductive layer that is disposed on the dielectric layer. The control gate structure 350 further includes a dielectric sidewall spacer. An interlayer dielectric (ILD) layer 360 is disposed on the structure. The first metal layer 370 includes a network of contacts that pass through the ILD layer 360. The LDMOS device of FIG. 4 in this embodiment shows an inner metal dielectric (IMD) layer 380 disposed on the second etched metal layer 390 to provide a contact network through the IMD layer 380.

Fig. 5B is a cross-sectional view showing the LDMOS region along the BB' segment line in Fig. 4. A cross-sectional view of an LDMOS device in accordance with an embodiment of the present invention has the same structure as in FIG. 5 except that separate N-energy segments and separate P-top segments are not disposed in HVNW 270. More specifically, the N energy level region 255 is disposed in the HVNW 270. Thus, in accordance with an embodiment of the present invention, the cross-section of the conventional structure shown in FIG. 3B and the cross-section of the LDMOS device of the invention shown in FIG. 5B may be substantially similar. The cross section of the conventional structure shown in Fig. 3A and the cross section of the LDMOS device shown in Fig. 5A are different.

6A through 17B are cross-sectional views of the LDMOS device of the present invention for fabricating the complete steps described for the LDMOS device. The figure number ends with a description of the section of the LDMOS device along the AA' segment line. Taking Figure 4 as an example, the separated N level and the separated P top area 240 are shown, and the figure number ends with B. For the description of the cross section of the LDMOS device of the BB' segment line, taking the fourth figure as an example, only the N energy level region 255 is shown.

6A and 6B are diagrams showing the LDMOS regions along the AA' and BB' segment lines in FIG. 4 after the high voltage N well (HVNW) 270 is formed in the P substrate 260, in accordance with an embodiment of the present invention. Sectional view. The HVNW 270 extends downward from the upper end portion of the P substrate 260. The method of forming HVNW 270 typically includes depositing a photoresist to define a region, wherein HVNW 270 is formed in P substrate 260, The lithography and the pattern and position required to develop the HVNW 270. For example, the implantation method can be performed by a lithographic, epitaxial layer of a reticle-developed P substrate 260. In some embodiments of the invention, the implantation method follows a N-drive-in step. The drive-in step typically occurs during certain periods of warming up. In certain embodiments of the invention, there is a temperature rise anywhere in the drive-in step and a range from 20 minutes to 2 hours in the range of from 1,000 ° C to 1,150 ° C. In certain embodiments of the invention, the drive-in step method is continued at 1,150 ° C for 1 hour. Any residual photoresist can typically be removed in the same manner as the HVNW 270 is processed or removed while the HVNW 270 is being processed.

7A and 7B show that after the first P well 280 is formed in the P substrate 260 and the second P well 290 is formed in the HVNW 270, in FIG. 4 along AA' and BB, in accordance with an embodiment of the present invention. 'A cross-sectional view of the respective LDMOS regions of the segment lines. The P well can be applied to the desired layer by using lithography and P-type impurity ion implantation. In certain embodiments of the invention, the ion implantation method can follow the P-well drive step, as in the case of the aforementioned drive-in step. The program also includes removing any residual photoresist. The first P well 280 and the second P well 290 may be formed substantially and simultaneously or in different steps, preferably the same if separate ions of the separate types are implanted into the P substrate 260 and the HVNW 270, respectively.

8A and 8B are diagrams showing the formation of a plurality of separate P top sections 245 and a plurality of separate N energy level sections 250 in HVNW 270, along AA' and BB in Fig. 4, in accordance with an embodiment of the present invention. A cross-sectional view of the respective LDMOS regions of the segment lines. A plurality of separate P top sections 245 and a plurality of separate N energy level sections 250 exhibit separate N energy levels and separate P top areas 240. The separated P top section is defined as a P type diffusion zone, and the separated N energy level section is defined as an N type diffusion zone.

For example, the first photoresist may be arranged to define an area in which the P top section 245 is to be formed in the HVNW 270, followed by a lithography method and development of the first desired pattern to confirm the separated N level and the separated P The location of the P top section 245 in the top zone 240. Implantation of P-type ions can deposit a plurality of P-top sections into HVNW 270 through a first patterned and developed reticle. The method of implanting a plurality of separate P top sections 245 may end with removing excess photoresist on the device. The first mask is removable and the second photoresist can be deposited to define a region in which the N level segment 250 is to be formed in the HVNW 270, followed by a lithography method and a desired pattern for development to confirm the separated N energy. The position of the N-level segment 250 in the P-top region 240 of the step and separation. The implantation of the N-type ions can deposit a plurality of N-energy segments into the HVNW 270 through the second patterned and developed photomask. One or more of the steps and/or conditions in the implantation method, for example, each P top segment 245 and each N energy segment 250 in HVNW 270 achieves a preferred position for those skilled in the art. The implant energy can vary.

FIG. 9A is a diagram showing an additional N-energy step 250 and a P-top segment 245 in the separated N-level and separated P-top regions 240 of the HVNW 270, in accordance with an embodiment of the present invention, in FIG. A cross-sectional view of the LDMOS region of the AA' segment line. As previously described, the reticle can be used in LDMOS devices, for example, lithography and N-type carriers can be implanted into HVNW 270 to define additional N energy level segments 250, while N energy level segments 250 define separate N energy levels. And a separate P top region 240. The reticle is removable and another reticle is available for the LDMOS device and the P-type carrier is implantable with the HVNW 270 to define an additional P-top section 250, while the P-top section 250 defines a separate N-level and separate P-top Area 240. The N energy level region 255, as shown in FIG. 9B, may be substantially any separate P top segment and a plurality of separate N energy segment segments.

Separate N energy levels and each P of the separated P top region 240 The top section 245 and the plurality of M energy level sections 250 may be formed simultaneously or even in the formation of separate P top regions 240 in two or more lithography and implantation steps. The embodiments of Figures 8A and 9A show a two-step method for implanting a plurality of separate P top segments 245 and a plurality of N energy segments into separate N energy levels and separate P top regions 240 . For example, when forming a N-energy step 250 and a P-top section 245 that are variable in the HVNW 270 and the depth of change of the section, there is a variable P-type ion concentration in the P-top section 245. Having a variable N-type ion concentration in the N-energy step 250 and/or laminating some or all of the P-top segments on the N-energy step, and vice versa, and in the separated N-level Two or more steps are particularly useful when the separate P-top regions 240 of the separated P top region 240 are capable of connecting or separating separate N energy levels and separate P top regions 240.

In other embodiments of the invention, any of the steps may be performed to accomplish the positioning required for separating the plurality of P-top segments 245 and the plurality of N-energy segments 250 in the separated N-level and separated P-top regions 240. In an embodiment of the invention, the steps illustrated in Figure 9A may not be implemented. For example, the illustrative step of FIG. 8A is sufficient to provide the positioning required for separating the plurality of P-top segments 245 and the plurality of N-energy segments 250 in the separated N-level and separated P-top regions 240.

According to some embodiments of the invention, for example, the N-type carrier may be selected from any one or more of the elements of Group 5A of the Periodic Table of the Elements, for example, may be phosphorus according to certain embodiments of the invention. In certain embodiments of the invention, the desired N-type ion may be formed from a compound having at least one element selected from Group 5A and at least one element selected from Group 4A, for example, a phosphonium phosphorus compound.

According to some embodiments of the invention, the P-type carrier may be selected from any one or more of the elements of Group 3A of the Periodic Table of the Elements, for example, in accordance with certain embodiments of the present invention, Often selected from boron. In certain embodiments of the invention, the desired P-type ions may be formed from a compound having at least one element selected from Group 3A and at least one element selected from Group 4A, for example, the P-type ion may be a bismuth boron compound.

In some embodiments of the invention, the separated N-level and separated P-top regions 240 comprise two, three, four, five, six, seven, eight, nine, ten or More separate P-top sections 245 and including two, three, four, five, six, seven, eight, nine, ten or more separate N-level sections 250 .

Attempts are not limited by theory, although the number of separated P top sections 245 and the separated N energy level sections 250 and the concentration of P-type carriers in the separated P-top sections may be N-type in the separated N-energy stage sections. The concentration of the carrier is balanced. More attempted not to be limited by theory, separate N-level and separate P-top regions 240 can be provided to improve charge balance and reduce the specific on-resistance of the LDMOS device. Still attempting not to be limited by theory, the separated N-level and separated P-top regions 240 are configured to allow upward depletion in the extended drain region of HVNW 270 to combine upward depletion from P substrate 260, which is not materialized. Affects and provides a breakdown voltage that is similar to that of a conventional LDMOS device. The HVNW 270 doping can achieve a lower specific on-resistance.

In certain embodiments of the invention, separate N energy levels and separate P top regions 240 may be disposed proximate to the second P well 290. For example, the number of separate P-top segments, the location of each P-top segment in HVNW 270, the position between each P-top segment in HVNW 270, and relative to other N-energy segments, and other described parameters will It will affect the extent to which the specific on-resistance of the LDMOS device is reduced. In addition, the number of separated N-level segments, the position of each N-energy segment of HVNW 270, the position between each N-energy segment and relative to other P-top segments, and other such parameters The number will affect the extent to which the specific on-resistance of the LDMOS device is reduced.

Finally, the N energy level region 255 shown in FIG. 9B is substantially any separated P top portion and a plurality of separate N energy level segments.

10A and 10B are cross-sectional views showing respective LDMOS regions along the AA' and BB' segment lines in Fig. 4 after forming the field oxide isolation region 340, in accordance with an embodiment of the present invention. In accordance with an embodiment of the present invention, field oxide isolation region 340 can include a plurality of field oxide isolation structures that separate LDMOS devices into different regions. For example, in the embodiment of FIGS. 10A and 10B, field oxide isolation region 340 includes field oxide isolation structures that are separated into different doped regions, which will eventually form first P well 280, second P well 290, and HVNW 270.

In accordance with an embodiment of the present invention, field oxide isolation region 340 may be formed using a relatively thick field oxide layer, for example, along the upper surface of LDMOS, as shown in Figures 10A and 10B, in accordance with certain embodiments of the present invention. On a scale of 1 micron or larger, a mask and etching are applied to define certain portions of the upper surface.

In some embodiments of the invention, the field oxide isolation regions 340 may be etched after growth to isolate certain regions of the LDMOS device. For example, a substantially uniform field oxide layer can be applied to field oxide diffusion. The photoresist can be applied to the growth field oxide layer and successively subjected to lithography and development to identify areas of the field oxide isolation layer that are to be etched to remove portions. Following the etch process, any residual photoresist can be removed and a plurality of field oxide structures remain to define the field oxide isolation region 340. In some embodiments of the invention, a precursor material such as a pad oxide and/or a germanium nitride may be applied as well as a field oxide oxidation process to etch the field oxide in the defined structure.

11A and 11B are diagrams showing AA' and BB' in FIG. 4 after forming a gate oxide layer 345 by performing a gate oxidation method according to an embodiment of the present invention. A cross-sectional view of the respective LDMOS regions of the segment lines. The gate oxidation process can include a sacrificial oxidation step that causes the oxide to grow into the surface of the crucible by exposing the surface of the crucible to oxygen for a period of time. Typically, the sacrificial oxidation process is carried out at elevated temperatures, for example, from about 800 ° C to about 1,000 ° C or higher. In certain embodiments of the invention, the elevated temperature may be between a temperature range from about 850 °C to about 950 °C. In still other embodiments of the invention, the elevated temperature can be about 900 °C.

The sacrificial oxidation process can be followed by a gate cleaning process or, more suitably, a pre-gate clean process to remove the essential oxides on the surface where the control gate is to be applied. Any conventional pre-gate cleaning method can be used. For example, the pre-gate cleaning method uses HF, HCL, or ozone to clean the area needed to form the gate oxide. Finally, a gate oxidation step can be used to form the gate oxide layer 345.

12A and 12B are cross-sectional views showing respective LDMOS regions along the AA' and BB' segment lines in Fig. 4 after forming the polysilicon layer of the control gate structure 350 in accordance with an embodiment of the present invention. The procedure for forming the polysilicon layer includes depositing polysilicon in the gate oxide layer 345, which is commonly performed by chemical vapor deposition. The deposition of polycrystalline germanium can continue to deposit tungsten germanide (WSix), which is bonded to the polycrystalline germanium layer, often referred to as a metal cyanide (polycide). The lithography method step can be used to define the area where the metal telluride layer will remain after etching. After the etching is completed, the polysilicon layer of the control gate structure 350 is defined to remain.

13A and 13B are diagrams showing the respective LDMOS along the AA' and BB' segment lines in FIG. 4 after forming a spacer 355 surrounding the polysilicon layer of the control gate structure 350, in accordance with an embodiment of the present invention. A section view of the area. In an embodiment of the invention. The conformal layer of tetraethoxy decane (TESO) can be placed in LDMOS The surface of the device. The lithography method can be used to define a residual spacer 355 that surrounds the control gate structure 350. The surface of the reticle can be etched to form a residual spacer 355 that surrounds the control gate structure 350. Preferably, the spacer 355 can also be considered as part of the control gate structure 350.

14A and 14B show that after the N ⁺ doped source region 320 is formed in the second P well 290 and the N ⁺ doped drain region 330 is formed in the HVNW 270, in FIG. 4, in accordance with an embodiment of the present invention, A cross-sectional view of the respective LDMOS regions along the AA' and BB' segment lines. Each of the N ⁺ doped regions 320 and 330 can be implanted in a respective region by depositing a photoresist to define where the N ⁺ doped regions 320 and 330 are to be formed, followed by lithography and development of the desired pattern to identify N ⁺ Doped regions 320 and 330 locations. The N ⁺ ions can be implanted or implanted into the region defined by the reticle to form the N ⁺ doped source region 320 in the second P well 290 and the N ⁺ doped drain region 330 in the HVNW 270. In some embodiments of the invention, each of the N ⁺ doped regions 320 and 330 may be formed by a process similar to that described above but separate.

15A and 15B show that after the P ⁺ doping region 300 is formed in the first P well 280 and the other P ⁺ doping region 310 is formed in the second P well 290, in accordance with an embodiment of the present invention, FIG. 4 A cross-sectional view of the respective LDMOS regions along the AA' and BB' segment lines. In some embodiments of the invention, the P ⁺ doped region 310 of the second P well 290 is adjacent to the N ⁺ doped source region 320 of the second P well 290.

Each of the P ⁺ doped regions 330 and 310 can be implanted in a respective region by depositing a photoresist to define where the P ⁺ doped regions 300 and 310 are to be formed, followed by a pattern required for lithography and development to identify N ⁺ Doped regions 300 and 310 locations. P ⁺ ions may be implanted or implanted into regions defined by the reticle to form P ⁺ doped source regions 300 in the first P well 280 and P ⁺ doped drain regions 310 in the second P well 290 in. In some embodiments of the invention, each P ⁺ doped region 300 and 310 may be formed by a process similar to that described above but separate.

16A and 16B are cross-sectional views showing respective LDMOS regions along the AA' and BB' segment lines in Fig. 4 after forming the interlayer dielectric (ILD) layer 360, in accordance with an embodiment of the present invention. The ILD layer 360 can be formed from a first deposited interlayer dielectric material to the LDMOS device. The lithography method can then be used to create a patterned photoresist to define a first core region 365 where the conductive material will be formed. Finally, the first core region 365 will be etched to determine the structure of the ILD layer 360.

17A and 17B are cross-sectional views showing respective LDMOS regions along the AA' and BB' segment lines in Fig. 4 after forming the first metal layer 370, in accordance with an embodiment of the present invention. The first metal of the first metal layer 370 can be disposed along the ILD layer 360 to substantially fill the first core region 360 defined in the ILD layer 360. The lithography method can then be used to create a patterned photoresist to define an insulating region 375 where the dielectric material of the bounded metal dielectric (IMD) layer 380 is formed. Finally, the insulating region 375 will be etched to determine the structure of the first metal layer 370.

The splicing layers can be applied identically. For example, as in the embodiment illustrated in FIGS. 5A and 5B, the IMD layer 380 can be applied to the first metal layer 370. A second metal layer 390 having a second insulating region can be applied to the IMD layer 380. Another dielectric layer 400, for example, can be applied to the second metal layer 390.

Figures 18A and 18B are TCAD simulation diagrams showing the impact generation rate of a conventional LDMOS device at the time of collapse. Figure 18B is a more detailed representation of block 110A block 410. Point 420, shown in Fig. 18B, is where the maximum impact rate in the device occurs. 19A is a TCAD simulation diagram showing the impact of the LDMOS device of the present invention in a crash according to an embodiment of the present invention. Birth rate. Figure 19B is a more detailed display of block 19A of block 19A. Point 440, shown in Figure 19B, is where the maximum impact rate occurs in the device. Figs. 18A to 19B are diagrams showing the rate of impact generation of the LDMOS of the present invention at the time of collapse, and the impact generation rate of the LDMOS of the present invention at the time of collapse is not affected by the material of the separated N level and the separated P top region. Therefore, the LDMOS device of the present invention exhibits a depression capability similar to that of the conventional device and the maximum breakdown voltage is not affected by the material.

Figure 20A is a TCAD simulation diagram showing the potential profile of a conventional LDMOS device at the time of collapse. Figure 20B is a more detailed representation of block 450 of block 20A. Line 450, shown in Figure 20B, is where the maximum potential potential occurs in the device. Figure 21A is a TCAD simulation diagram showing the potential potential of the LDMOS device of the present invention in the event of a crash. Figure 21B is a more detailed representation of block 21A of block 21A. Line 480, shown in Figure 21B, is where the maximum potential potential occurs in the device. 20A to 21B are diagrams showing the potential potential distribution at the time of collapse between the conventional LDMOS device and the LDMOS device of the present invention, which does not differ depending on the material. Therefore, the LDMOS device of the present invention exhibits a potential potential similar to that of the conventional device and the maximum breakdown voltage is not affected by the material.

Figure 22A is a TCAD simulation diagram showing the electric field of a conventional LDMOS device at the time of collapse. Figure 22B is a more detailed representation of block 22A of block 22A. The point 500 shown in Figure 22B is where the maximum electric field occurs in the device. Figure 23A is a diagram of a TCAD simulation in accordance with an embodiment of the present invention showing the electric field of the LDMOS device of the present invention in the event of a crash. Figure 23B is a more detailed representation of block 23A of block 23A. Point 520, shown in Figure 23B, is where the maximum electric field occurs in the device. 22A to 23B are diagrams of a conventional LDMOS device and an LDMOS device of the present invention. The electric field at the time of collapse does not vary from material to material. Therefore, the LDMOS device of the present invention exhibits an electric field similar to that of the conventional device and the maximum breakdown voltage is not affected by the material.

Figure 24A is a graphical representation of the gate voltage vs. gate current of a conventional LDMOS device 530 and an LDMOS device 540 of the present invention in accordance with an embodiment of the present invention. Fig. 24A shows the maximum breakdown voltage 550 between the conventional LDMOS device and the LDMOS device of the present invention. However, in contrast to conventional LDMOS devices with high drain voltages, the LDMOS device of the present invention may increase the drain current because the device of the present invention has a lower resistance when the voltage is close to the collapse voltage.

Figure 24B is another illustration of the gate voltage versus the drain current of the conventional LDMOS device 560 and the LDMOS device 570 of the present invention in accordance with an embodiment of the present invention. Figure 24B shows the on-resistance of a conventional LDMOS device having a continuous P top region. The LDMOS device of the present invention has an improvement in the on-resistance 580 of 11.6% when the drain voltage is 1 volt.

Figure 25 is a cross-sectional view of an LDMOS device 600 in accordance with an embodiment of the present invention in accordance with Figure 5A. In accordance with an embodiment of the invention, the frame portion 610 of the LDMOS device 600 exhibits a plurality of separate P top segments 620 and a plurality of separate N energy segments 630.

Figure 26 is a cross-sectional view detailing the frame portion 610 of the LDMOS device 600 of Figure 25, showing five separate P-top segments 620 having W _P1 , W _P2 , W _P3 , W _P4 and W _P5 widths, respectively. . As previously mentioned, there may be any number of separate P-top segments 620 in the separated N-level and separated P-top regions, but it is clear that the embodiment shown in Figure 26 has five separate P-tops. Section 620. In more detail, the embodiment of Figure 26 shows that the separated N-level and separated P-top regions have a first plurality of P-top segments interspersed between the first plurality of discrete N-level segments and A second plurality of N energy stages are interspersed between the second plurality of discrete N energy level segments. In the embodiment of Figure 26, the bottom layer is shown as a first bottom section, which is a separate P-top section, followed by a second bottom section, which is a separate N-energy section, followed by a third a bottom section, which is another separate P-top section, continuing as a fourth bottom section, which is another separate N-energy section, followed by a fifth bottom section, which is another separate P Top section. In the embodiment of Figure 26, the top layer is shown as being substantially aligned with the first top section of the first bottom section, which is a separate N energy level section, which is subsequently substantially aligned with the second bottom a second top section of the section, which is a separate P top section, followed by a third top section substantially aligned with the third bottom section, which is another separate N energy level section, followed by To be substantially aligned with the fourth top section of the fourth bottom section, which is another separate P top section, followed by a fifth top section substantially aligned with the fifth bottom section, which is Another separate N energy level segment. In accordance with an embodiment of the present invention, the top and bottom structures illustrated in FIG. 26 exhibit an arrangement that is a crash-cross arrangement of the aforementioned separate P-top segments and separate N-energy segments. ).

In an embodiment of the invention, the widths W _P1 , W _P2 , W _P3 , W _{P4 ,} and W _{P5 of the} separated P top sections 620 may be substantially the same. In other embodiments, the widths W _P1 , W _P2 , W _P3 , W _{P4 ,} and W _{P5 of the} separated P top sections 620 may be different to achieve the need in the on-resistance without substantially affecting the maximum breakdown voltage. The cut. In certain embodiments of the invention, the P-type ion implantation concentrations in the separate P-top sections 620 may be different such that even though the widths of the separated P-top sections 620 are different, complete depletion conditions may be achieved. In some embodiments of the invention, the separated P-top segments 620 are separated along the gap walls S _P1 , S _P2 , S _{P3 ,} and S _P4 and the depths D _P1 , D _P2 , D _P3 , D _{P4 ,} and D _{P5 .} Synchronous adjustment of implant concentration and depth provides improved on-resistance while still maintaining a high breakdown voltage substantially and simultaneously.

Figure 27 is a cross-sectional view detailing the frame line portion 610 of the LDMOS device 600 of Figure 25, showing five separate P top segments 620 and five separate N energy segments 630, wherein the separation in the upper region The N energy level section and the separated N energy level section in the lower area are respectively disposed at the upper end and the lower end by the spacer distances S _P1 , S _P2 , S _{P3 ,} and S _P4 . The separate P top regions but separate N energy segments can be any number, but for the purposes of Figure 27, there are five embodiments shown. In an embodiment of the invention, the distances S _P1 , S _P2 , S _P3 and S _P4 may be substantially the same. In other embodiments of the invention, the distances S _P1 , S _P2 , S _{P3 ,} and S _P4 may be different to achieve the desired reduction in on-resistance without substantially affecting the maximum breakdown voltage. In certain embodiments of the present invention, the P-type ion implantation concentration in the N-type ion implantation concentration in the separated P top section 620 and the separated N energy level section 630 including the P top section width may not The same, even if the gap walls are different from S _P1 , S _P2 , S _P3 and S _P4 , the condition of complete depletion can be achieved. In some embodiments of the invention, the implant concentration and width of the separated P top section 620 and the separated N energy levels of the gaps S _P1 , S _P2 , S _{P3 ,} and S _P4 . Synchronous adjustment of the implant concentration of segment 630 can provide improved on-resistance while still maintaining a high breakdown voltage substantially and simultaneously.

Figure 28 is a cross-sectional view detailing the frame portion 610 of the LDMOS device 600 of Figure 25, showing five separate N-level segments 630 each having W _N1 , W _N2 , W _N3 , W _{N4 ,} and W _N5 . . The separated N energy levels and the separated N energy level segments 630 in the separated P top regions can be any number, but for the purposes of the display of FIG. 28, the embodiment shown therein has five separate N energy level segments 630. . In an embodiment of the invention, the widths W _N1 , W _N2 , W _N3 , W _{N4 ,} and W _{N5 of the} separated N energy level segments 630 may be substantially the same. In other embodiments of the present invention, the widths W _N1 , W _N2 , W _N3 , W _{N4 ,} and W _{N5 of the} separated N-level segments 630 may be different to be in the on-resistance without substantially affecting the maximum breakdown voltage. Reach the required cuts. In some embodiments of the invention, the N-type ion implantation concentrations of the separated N-energy segments 630 may be different such that even if the separated N-energy segments 630 are different, complete depletion conditions may be achieved. In some embodiments of the invention, the separated N energy levels are along the gap walls S _N1 , S _N2 , S _N3 , S _N4 and S _N5 and D _N1 , D _N2 , D _N3 , D _N4 and D _{N5 .} Synchronous adjustment of the implant concentration and width of segment 630 can provide improved on-resistance while still maintaining a high breakdown voltage substantially and simultaneously.

Figure 29 is a cross-sectional detail view of the frame line portion 610 of the LDMOS device 600 of Figure 25 showing five separate P top segments 620 and five separate N energy segments 630. The separated N energy levels and the separated N energy level segments 630 in the separated P top regions can be any number, but for the purposes of the display of FIG. 28, the embodiment shown therein has five separate N energy level segments 630. The separated P top section in the upper region and the separated P top section in the lower region are respectively disposed at the upper end and the lower end by the spacer distances S _N1 , S _N2 , S _{N3 ,} and S _N4 . The separated P top regions, but separate N energy segments, can be any number, but for the purposes of Figure 29, there are five embodiments shown. In an embodiment of the invention, the distances S _N1 , S _N2 , S _N3 and S _N4 may be substantially the same. In other embodiments of the invention, the distances S _N1 , S _N2 , S _{N3 ,} and S _N4 may be different to achieve the desired reduction in on-resistance without substantially affecting the maximum breakdown voltage. In certain embodiments of the invention, the P-type ion implantation concentration in the separated P top section 620 and the N-type ion implantation in the separated N energy level section 630 including the width of the N energy level section The concentrations may be different, such that even if the spacers are different in distances S _N1 , S _N2 , S _N3 and S _N4 , complete depletion conditions can be achieved. In some embodiments of the invention, the implant concentration and width of the separated N-level segment 630 and the P top of the separated gap distances S _N1 , S _N2 , S _{N3 ,} and S _N4 Synchronous adjustment of the implant concentration of segment 620 can provide improved on-resistance while still maintaining a high breakdown voltage substantially and simultaneously.

Figure 30 is a cross-sectional view detailing the frame line portion 610 of the LDMOS device 600 of Figure 25, showing five separate P-top segments 620 and five separate N-energy segments 630 with separate P-top regions Segments 620 each have different implant depths D _P1 , D _P2 , D _P3 , D _{P4 ,} and D _P5 . Different implant depths can be controlled by changing the implantation method, such as implanting energy. The separated P-top section and the separated N-energy section can be any number, but for the purpose of display of Figure 30, there are five embodiments shown. In an embodiment of the invention, the depths D _P1 , D _P2 , D _P3 , D _P4 and D _P5 may be substantially the same. In other embodiments of the invention, the depths D _P1 , D _P2 , D _P3 , D _{P4 ,} and D _P5 may be different to achieve the desired reduction in on-resistance without substantially affecting the maximum breakdown voltage. In certain embodiments of the invention, the P-type ion implantation concentration in the separated P top section 620 and the separation including the P top section width and the spacer distances S _P1 , S _P2 , S _{P3 ,} and S _P4 The N-type ion implantation concentration in the N-energy step 630 may be different, so that even if the depths D _P1 , D _P2 , D _P3 , D _{P4 ,} and D _{P5 are} different, a complete depletion condition can be achieved. In some embodiments of the invention, the implant concentration and width of the separated P top section 620, the spacer distances S _P1 , S _P2 , S _{P3 ,} and S _{P4 ,} and the depths D _P1 , D before and after _The simultaneous adjustment of the implant concentration of the separate N-level segments 630 of _P2 , D _P3, and D _P4 provides improved on-resistance while still maintaining a high breakdown voltage substantially and simultaneously.

Figure 31 is a cross-sectional view detailing the frame portion 610 of the LDMOS device 600 of Figure 25, showing that the separated N-level segments 630 each have different implant depths D _N1 , D _N2 , D _N3 , D _N4 and D _N5 . Different implant depths can be controlled by changing the implantation method, such as implanting energy. The separate P top section and the separated P top section can be any number, but for the purposes of Figure 31, there are five embodiments shown. In an embodiment of the invention, the depths D _N1 , D _N2 , D _N3 , D _N4 and D _N5 may be substantially the same. In other embodiments of the invention, the depths D _N1 , D _N2 , D _N3 , D _{N4 ,} and D _N5 may be different to achieve the desired reduction in on-resistance without substantially affecting the maximum breakdown voltage. In some embodiments of the invention, the N-type ion implantation concentration in the separated N-level segment 630 and the N-energy segment width and the spacer distances S _N1 , S _N2 , S _{N3 ,} and S _N4 The P-type ion implantation concentration in the separated P top section 620 can be different, so that even if the depths D _N1 , D _N2 , D _N3 , D _{N4 ,} and D _{N5 are} different, the condition of complete depletion can be achieved. In some embodiments of the invention, the implant concentration and width, the spacer distances S _N1 , S _N2 , S _{N3 ,} and S _N4 of the separated N energy level segments 630 and the depth D _N1 , Synchronous adjustment of the implant concentration of the separate P top sections 620 of D _N2 , D _N3 , D _{N4 ,} and D _N5 can provide improved on-resistance while still maintaining a high breakdown voltage substantially and simultaneously.

Rather, any of the commonly used variables shown, such as the separate P top and N energy segments, Wi, Si, Di, relative to a conventional LDMOS device with a substantially and continuously disposed P top region, separate N Any, a combination, or even all of the separate P-top segments and separate N-energy segments of the energy-producing and separated P-top regions may be provided to provide at least 5% improvement in on-resistance, at least 10% Improved, at least 15% improvement, at least 20% improvement or at least 25% improvement.

32A is a cross-sectional view showing an N-channel metal oxide semiconductor (NMOS) device, particularly an ultra-high voltage NMOS device having a plurality of separate N-level segments and a plurality of separate Ps in accordance with an embodiment of the present invention. Top section. The embodiment of Fig. 32 shows a P substrate 700 which may form a P-type epitaxial layer in whole or in part, wherein HVNW 710 has been provided. The first P well 720 is formed in the P substrate 700 and the second P well 725 is formed in the HVNW 710, the first P well 720 has a first P ⁺ doped region 730 and the second P well 725 has a second P ⁺ doping Region 735 is adjacent to N ⁺ doped source region 740. An N ⁺ doped drain region 745 is formed in the HVNW 710. The NMOS device is shown by a separate N-level and separated P-top region 760 having a plurality of separate N-level segments and a plurality of separate P-top segments (not explicitly framed). Field oxide isolation region 770 substantially separates doped regions 730, 735 and 740, 745. The NMOS also has a control gate structure 780, an interlayer dielectric layer 785, and a conductive layer 790.

Figure 32B is a cross-sectional view showing the N-energy block of the NMOS device of Figure 32A without the separated N-level segment and the separated P-top segment.

Figure 33A is a cross-sectional view showing an insulated gate bipolar transistor (IGBT) device in accordance with an embodiment of the present invention, particularly an ultrahigh voltage IGBT device having a plurality of discrete N-level segments and a plurality of separations P top section. The embodiment of Fig. 33A shows a P substrate 800 which may form a P-type epitaxial layer in whole or in part, wherein HVNW 810 has been provided. The first P well 820 is formed in the P substrate 800 and the second P well 825 is formed in the HVNW 810, the first P well 820 has a first P ⁺ doped region 830 and the second P well 825 has a second P ⁺ doped Region 835 is adjacent to N ⁺ doped region 840. A third P ⁺ doped region 845 is formed in the HVNW 810. The NMOS device is shown by a separate N-level and separated P-top region 860 having a plurality of separate N-level segments and a plurality of separate P-top segments (not explicitly framed). Field oxide isolation region 870 substantially separates doped regions 830, 835 and 840, 845. The IGBT device also has a control gate structure 880, an interlayer dielectric layer 885, and a conductive layer 890.

Figure 33B is a cross-sectional view showing the N-energy block of the IGBT device of Figure 32A without the separated N-level segment and the separated P-top segment.

Figure 34A is a cross-sectional view of a diode in accordance with an embodiment of the present invention, particularly an ultra high voltage diode having a plurality of discrete N energy segments and a plurality of separate P top segments. The embodiment of Fig. 34A shows a P substrate 900 which may form a P-type epitaxial layer in whole or in part, wherein HVNW 910 has been provided. The first P well 920 is formed in the P substrate 900 and the second P well 825 is formed in the HVNW 810, the first P well 920 has a first P ⁺ doped region 930 and the second P well 925 has a second P ⁺ doping Region 935 is adjacent to N ⁺ source doped region 940. An N ⁺ doped drain region 945 is formed in the HVNW 910. The NMOS device is shown by a separate N-level and separated P-top region 960 having a plurality of separate N-level segments and a plurality of separate P-top segments (not explicitly framed). Field oxide isolation region 870 substantially separates doped regions 930, 935 and 940, 945. The IGBT device also has a control gate structure 980, an interlayer dielectric layer 985, and a conductive layer 990.

Figure 34B is a cross-sectional view showing the N-energy block of the undivided N-energy segment and the separated P-top segment of the dipole of Figure 34A.

Figure 35 is a flow chart of a method of fabricating an LDMOS device in accordance with an embodiment of the present invention. The method of fabricating the LDMOS device 1000 includes providing a P substrate 1010; forming a high voltage N well 10 in the P substrate; forming a P well in the P substrate and the HVNW 1030; and forming a separated P top region in the HVNW 1040, wherein the separated The P top region includes a plurality of separate P top segments. In an embodiment of the invention, the separated P top sections are interspersed between one or more separate N energy level sections.

The method of fabricating LDMOS device 1000 further includes forming a separate N energy level region in HVNW 1050, wherein the separated N energy level region includes one or more separate M energy level segments interspersed in one or more separate P top regions Between segments.

The method of fabricating the LDMOS device 1000 further includes forming a field oxide isolation region 1060; forming a control gate structure. The step of forming the control gate structure includes performing gate oxidation 1070; forming a polysilicon layer 1080 that controls the gate structure; and forming a spacer 1090 surrounding the polysilicon layer of the control gate structure.

The method for manufacturing the LDMOS device 1000 further includes: forming an N ⁺ doped region in the second P well and HVNW 1100; forming a P ⁺ doped region in the first P well and the second P well 1110; and depositing the interlayer dielectric layer 1120; And depositing a first metal layer on the inter-layer dielectric layer 1130. The method of fabricating the LDMOS device 1000 further includes, for example, forming an IMD layer and/or a second metal layer.

One aspect of the present invention is directed to the use of the present invention in a semiconductor structure formed by a process or method of forming a semiconductor gate structure. In some embodiments, the MOS device can be formed using any of the methods described herein. In a further embodiment, the LDMOS device can be formed using any of the methods described herein.

The various modifications and other embodiments of the present invention described herein will be apparent to those skilled in the art of the present invention. Other embodiments are also intended to be included within the scope of the appended claims, and the foregoing description and related drawings are in some exemplary combinations of elements and/or functions. Embodiments are described in the context of the present invention, but different combinations of elements and/or functions may be provided without departing from the scope of the alternative embodiments of the appended claims. Different combinations of functions are also contemplated as being set forth in certain appended claims; certain specific terms used in the present disclosure are only used in the generic and descriptive concepts and not for the purpose of limitation.

240‧‧‧Separated N-level and separated P-top

255‧‧‧N energy level zone

245‧‧‧Separated P-top section

260‧‧‧P substrate

270‧‧‧HVNW

280‧‧‧First P well

290‧‧‧Second P well

300‧‧‧P ⁺ doped area

310‧‧‧P ⁺ doped area

320‧‧‧N ⁺ doped source region

330‧‧‧N ⁺ doped bungee zone

340‧‧‧Field Oxidation Isolation Area

350‧‧‧Control gate structure

345‧‧ ‧ gate oxide layer

355‧‧‧ spacer

360‧‧‧Interlayer dielectric (ILD) layer

370‧‧‧First metal layer

365‧‧‧First core area

375‧‧‧Insulated area

380‧‧•Metal dielectric (IMD) layer

390‧‧‧Second metal layer

400‧‧‧ dielectric layer

Claims (21)

A semiconductor comprising: a P substrate; a high voltage N well (HVNW) disposed in the P substrate; a first P well formed in the P substrate having a first P ⁺ doped region; a second P well formed in the HVNW having a second P ⁺ doped region, wherein the second P ⁺ doped region is adjacent to an N ⁺ doped source region; and a separate N energy level And a P top region disposed in the HVNW, wherein the separated N energy level and P top region have a layer or a cross arrangement defined by a plurality of N energy level segments and a plurality of P top segments alternately arranged Multiple layers. The semiconductor of claim 1, wherein the separated N and P top regions comprise two or more layers and the plurality of P top segments and the plurality of N energy segments are in a collapse cross adjustment. The semiconductor of claim 1, wherein the semiconductor is a laterally diffused metal oxide semiconductor (LDMOS) and the HVNW has an N ⁺ doped drain region. The semiconductor of claim 3, wherein each of the plurality of P top sections of the HVNW has a depth to define a plurality of depths, a width to define a plurality of widths, and a separation distance to Define a number of separation distances. The semiconductor of claim 4, wherein each of the plurality of depths is the same depth. The semiconductor of claim 4, wherein the depth of the plurality of depths is increasing. The semiconductor described in claim 4, having a continuous P compared to the other The top region is disposed in an LDMOS device under a continuous N energy level region, wherein the plurality of depths, the plurality of widths, and the plurality of spacer distances are reduced by at least 11.6%, about 1 volt, in an on-resistance of a drain voltage. The semiconductor of claim 7, wherein a breakdown voltage of the LDMOS device is the same as a breakdown voltage of the other LDMOS device. The semiconductor of claim 3, wherein the plurality of N energy level segments in the HVNW have a depth to define a plurality of depths, a width to define a plurality of widths, and a vertical adjacent P top region A spacing distance of the segments to define a plurality of spacing distances. The semiconductor of claim 9, wherein the plurality of LDMOS devices having a continuous P top region are disposed under a continuous N energy level region, wherein the plurality of depths, a plurality of widths, and a plurality of spaced distances are At least 11.6%, approximately 1 volt, is reduced in an on-resistance of a drain voltage. The semiconductor of claim 3, further comprising an oxidation isolation region disposed to isolate a first P ⁺ doped region from a second P ⁺ doped region, wherein the second P ⁺ doped region is adjacent to And the N ⁺ doped source region and the N ⁺ doped drain region. The semiconductor of claim 11, further comprising a gate structure disposed between the N ⁺ doped source region and the N ⁺ doped drain region. The semiconductor of claim 1, wherein the semiconductor is an insulated gate bipolar transistor and the HVNW has a third P ⁺ doped region. The semiconductor of claim 1, wherein the semiconductor is a diode and the HVNW has an N ⁺ doped drain region. A method of fabricating a semiconductor, comprising: providing a P substrate layer; Forming a high voltage N well (HVNW) in the P substrate layer; forming a first P well in the P substrate; forming a second P well in the HVNW; and forming a separate N energy in the HVNW And a P top region, wherein the separated N energy level and P top region have a plurality of layers defined by a layer or a cross arrangement defined by a plurality of N energy level segments and a plurality of P top segments alternately arranged. The method of claim 15, further comprising forming an oxidation isolation region, wherein the field oxidation isolation region is overlapped by the first P-well and the second P-well and a first The two field oxidation structure is overlapped by the N energy level region. The method of claim 16, further comprising forming a gate structure. The method of claim 17, wherein the step of forming a gate structure comprises: performing a gate oxidation method; forming a polysilicon layer; and forming a spacer surrounding the gate structure. The method of claim 17, further comprising forming an N ⁺ doped source region adjacent to the gate structure in the second P-type well; forming a first P in the first P-type well ^a doped region; a second P ⁺ doped region is formed in the second P-type well; and a doped region adjacent to the second field oxide structure is formed in the HVNW. The method of claim 19, wherein the semiconductor is a laterally diffused metal oxide semiconductor and the doped region is an N ⁺ doped drain region. The method of claim 19, wherein the semiconductor is an insulated gate bipolar transistor and the doped region is a third P ⁺ doped region.