TWI544221B - Latch-up test device and method - Google Patents

Description

Latch test device and method

The present invention relates to a latch test apparatus and method, and more particularly to a latch test apparatus and method that can be used to test a wafer to be tested.

The Latch-up effect is an important factor affecting the reliability of the integrated circuit. Therefore, the integrated circuit is mostly tested for latch-up resistance before leaving the factory. In general, the manufacturing process of an integrated circuit includes circuit design, wafer fabrication, and wafer packaging. In addition, the existing latch test method utilizes a linearly increasing trigger pulse to perform a latch test on the integrated circuit during the chip packaging stage. However, since the trigger pulse is gradually increased in a linear manner, the existing latch test method often requires a large test time to complete the test of the anti-latch capability of the integrated circuit. In addition, since the existing latch test method can only test the integrated circuit in the chip packaging stage, the manufacturer often has to wait until the final stage of the manufacturing process to determine whether to re-create the integrated circuit. This in turn leads to an increase in the production cost and production time of the integrated circuit.

The present invention provides a latch test apparatus and method that can reduce test time and help reduce production cost and production time.

The latch test method of the present invention comprises the following steps. The setting operation is performed to select one of the plurality of test values covered by the test interval as the reference test value, and the trigger pulse and the preset error value are set by using the reference test value. Wherein, the benchmark test value divides the test interval into a first sub-interval and a second sub-interval. The test chip in the wafer to be tested is tested by using a trigger pulse to obtain at least one detection signal. Determining whether the test wafer is in a latched state according to at least one detection signal. When the test wafer is not in the latched state, the test interval is updated according to the first subinterval and returns to the step of performing the setting operation. When the test wafer is in a latched state, and the difference between the latch threshold and the reference test value is greater than the preset error value, the latch threshold and the test interval are respectively updated according to the reference test value and the second subinterval, and are returned The steps to perform the setting operation. The test of the test wafer is stopped when the test wafer is in the latched state and the difference between the latch threshold and the reference test value is not greater than the preset error value.

The latch test device of the present invention comprises a controller, a signal generator and a signal detector. The controller selects one of the plurality of test values covered by the test interval as the reference test value, and uses the benchmark test value to set the trigger pulse and the preset error value, and the benchmark test value divides the test interval into the first subinterval and the second Subinterval. The signal generator generates a trigger pulse according to the reference test value and transmits the trigger pulse to the test wafer in the wafer to be tested, so that the latch test device performs the test of the test wafer. The signal detector detects the signal from the test chip to obtain at least one detection signal and controls The controller determines whether the test wafer is in a latched state according to at least one detection signal. When the test wafer is not in the latched state, the controller updates the test interval according to the first sub-interval and resets the trigger pulse according to the updated test interval, so that the latch test device performs the test of the test wafer again. When the test wafer is in a latched state, and the difference between the latch threshold and the reference test value is greater than a preset error value, the controller updates the latch threshold and the test interval respectively according to the reference test value and the second subinterval, so as to cause The latch test device again tests the test wafer. The latch test device stops testing the test wafer when the test wafer is in a latched state and the difference between the latch threshold and the reference test value is not greater than the preset error value.

Based on the above, the present invention can adjust the test interval, and can select a corresponding reference test value according to the test interval, thereby setting a trigger pulse for testing the wafer to be tested. This will reduce test time and help reduce production costs and production time.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Latch test device

110‧‧‧Signal Generator

120‧‧‧Signal Detector

200‧‧‧ wafer under test

210‧‧‧Test wafer

S210~S280‧‧‧Steps in the embodiment of Figure 2

VH3, VL3, VA31~VA33‧‧‧ test values

310~330‧‧‧Value range

311, 321, 331‧‧‧ first subinterval

312, 322, 332‧‧‧ second subinterval

VA41~VA46‧‧‧ benchmark value

S510~S560‧‧‧Steps in the embodiment of Figure 5

During the period of T61~T63, T81~T83‧‧

610‧‧‧Power supply voltage

620, 810‧‧‧ trigger pulse

S710~S750‧‧‧Steps in the Figure 7 embodiment

1 is a schematic diagram of a latch test apparatus in accordance with an embodiment of the present invention.

2 is a flow chart of a latch test method in accordance with an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating the adjustment of a test interval according to an embodiment of the invention.

4 is a diagram showing the variation of a benchmark test value as a function of a test interval, in accordance with an embodiment of the present invention.

FIG. 5 is a detailed flow chart for explaining steps S220 and S230 according to an embodiment of the invention.

6 is a waveform diagram for explaining a latch test according to an embodiment of the present invention.

FIG. 7 is a detailed flow chart for explaining steps S220 and S230 according to still another embodiment of the present invention.

FIG. 8 is a waveform diagram for explaining a latch test according to an embodiment of the present invention.

1 is a schematic diagram of a latch test apparatus in accordance with an embodiment of the present invention. As shown in FIG. 1, the latch test apparatus 100 can be a test machine for testing the wafer 200 to be tested. The wafer to be tested 200 includes a test wafer 210, and the test wafer 210 includes an integrated circuit. The latch test device 100 can be electrically connected to the wafer to be tested 200 through a probe on a probe card (not shown) to perform various tests on the integrated circuit in the test wafer 210 on the wafer 200 to be tested. For example, a latch test.

The latch test apparatus 100 includes a signal generator 110, a signal detector 120, and a controller 130. The signal generator 110 can generate a trigger pulse and can transmit a trigger pulse to the test wafer 210 through the probe. In addition, the controller 130 can adjust the size of the trigger pulse (for example, vibration) according to the reference test value, so that the simulation can cause the test wafer 210 generates various trigger sources for the latch-up effect. The signal detector 120 can detect the signal on the test wafer 210 through the probe for the controller 130 to analyze the characteristics or state of the test wafer 210, thereby verifying the latch-up resistance of the integrated circuit in the test wafer 210. .

2 is a flow chart of a latch test method in accordance with an embodiment of the present invention, and the latch test performed by the latch test apparatus 100 on the wafer 200 to be tested will be further described below with reference to FIGS. 1 and 2. As shown in step S210, the latch test apparatus 100 may perform a setting operation to thereby set a reference test value, a trigger pulse, and a preset error value. Specifically, the controller 130 in the latch test apparatus 100 may select one of a plurality of test values covered by a test interval as a reference test value, and set a trigger pulse and a preset error value by using the reference test value. Wherein, the benchmark test value divides the test interval into a first sub-interval and a second sub-interval.

For example, FIG. 3 is a schematic diagram illustrating the adjustment of a test interval according to an embodiment of the invention. As shown in FIG. 3, the test interval can be, for example, a value interval 310 from the test value VL3 to the test value VH3. The controller 130 can set the test value VA31 in the value interval 310 as the reference test value, and can further set the trigger pulse according to the reference test value. In addition, the controller 130 can bring the reference test value VA31 into an arithmetic expression to calculate a preset error value. For example, if VA31 = a × 10 ^b , the calculated preset error value can be expressed as 10 ^{( b -2)} , where 1 ≦ a < 10 and b is an integer. That is, when VA31=300 mA, the preset error value is equal to 1 mA. When VA31 = 20 mA, the preset error value is equal to 0.1 mA. Furthermore, the benchmark value VA31 can divide the value interval 310 into the first sub-interval 311 and the second sub-interval 312, and the test value in the first sub-interval 311 is greater than the reference test value VA31, and the test in the second sub-interval 312 The value is less than the reference test value VA31.

As shown in step S220, the signal generator 110 can generate a trigger pulse according to the reference test value. Additionally, the signal generator 110 can transmit a trigger pulse to the test wafer 210 to latch the test device 100 to test the test wafer 210. The signal detector 120 can detect the signal from the test chip 210 and generate at least one detection signal accordingly. Furthermore, as shown in step S230 and step S240, the controller 130 can determine whether the test wafer 210 is in a latched state according to the at least one detection signal, and can determine whether the difference between the latch threshold value and the reference test value is greater than Preset error value.

When the controller 130 determines that the test wafer 210 is not in the latched state, that is, when the integrated circuit in the test wafer 210 does not generate a latch-up effect, as shown in step S250, the controller 130 may update the test interval according to the first sub-interval. And returns to step S210. For example, as shown in FIG. 3, when the test result obtained by using the test value VA31 is that the test wafer 210 does not generate a latch-up effect, the controller 130 may update the test interval according to the first sub-interval 311, thereby causing the test interval. It is updated to a value interval 320 from the test value VA31 to the test value VH3. In addition, the latch test apparatus 100 may repeat step S210 to select the test value VA32 from the updated test interval (ie, the value interval 320) as a new benchmark test value and utilize the new benchmark test value (ie, , test value VA32) to reset the trigger pulse and the preset error value. The new benchmark value (ie, the test value VA32) may divide the updated test interval (ie, the value interval 320) into the first sub-interval 321 and the second sub-interval 322.

Furthermore, the latch test apparatus 100 can repeat steps S210 to S230 to facilitate The test of the test wafer 210 is again performed with the reset trigger pulse, and the test result of the test wafer 210 is analyzed again. On the other hand, when the controller 130 determines that the test wafer 210 is in the latched state (ie, the integrated circuit in the test wafer 210 generates a latch-up effect), and the difference between the latch-off threshold and the reference test value is greater than the preset error. When the value is as shown in step S260 and step S270, the controller 130 may update the latching threshold according to the reference test value, and may update the test interval according to the second subinterval.

For example, as shown in FIG. 3, when the test result obtained by using the test value VA32 generates a latch-up effect for the test wafer 210, and the difference between the latch-off threshold value and the reference test value is greater than the preset error value, the controller 130 may update the latch threshold according to the benchmark value (ie, test value VA32), and may update the test interval according to the second subinterval 322, thereby causing the test interval to be updated to a value from the test value VA31 to the test value VA32. Interval 330. In addition, the latch test apparatus 100 may repeat step S210 to select the test value VA33 from the updated test interval (ie, the value interval 330) as a new reference test value, and utilize the new reference test value (ie, Test value VA33) to reset the trigger pulse and preset error value. The new benchmark value (ie, the test value VA33) may divide the updated test interval (ie, the value interval 330) into the first sub-interval 331 and the second sub-interval 332.

By analogy, the latch test apparatus 100 can continuously update the test interval and use the updated test interval to reset the trigger pulse to perform the test of the test wafer 210 again. In addition, when the test result of the test wafer 210 is that the test wafer 210 is in the latched state, and the difference between the latch threshold and the reference test value is not greater than the preset error value, the latch test apparatus 100 is as shown in step S280. Will stop testing Test the test wafer 210. In addition, the latching threshold ultimately achieved by the latch test device 100 will be used to define the ability of the integrated circuit in the test wafer 210 to protect against latch-up effects.

It is worth mentioning that since the latch test device 100 can continuously update the test interval, the latch test device 100 can take less test times to complete the test of the test wafer 210. For example, FIG. 4 is a schematic diagram illustrating changes in a benchmark test value as a function of a test interval, in accordance with an embodiment of the present invention. In the embodiment of Figure 4, the initial test interval can be, for example, from 0 to 500 mA. In the first test, the latch test apparatus 100 tests the test wafer 210 according to the reference test value VA41 (ie, 250 mA), and the analyzed test result is that the test wafer 210 is not in a latched state, so the latch The lock test device 100 updates the test interval using the upper half interval (ie, the first subinterval) in the test interval. Thereby, in the second test, the latch test apparatus 100 will be able to test the test wafer 210 based on a larger reference test value VA42 (ie, 375 mA).

In addition, the second test result produces a latch-up effect on the test wafer 210, and the difference between the latch-off threshold and the reference test value is greater than the preset error value. Therefore, the latch test apparatus 100 can update the test section using the lower half interval (ie, the second subinterval) in the test section, and update the latch threshold using the reference test value VA42. Thereby, in the third test, the latch test apparatus 100 will be able to test the test wafer 210 based on the smaller reference test value VA43 (i.e., 312.5 mA). Further, based on the third test result, the latch test apparatus 100 can update the latch threshold using the reference test value VA43.

By analogy, the latch test apparatus 100 can continually update the test interval and adjust the reference test value accordingly. In addition, the latch test apparatus 100 can update the latch threshold value by using the reference test value VA44 (ie, 304.6875 mA) and the reference test value VA45 (ie, 300.78125 mA) in sequence according to the test result. Further, in the ninth test, the latch test apparatus 100 can test the test wafer 210 based on the reference test value VA46 (ie, 299.8203125 mA). In addition, the ninth test result is that the test wafer 210 is in a latched state, and the difference between the latch threshold and the reference test value is not greater than a preset error value (1 mA). Thus, the latch test apparatus 100 will stop testing the wafer 210 for testing, and the resulting latched threshold (i.e., 300.78125 mA) will be used to define the latch-up resistance of the integrated circuitry in the test wafer 210.

It is worth mentioning that the existing latch test method is to gradually increase the trigger pulse in a linear manner. Therefore, for the existing latch test method, it is necessary to repeatedly perform the latch test of the test wafer 210 by using the trigger pulses of 1 mA, 2 mA, 3 mA, ..., 300 mA in sequence. In other words, the existing latch test method must perform a latch test of 300 times in order to verify the latch-up resistance of the test wafer 210. Therefore, the latch test apparatus 100 can effectively reduce the test time of the test wafer 210 compared to the existing latch test method. In addition, the latch test apparatus 100 can directly test the test wafer 210 in the wafer 200 to be tested, that is, the latch test apparatus 100 can perform a latch test for the integrated circuit at the wafer fabrication stage. Therefore, the latch test apparatus 100 can also effectively reduce the production cost and production time of the integrated circuit as compared with the existing latch test method.

In order to make the present invention more familiar to those skilled in the art, the detailed steps of step S220 and step S230 in FIG. 2 will be further explained below. For example, FIG. 5 is a detailed flowchart for explaining steps S220 and S230 according to an embodiment of the present invention.

For the detailed steps of step S220, as shown in steps S510 and S520, the signal generator 110 can supply a power supply voltage to the power pad of the test wafer 210 and can provide a trigger pulse to the input pad of the test wafer 210. In addition, as shown in step S530, before and after the trigger pulse is provided, the signal detector 120 can respectively detect the current flowing through the power pad to obtain the first initial current and the first of the at least one detection signal. Detect current.

For example, FIG. 6 is a waveform diagram for explaining a latch test according to an embodiment of the invention. As shown in FIG. 6, during the period T61~T63, the signal generator 110 can supply the power supply voltage 610 to the power pad of the test wafer 210. Additionally, during a period T62, the signal generator 110 can provide a trigger pulse 620 to the input pads of the test wafer 210. Moreover, before the trigger pulse 620 is provided, that is, during the period T61, the signal detector 120 can detect the current flowing through the power pad to obtain the first initial current. After the trigger pulse 620 is provided, that is, during the period T63, the signal detector 120 can also detect the current flowing through the power pad to obtain the first detection current. Additionally, the trigger pulse 620 can be, for example, a positive pulse current. In another embodiment, the trigger pulse 620 can also be, for example, a negative pulse current.

For the detailed step of step S230, as shown in step S540, the controller 130 may compare the first detection current with the first initial current to determine the first detection power. Whether the flow is greater than the first initial current. Moreover, when the first detection current is greater than the first initial current, as shown in step S550, the controller 130 may determine that the test wafer 210 is in a latched state. On the other hand, when the first detection current is not greater than the first initial current, the controller 130 may determine that the test wafer 210 is not in the latched state.

FIG. 7 is a detailed flow chart for explaining steps S220 and S230 according to still another embodiment of the present invention, and FIG. 8 is a waveform diagram for explaining a latch test according to an embodiment of the present invention. In the detailed step of step S220, as shown in step S710, the signal generator 110 can provide a power supply pad to the test wafer 210. For example, referring to FIG. 8, during a period T82, the signal generator 110 can provide a trigger pulse 810 to the power pad of the test wafer 210, and the trigger pulse 810 can be, for example, a positive pulse voltage.

Moreover, as shown in step S720, before and after the trigger pulse is provided, the signal detector 120 can respectively detect the current flowing through the power pad to obtain the initial current and the detection current in the at least one detection signal. . For example, referring to FIG. 8, before the trigger pulse 810 is provided, that is, during the period T81, the signal detector 120 can detect the current flowing through the power pad to obtain the initial current. After the trigger pulse 810 is provided, that is, during the period T83, the signal detector 120 can detect the current flowing through the power pad to obtain the detection current.

In the detailed step of step S230, as shown in step S730, the controller 130 compares the detected current with the initial current to determine whether the detected current is greater than the initial current. In addition, when the detected current is greater than the initial current, as shown in step S740, the controller 130 may determine that the test wafer 210 is in a latched state. On the other hand, when The measured current is not greater than the initial current. As shown in step S750, the controller 130 may determine that the test wafer is not in a latched state.

In summary, the present invention can adjust the test interval, and can select a corresponding reference test value according to the test interval, thereby setting a trigger pulse for testing the wafer to be tested. Thereby, the number of tests of the wafer to be tested can be effectively reduced, thereby helping to reduce the test time. Further, the present invention can perform a latch test for the integrated circuit at the wafer manufacturing stage, and thus can effectively reduce the production cost and production time of the integrated circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

S210~S280‧‧‧Steps in the embodiment of Figure 2

Claims (8)

A latch test method includes: performing a setting operation to select one of a plurality of test values covered by a test interval as a reference test value, and use the benchmark test value to set a trigger pulse and a preset error value The benchmark test value divides the test interval into a first sub-interval and a second sub-interval; transmitting the trigger pulse to a test wafer in a wafer to be tested for testing the test wafer, and detecting from The signal of the test chip is used to obtain at least one detection signal; determining whether the test chip is in a latched state according to the at least one detection signal; and updating the first sub-interval according to the first sub-interval when the test chip is not in the latched state The test interval, and returning to the step of performing the setting operation; when the test wafer is in the latched state, and a difference between the latch threshold and the reference test value is greater than the preset error value, according to the benchmark test And updating the latch threshold and the test interval respectively to the second subinterval and returning to the step of performing the setting operation; and when the test wafer is in the latched state When the latch and the reference test threshold value difference is not greater than the predetermined error value, stop the test of the test wafer. The latch test method of claim 1, wherein the trigger pulse is transmitted to the test wafer in the wafer to be tested to perform the test of the test wafer, and the signal from the test wafer is detected. Obtaining at least one detection signal The method includes: providing a power voltage to a power pad of the test chip; providing the trigger pulse to an input pad of the test chip; and detecting the flow through the power pad before and after providing the trigger pulse The current is obtained to obtain a first initial current and a first detection current of the at least one detection signal. The latch test method of claim 2, wherein the step of determining whether the test wafer is in the latched state according to the at least one detection signal comprises: comparing the first detection current with the first initial current When the first detection current is greater than the first initial current, determining that the test wafer is in the latched state; and when the first detection current is not greater than the first initial current, determining that the test wafer is not In this latched state. The latch test method of claim 1, wherein the trigger pulse is transmitted to the test wafer in the wafer to be tested to perform the test of the test wafer, and the signal from the test wafer is detected. The step of obtaining the at least one detection signal includes: providing the trigger pulse to a power pad of the test chip; detecting current flowing through the power pad before and after providing the trigger pulse to obtain the at least An initial current and a detection current in a detection signal. The latch test method according to claim 4, wherein the basis is The step of determining whether the test chip is in the latched state by the at least one detecting signal comprises: comparing the detecting current with the initial current; and when the detecting current is greater than the initial current, determining that the test wafer is in the latching a state; and when the detection current is not greater than the initial current, determining that the test wafer is not in the latched state. A latch test device includes: a controller that selects one of a plurality of test values covered by a test interval as a reference test value, and uses the reference test value to set a trigger pulse and a preset error value, and The reference test value divides the test interval into a first sub-interval and a second sub-interval; a signal generator generates the trigger pulse according to the reference test value, and transmits the trigger pulse to a wafer to be tested a test chip for causing the latch test device to perform the test of the test chip; and a signal detector for detecting a signal from the test chip to obtain at least one detection signal, and the controller is based on the at least one The detecting signal determines whether the test chip is in a latched state. When the test chip is not in the latched state, the controller updates the test interval according to the first sub-interval and resets according to the updated test interval. The trigger pulse causes the latch test device to perform the test of the test wafer again, when the test wafer is in the latched state, and a latch threshold is Benchmarks When the difference between the trial values is greater than the preset error value, the controller updates the latch threshold and the test interval according to the reference test value and the second sub-interval respectively, so that the latch test device performs the test again. The test of the wafer, when the test wafer is in the latched state, and the difference between the latch threshold and the reference test value is not greater than the preset error value, the latch test device stops the test of the test wafer. The latch test device of claim 6, wherein the signal generator supplies a power supply voltage to a power pad of the test chip and provides the trigger pulse to an input pad of the test chip. Before and after the trigger pulse is supplied, the signal detector detects the current flowing through the power pad to obtain a first initial current and a first detection current of the at least one detection signal, the control Comparing the first detection current with the first initial current, when the first detection current is greater than the first initial current, the controller determines that the test wafer is in the latched state, when the first detection When the current is not greater than the first initial current, the controller determines that the test wafer is not in the latched state. The latch test device of claim 6, wherein the signal generator provides the trigger pulse to a power pad of the test chip, before and after the trigger pulse is provided, the signal detector respectively Detecting a current flowing through the power pad to obtain an initial current and a detection current in the at least one detection signal, the controller comparing the detection current with the initial current, when the detection current is greater than At the initial current, the controller determines that the test wafer is in the latched state. When the detected current is not greater than the initial current, the controller determines that the test wafer is not in the latched state.