JP2019039768A - Tester, method for controlling tester, and method for manufacturing electronic device - Google Patents

Abstract

To provide a tester with which it is possible to improve the reliability of test of a load under test that is executed with an AC voltage outputted by an AC power supply.SOLUTION: The tester comprises: a zero-cross trigger generation unit for outputting a zero-cross trigger signal that is inverted synchronously with the timing at which the AC voltage outputted by an AC power supply becomes zero; a successive peak check unit for comparing the peak voltage of the AC voltage with a preset reference voltage synchronously with the zero-cross trigger signal to determine whether or not the peak voltage is within a reference voltage range defined by the reference voltage and outputting a peak determination signal; a successive cycle check unit for determining whether or not the cycle of the zero-cross trigger signal is in a preset reference cycle range and outputting a cycle determination signal; and a control device for executing test of a load under test on the basis of the voltage value of the output voltage of a load under test, and determining, on the basis of the peak determination signal and cycle determination signal, whether or not the AC voltage is normally applied to the load under test during the test of the load under test.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a test apparatus, a test apparatus control method, and an electronic apparatus manufacturing method.

  2. Description of the Related Art Conventionally, in a test apparatus that executes a test by measuring an output signal by applying an alternating current to a load under test (regulator) using an alternating current power supply (see, for example, Patent Document 1), the alternating current power supply has a normal alternating voltage. In the case where an abnormality occurs in the output AC voltage, there was no mechanism for detecting this abnormality.

  Therefore, even if there is an abnormality in the output of the AC voltage used for the test, it does not affect the measured value of the load under test, or if the measured value is within the allowable range, the abnormality in the output of the AC voltage used in the test Regardless of this, the test will be executed correctly.

Japanese Patent Laying-Open No. 2015-082913

  As described above, in the conventional test apparatus, there is a problem that the reliability of the test of the load under test performed with the AC voltage output from the AC power supply is lowered.

  Therefore, an object of the present invention is to provide a test apparatus capable of improving the reliability of a test of a load under test performed with an AC voltage output from an AC power supply.

A test apparatus according to an embodiment of one aspect of the present invention includes:
A test apparatus for testing a load under test with an alternating voltage,
An AC power supply for outputting the AC voltage to the load under test;
A zero-cross trigger generator that outputs a zero-cross trigger signal that is input when the AC voltage is input and is inverted when the AC voltage becomes zero;
In synchronization with the zero-cross trigger signal, the peak voltage of the AC voltage is compared with a preset reference voltage to determine whether the peak voltage is within a reference voltage range defined by the reference voltage, A peak sequential check unit that outputs a peak determination signal based on the determination result;
A cycle sequential check unit that determines whether or not the cycle of the zero-cross trigger signal is within a preset reference cycle range and outputs a cycle determination signal based on the determination result;
Measure the output voltage output by the load under test according to the input of the AC voltage, and output a voltage value of the output voltage; and
Controlling the AC power supply, applying the AC voltage to the load under test, and executing the test of the load under test based on the voltage value of the output voltage of the load under test measured by the voltmeter, A controller for determining whether or not the AC voltage is normally applied to the load under test during the test of the load under test based on the peak determination signal and the cycle determination signal. To do.

In the test apparatus,
The control device includes:
When the peak determination signal indicates that the peak voltage is not in the reference voltage range, or when the cycle determination signal indicates that the period of the zero cross trigger signal is not in the reference period range, the load under test It is determined that the AC voltage is not normally applied to the load under test during the test.

In the test apparatus,
The control device includes:
When the peak determination signal indicates that the peak voltage is in the reference voltage range, and the cycle determination signal indicates that the period of the zero cross trigger signal is in the reference period range, It is judged that the AC voltage is normally applied to the load under test during the test.

In the test apparatus,
The control device further includes an output device that outputs a determination result as to whether or not the AC voltage is normally applied to the load under test during the test of the load under test.

In the test apparatus,
The peak sequential check unit
A peak hold unit that holds the peak voltage of the AC voltage in synchronization with the zero-cross trigger signal;
A peak level comparison unit that compares the peak voltage held by the peak hold unit with the reference voltage and outputs a comparison result signal according to the comparison result;
A peak determination unit that determines whether or not the peak of the AC voltage is in the reference voltage range based on the comparison result signal and outputs the peak determination signal based on the determination result. And

In the test apparatus,
The cycle sequential check unit includes:
A periodic distributor for distributing the zero-cross trigger signal to a first distribution signal and a second distribution signal having the same period and frequency as the first distribution signal;
It is determined whether or not the first pulse period from when the pulse of the zero cross trigger signal rises until the pulse of the first distribution signal falls is within a preset reference pulse period. A first cycle determination unit that outputs a first cycle determination signal based on
It is determined whether or not the second pulse period from when the pulse of the zero cross trigger signal rises until the pulse of the second distribution signal falls is within the reference pulse period, and based on this determination result A second cycle determination unit that outputs a second cycle determination signal;
A logic circuit that receives the first and second cycle determination signals and outputs a signal obtained by calculating the first and second cycle determination signals as the cycle determination signal. .

In the test apparatus,
The logic circuit is:
An OR circuit that performs an OR operation on the first and second cycle determination signals and outputs a signal obtained by the OR operation as the cycle determination signal.

In the test apparatus,
The control device includes:
The reference pulse period corresponding to the AC voltage applied to the load under test by controlling the AC power source is set in the first and second cycle determination units.

In the test apparatus,
The control device includes:
The reference voltage corresponding to the AC voltage applied to the load under test by controlling the AC power supply is supplied to the peak sequential check unit.

In the test apparatus,
The circuit configuration and function of the first cycle determination unit are the same as the circuit configuration and function of the second cycle determination unit.

In the test apparatus,
The control device includes:
The determination operation of the peak determination unit is started by outputting a chip select signal to the peak determination unit.

In the test apparatus,
The peak determination unit
Cancel the reset of the peak voltage hold of the peak hold unit at the first level of the zero cross trigger signal,
Determining whether the peak of the AC voltage is within the reference voltage range based on the comparison result signal at the second level of the zero-cross trigger signal;
Then, the peak voltage hold of the peak hold unit is reset.

A control method of a test apparatus according to an embodiment according to an aspect of the present invention includes:
A test apparatus for testing a load under test with an AC voltage, the AC power source outputting the AC voltage to the load under test, and a zero cross trigger that reverses when the AC voltage is input and the AC voltage becomes zero A zero-cross trigger generator that outputs a signal, a peak voltage of the AC voltage is compared with a preset reference voltage in synchronization with the zero-cross trigger signal, and the peak voltage is defined by the reference voltage A peak sequential check unit that outputs a peak determination signal based on the determination result, and determines whether or not the period of the zero cross trigger signal is within a preset reference period range. The cycle sequential check unit that outputs a cycle determination signal based on the determination result, and the load under test outputs according to the input of the AC voltage A force voltage is measured, a method of controlling a test apparatus including a voltage meter for outputting a voltage value of the output voltage, and a control unit, a
The control device controls the AC power supply, applies the AC voltage to the load under test, and tests the load under test based on the voltage value of the output voltage of the load under test measured by the voltmeter. And determining whether or not the AC voltage is normally applied to the load under test during the test of the load under test based on the peak determination signal and the cycle determination signal. .

An electronic component manufacturing method according to an embodiment of one aspect of the present invention includes:
Manufacturing electronic components;
Testing the electronic component being a load under test with an alternating voltage by the test device;
A step of performing processing according to the result of testing the electronic component,
It is determined whether or not the AC voltage is normally applied to the electronic component during the testing of the electronic component by the test apparatus.

In the method of manufacturing the electronic component,
The processing according to the result of testing the electronic component includes determining whether the result of testing the electronic component is good or changing manufacturing conditions of a manufacturing apparatus for manufacturing the electronic component. .

  A test apparatus according to an aspect of the present invention is a test apparatus for testing a load under test with an AC voltage, and an AC power source that outputs an AC voltage to the load under test, an AC voltage is input, and the AC voltage is zero. The zero-cross trigger generator that outputs a zero-cross trigger signal that is inverted at the same timing, and the peak voltage of the AC voltage is compared with a preset reference voltage in synchronization with the zero-cross trigger signal, and the peak voltage is defined by the reference voltage. A peak sequential check unit that outputs a peak determination signal based on the determination result, and whether or not the cycle of the zero-cross trigger signal is within a preset reference cycle range. A cycle sequential check unit for determining and outputting a cycle determination signal based on the determination result, and measuring an output voltage output by the load under test in response to an input of an AC voltage. Then, based on the voltage value of the output voltage of the load under test measured by the voltmeter, the voltmeter that outputs the voltage value of the output voltage, the AC power supply is controlled and the AC voltage is applied to the load under test. And a control device that executes a test of the test load and determines whether or not an AC voltage is normally applied to the load under test during the test of the load under test based on the peak determination signal and the cycle determination signal. .

  As described above, in the test apparatus of the present invention, each of the peak and cycle of the AC voltage output from the AC power supply is sequentially monitored while the test of the load under test is performed with the AC voltage output from the AC power supply. It is determined whether or not there is an abnormality in the AC voltage output by.

  Thereby, when there is no abnormality in the AC voltage output from the AC power source, it is proved that the test is effective.

  That is, according to the test apparatus of the present invention, it is possible to improve the reliability of the test of the load under test performed with the AC voltage output from the AC power supply.

FIG. 1 is a diagram illustrating an example of a configuration of a test apparatus 100 according to the first embodiment. FIG. 2 is a diagram illustrating an example of the configuration of the cycle sequential check unit SX of the test apparatus 100 illustrated in FIG. FIG. 3 is a waveform diagram showing an example of each signal waveform of the cycle sequential check unit SX shown in FIG. FIG. 4 is a diagram illustrating an example of each signal waveform when the determination result of the cycle sequential check unit SX illustrated in FIG. 2 is GOOD. FIG. 5 is a diagram illustrating an example of each signal waveform when the determination result of the cycle sequential check unit SX illustrated in FIG. 2 is NG. FIG. 6 is a diagram illustrating an example of the configuration of the peak sequential check unit PX of the test apparatus 100 illustrated in FIG. FIG. 7 is a diagram illustrating an example of each signal waveform when the determination result of the peak sequential check unit PX illustrated in FIG. 6 is GOOD. FIG. 8 is a diagram illustrating an example of each signal waveform when the determination result of the peak sequential check unit PX illustrated in FIG. 6 is NG. FIG. 9 is a diagram illustrating an example of a flow of a method for manufacturing an electronic component using the test apparatus 100 illustrated in FIG.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

First embodiment

  FIG. 1 is a diagram illustrating an example of a configuration of a test apparatus 100 according to the first embodiment.

  For example, as shown in FIG. 1, the test apparatus 100 according to the first embodiment tests a load under test DUT with an AC voltage VAC. The load under test DUT is an electronic component such as a regulator.

  As shown in FIG. 1, for example, the test apparatus 100 includes an AC power supply AC, a zero cross trigger generation unit ZX, a peak sequential check unit PX, a cycle sequential check unit SX, a voltmeter VX, and a control device CPU. And an output device OX.

  As shown in FIG. 1, the AC power supply AC outputs the AC voltage VAC to the load DUT to be tested.

  As shown in FIG. 1, the voltmeter VX measures the output voltage VOUT output from the load under test DUT according to the input of the AC voltage VAC, and outputs the measured voltage value of the output voltage VOUT. It has become.

  When the test apparatus 100 tests the load under test DUT, the load under test DUT is connected between the output of the AC power supply AC and the input of the voltmeter DX.

  Further, as shown in FIG. 1, the zero-cross trigger generation unit ZX receives the AC voltage VAC output from the AC power supply AC, and outputs a zero-cross trigger signal ZCT that is inverted when the AC voltage VAC becomes zero. ing.

  As shown in FIG. 1, the cycle sequential check unit SX determines whether or not the cycle of the zero cross trigger signal ZCT output from the zero cross trigger generation unit ZX is within a preset reference cycle range BF. A cycle determination signal SD based on the result is output.

  Here, FIG. 2 is a diagram illustrating an example of the configuration of the cycle sequential check unit SX of the test apparatus 100 illustrated in FIG. FIG. 3 is a waveform diagram showing an example of each signal waveform of the cycle sequential check unit SX shown in FIG.

  The cycle sequential check unit SX illustrated in FIG. 1 includes, for example, a periodic distributor DX, a first cycle determination unit SA1, a second cycle determination unit SA2, and a logic circuit RC as illustrated in FIG.

  Then, the periodic distributor DX distributes the zero-cross trigger signal ZCT into the first distribution signal Div1 and the second distribution signal Div2 having the same period and frequency as the first distribution signal Div1. (FIG. 3).

  Then, the first cycle determination unit SA1 has a first pulse period P1 from when the pulse of the zero cross trigger signal ZCT rises until the pulse of the first distribution signal Div1 falls for the first reference pulse period BP ( It is determined whether it is within the cycle reference value), and the first cycle determination signal SD1 is output based on the determination result.

  The first cycle determination unit SA1 starts a determination operation in response to a chip select signal CS and a start signal CYCSTRT output from the control device CPU.

  The first cycle determination signal SD1 is set to have a reference pulse period BP corresponding to the AC voltage VAC applied to the DUT under test by controlling the AC power supply AC by the control device CPU.

  Then, the second cycle determination unit SA2 determines whether or not the second pulse period P2 from when the pulse of the zero cross trigger signal ZCT rises until the pulse of the second distribution signal Div2 falls is within the reference pulse period BP. The second cycle determination signal SD2 is output based on the determination result.

  The second cycle determination unit SA2 is configured to start the determination operation according to the chip select signal CS and the start signal CYCSTRT output from the control device CPU.

  The second cycle determination signal SD2 is set to have a reference pulse period BP corresponding to the AC voltage VAC applied to the DUT under test by controlling the AC power supply AC by the control device CPU.

  The circuit configuration and function of the first cycle determination unit SA1 are the same as the circuit configuration and function of the second cycle determination unit SA2.

  Accordingly, the first and second cycle determination units SA1 and SA2 between the first cycle determination signal SD1 output from the first cycle determination unit SA1 and the second cycle determination signal SD2 output from the second cycle determination unit SA2. Errors due to the circuit configuration and function can be reduced.

  Further, for example, as shown in FIG. 2, the logic circuit RC receives the first and second cycle determination signals SD1 and SD2 and receives the signals obtained by calculating the first and second cycle determination signals SD1 and SD2. Is output as a cycle determination signal SD.

  For example, as shown in FIG. 4, the logic circuit RC performs an OR operation on the first and second cycle determination signals SD1 and SD2, and outputs a signal obtained by the OR operation as a cycle determination signal SD. It is.

  Here, FIG. 4 is a diagram illustrating an example of each signal waveform when the determination result of the cycle sequential check unit SX illustrated in FIG. 2 is GOOD. FIG. 5 is a diagram illustrating an example of each signal waveform when the determination result of the cycle sequential check unit SX illustrated in FIG. 2 is NG. In addition, although operation | movement of 1st cycle determination part SA1 is demonstrated as an example here, operation | movement of 2nd cycle determination part SA2 is demonstrated similarly.

  For example, as shown in FIG. 4, at time t11, the first cycle determination unit SA1 starts the cycle check operation when the chip select signal CS and the start signal CYCSTR become “Low” level.

  At time t12, the first cycle determination unit SA1 starts counting a preset timer at the rising edge of the first distribution signal Div1.

  And 1st cycle determination part SA1 stops the count of the said timer, after confirming the rising from the falling of the zero cross trigger signal ZCT in order (time t13).

  Then, when comparing the counted timer value with the set value, the first cycle determination unit SA1 determines that there is no abnormality (GOOD) because the timer value is within the range of the cycle reference value described above (D1). To “Low” level).

  Thereafter, at time t14, the first cycle determination unit SA1 starts counting the timer described above at the rising edge of the first distribution signal Div1.

  And 1st cycle determination part SA1 stops the count of the said timer, after confirming a rising in order from the falling of the zero cross trigger signal ZCT (time t15).

  Then, when comparing the counted timer value with the set value, the first cycle determination unit SA1 determines that there is no abnormality (GOOD) because the timer value is within the range of the cycle reference value (D1 is set to “Low”). “To the level”.

  Thereafter, the same operation is repeated, and when the start signal CYCSTR output from the control device CPU becomes the “High” level at time t17, the first cycle determination unit SA1 ends the cycle check operation.

  In the example of FIG. 4, the first cycle determination unit SA1 only determines that there is no abnormality (GOOD) (D1 is “Low” level), and the abnormality (NG) is not stored, so this determination result (GOOD) ) Based on the first cycle determination signal SD1 ("Low" level).

  As described above, the first cycle determination unit SA1 is set in advance with the first pulse period P1 (timer value) from when the pulse of the zero cross trigger signal ZCT rises until the pulse of the first distribution signal Div1 falls. If it is determined that it is within the reference pulse period BP (cycle reference value), a first cycle determination signal SD1 (“Low” level) based on the determination result (GOOD) is output.

  Note that the first cycle determination unit SA1 processes the first determination as invalid because the determination before the first time t13 may be started from the middle of the cycle of the AC voltage VAC.

  The first cycle determination unit SA1 latches the determination until the next chip select signal CS is input.

  Next, for example, as illustrated in FIG. 5, the cycle of the AC voltage VAC may be reduced after the processing similar to that in FIG. In this case, at time t14a, the first cycle determination unit SA1 starts counting the timer described above at the rising edge of the first distribution signal Div1.

  Then, the first cycle determination unit SA1 sequentially checks the rising edge from the falling edge of the zero-cross trigger signal ZCT, and then stops counting the timer (time t15a).

  Then, the first cycle determination unit SA1 compares the counted timer value with the set value, and determines that there is an abnormality (NG) because the timer value is outside the range of the cycle reference value described above (D1 is “ High ”level).

  At this time, the first cycle determination unit SA1 stores the determination result (abnormality (NG)) in the memory.

  Thereafter, when the same operation is repeated and the cycle of the AC voltage VAC returns, the first cycle determination unit SA1 compares the counted timer value with the set value at time t16, and the timer value becomes the cycle reference value. Therefore, it is determined that there is no abnormality (GOOD) (D1 is set to “Low” level).

  After that, when the start signal CYCSTR output from the control device CPU becomes “High” level at time t17, the first cycle determination unit SA1 ends the cycle check operation.

  In the example of FIG. 5, the first cycle determination unit SA1 has an abnormality determination (NG) determination (D1 is “High” level), and the abnormality (NG) is stored. Therefore, the determination result (NG) The first cycle determination signal SD1 (“High” level) based on the above is output.

  As described above, the first cycle determination unit SA1 is set in advance with the first pulse period P1 (timer value) from when the pulse of the zero cross trigger signal ZCT rises until the pulse of the first distribution signal Div1 falls. If it is determined that it is within the reference pulse period BP (cycle reference value), a first cycle determination signal SD1 (“High” level) based on this determination result (NG) is output.

  Here, in the examples of FIGS. 4 and 5, the first cycle determination unit SA1 has a timer value determination process, but the first distribution signal Div1 and the second distribution signal Div2 are shifted by a half cycle. Therefore, another second cycle determination unit SA2 can execute the count process at the timing of the determination process of the first cycle determination unit SA1.

  As described above, the first cycle determination unit SA1 has the first pulse period P1 (timer value) from when the pulse of the zero cross trigger signal ZCT rises until when the pulse of the first distribution signal Div1 falls. If it is determined that it is within a preset reference pulse period BP (cycle reference value), a first cycle determination signal SD1 based on the determination result D1 is output.

  Further, the second cycle determination unit SA2 is configured such that the second pulse period P2 (timer value) from when the pulse of the zero cross trigger signal ZCT rises to when the pulse of the second distribution signal Div2 falls for the first time is a preset reference. If it is determined that it is within the pulse period BP (cycle reference value), a second cycle determination signal SD2 based on the determination result D2 is output.

  As described above, the logic circuit RC receives the first and second cycle determination signals SD1 and SD2 and inputs the signals obtained by calculating the first and second cycle determination signals SD1 and SD2 to the cycle. Output as determination signal SD.

  As a result, the cycle sequential check unit SX can sequentially monitor the cycle of the AC voltage VAC.

  Further, as shown in FIG. 1, the peak sequential check unit PX compares the peak voltage of the AC voltage VAC with a preset reference voltage Vref (peak reference value) in synchronization with the zero cross trigger signal ZCT, It is determined whether or not the voltage is in a reference voltage range VrefX defined by the reference voltage Vref. The peak sequential check unit PX outputs a peak determination signal PD based on the determination result.

  Here, FIG. 6 is a diagram illustrating an example of the configuration of the peak sequential check unit PX of the test apparatus 100 illustrated in FIG.

  The peak sequential check unit PX illustrated in FIG. 1 includes a peak hold unit PH, a peak level comparison unit COMP, and a peak determination unit PK, for example, as illustrated in FIG.

  The peak hold unit PH is configured to hold the peak voltage SPH of the AC voltage VAC in synchronization with the zero cross trigger signal ZCT output from the zero cross trigger generation unit ZX.

  The peak level comparison unit COMP compares the peak voltage SPH held by the peak hold unit PH with the reference voltage Vref, and outputs a comparison result signal SCOMP according to the comparison result.

  In addition, this peak level comparison part COMP is a window comparator, for example.

  Further, the peak determination unit PK starts the determination operation of the peak determination unit PK in accordance with the chip select signal CS output from the control device CPU.

  Then, the peak determination unit PK determines whether or not the peak of the AC voltage VAC is in the above-described reference voltage range VrefX based on the comparison result signal SCOMP output from the peak level comparison unit COMP. The peak determination signal PD is output based on the above.

  The peak determination unit PK is supplied with a reference voltage Vref corresponding to the AC voltage VAC applied to the load DUT by controlling the AC power supply AC by the control device CPU.

  The peak determination unit PK resets the hold of the peak voltage of the peak hold unit PH by the release signal SR (“High” level) at the falling edge (first level: “Low” level) of the zero cross trigger signal ZCT. It comes to cancel.

  Then, the peak determination unit PK determines whether the peak of the AC voltage VAC is in the reference voltage range VrefX based on the comparison result signal SCOMP at the rising edge of the zero cross trigger signal ZCT (second level: “High” level). It comes to judge.

  And the peak determination part PK resets the hold | maintenance of the peak voltage of the peak hold part PH after the said determination.

  Note that the above-described reference voltage range VrefX is defined by, for example, a range VrefX between two different reference voltages Vrefa and Vrefb (upper reference voltage Vrefa and lower limit reference voltage Vrefb) (FIGS. 7 and 8 described later). Or, it may be defined within a set value range centered on the reference voltage Vref.

  Here, FIG. 7 is a diagram illustrating an example of each signal waveform when the determination result of the peak sequential check unit PX illustrated in FIG. 6 is GOOD. FIG. 8 is a diagram illustrating an example of each signal waveform when the determination result of the peak sequential check unit PX illustrated in FIG. 6 is NG.

  For example, as shown in FIGS. 7 and 8, at time t1, the peak determination unit PK is enabled (time t1) when the chip select signal CS output from the control device CPU becomes “Low” level. The determination operation of the part PK is started.

  Then, the peak determination unit PK cancels the reset of the peak hold unit PH by the release signal SR (“High” level) at the falling edge of the zero cross trigger signal ZCT.

  Then, the peak level comparing unit COMP compares the peak voltage SPH held by the peak holding unit PH with the reference voltages Vrefa and Vrefb, and outputs a comparison result signal SCOMP corresponding to the comparison result (time t2).

  Then, when the peak voltage SPH held by the peak hold unit PH is in the reference voltage range VrefX (FIG. 7), the peak level comparison unit COMP outputs the “Low” level comparison result signal SCOMP (FIG. 7). Time t2 to t3).

  On the other hand, when the peak voltage SPH held by the peak hold unit PH is not in the reference voltage range VrefX (FIG. 8), the peak level comparison unit COMP outputs the “High” level comparison result signal SCOMP (FIG. 8). Time t2a to t2b).

  Thereafter, the peak determination unit PK confirms (acquires) the comparison result signal SCOMP output from the peak level comparison unit COMP at the rising edge of the zero-cross trigger signal ZCT. Then, it is determined as abnormal NG (FIG. 8).

  After the above determination, the peak determination unit PK sets the release signal SR to the “Low” level and resets the peak hold unit PH.

  The peak determination unit PK determines that the initial state (before time t2) is abnormal NG, and sequentially performs GOOD / NG determination during a period when the chip select signal CS is at the “Low” level (between times t1 and t3). Output.

  Further, the peak determination unit PK stores the result in the memory when the NG determination is made during the period when the chip select signal CS is at the “Low” level. At time t3, when the chip select signal CS output from the control device CPU becomes the “High” level, the peak determination unit PK ends the monitoring, confirms the memory, confirms the determination, and determines the determination result. A peak determination signal PD is output based on the corresponding determination result.

  The peak determination unit PK latches the determination until the next chip select signal CS is input.

  Further, as shown in FIG. 1, the control device CPU controls the AC power source AC to apply the AC voltage VAC to the load DUT to be measured, and sets the voltage value of the output voltage VOUT of the load DUT measured by the voltmeter. Based on this, a test of the load under test DUT is executed.

  Further, the control device CPU determines whether or not the AC voltage VAC is normally applied to the test load DUT during the test of the test load DUT based on the peak determination signal PD and the cycle determination signal SD. It has become.

  In addition, when the peak determination signal PD indicates that the peak voltage is not in the above-described reference voltage range VrefX, the control device CPU normally applies the AC voltage VAC to the load under test DUT during the test of the load under test DUT. It has come to judge that it is not.

  Similarly, when the cycle determination signal SD indicates that the cycle of the zero cross trigger signal ZCT is not within the reference cycle range BF, the control device CPU applies the AC voltage VAC to the load DUT during the test of the load DUT. It is judged that it is not applied normally.

  Further, the control device CPU indicates that the peak voltage is in the reference voltage range VrefX by the peak determination signal PD, and the cycle determination signal SD indicates that the cycle of the zero cross trigger signal ZCT is in the reference cycle range BF. In this case, it is determined that the AC voltage VAC is normally applied to the load under test DUT during the test of the load under test DUT.

  Further, the control device CPU sets the reference pulse period BP corresponding to the AC voltage VAC applied to the load DUT by controlling the AC power supply AC in the first and second cycle determination units SA1 and SA2. ing.

  The control device CPU controls the AC power supply AC and supplies a reference voltage Vref corresponding to the AC voltage VAC applied to the load DUT to be tested to the peak sequential check unit.

  In addition, the control device CPU starts the determination operation of the peak determination unit PK by outputting a chip select signal CS to the peak determination unit PK.

  Further, the control device CPU outputs the chip select signal CS and the start signal CYCSTRT to the first and second cycle determination units SA1 and SA2, thereby performing the determination operation of the first and second cycle determination units SA1 and SA2. It is supposed to start.

  Further, the output device OX outputs (notifies the user) the above-described determination result as to whether or not the AC voltage VAC is normally applied to the test load DUT while the control device CPU is testing the test load DUT. It has become.

  As described above, the test apparatus 100 sequentially monitors the peak value and cycle of the AC power supply AC in a test in which AC is applied to a load (regulator, etc.) using the AC power supply AC, and exceeds the allowable range during the test. If there is an error, it will be notified as abnormal.

  Next, an example of a control method of the test apparatus 100 having the above configuration will be described.

  First, the control device CPU controls the AC power supply AC to apply the AC voltage VAC to the load DUT to be tested, and based on the voltage value of the output voltage VOUT of the load DUT measured by the voltmeter, the test load DUT Run the test.

  During this test, the cycle sequential check unit SX determines whether or not the cycle of the zero cross trigger signal ZCT output from the zero cross trigger generation unit ZX is within a preset reference cycle range BF, and based on this determination result A cycle determination signal SD is output.

  Furthermore, during this test, the peak sequential check unit PX compares the peak voltage of the AC voltage VAC with a preset reference voltage Vref (peak reference value) in synchronization with the zero cross trigger signal ZCT, and the peak voltage is It is determined whether or not the reference voltage range VrefX is defined by the reference voltage Vref.

  Then, during the test, the control device CPU performs alternating current during the test of the DUT under test based on the peak determination signal PD output from the peak sequential check unit PX and the cycle determination signal SD output from the cycle sequential check unit SX. It is determined whether or not the voltage VAC is normally applied to the load under test DUT.

  For example, when the peak determination signal PD indicates that the peak voltage is not in the above-described reference voltage range VrefX, the control device CPU normally applies the AC voltage VAC to the load under test DUT during the test of the load under test DUT. Judge that it is not.

  Similarly, when the cycle determination signal SD indicates that the cycle of the zero cross trigger signal ZCT is not within the reference cycle range BF, the control device CPU applies the AC voltage VAC to the load DUT during the test of the load DUT. Judge that it is not applied normally.

  Further, the control device CPU indicates that the peak voltage is in the reference voltage range VrefX by the peak determination signal PD, and the cycle determination signal SD indicates that the cycle of the zero cross trigger signal ZCT is in the reference cycle range BF. In this case, it is determined that the AC voltage VAC is normally applied to the load under test DUT during the test of the load under test DUT.

  Then, the output device OX outputs (notifies the user) the above-described determination result as to whether or not the AC voltage VAC is normally applied to the test load DUT while the control device CPU is testing the test load DUT.

  According to the control method of the test apparatus 100, when there is no abnormality in the AC voltage output from the AC power source, it is proved that the test is effective.

  Here, an example of an electronic component manufacturing method using the test apparatus 100 according to the present embodiment will be described. FIG. 9 is a diagram illustrating an example of a flow of a method for manufacturing an electronic component using the test apparatus 100 illustrated in FIG.

  First, as shown in FIG. 9, a step of manufacturing an electronic component (a load DUT to be tested) (step S1).

  Next, an electronic component that is the load DUT to be tested is tested with an AC voltage by the test apparatus 100 according to the present embodiment (step S2).

  Then, as described above, it is determined whether or not an AC voltage is normally applied to the electronic component during the test of the electronic component by the test apparatus 100.

  Thereby, when there is no abnormality in the AC voltage output from the AC power source by the test apparatus 100, it is proved that the test is effective.

  Next, processing according to the result of testing the electronic component is executed (step S3).

  The processing according to the result of testing the electronic component in step S3 may include determining whether the result of testing the electronic component is good or not, or changing the manufacturing conditions of a manufacturing apparatus that manufactures the electronic component. .

  According to the method for manufacturing an electronic component using such a test apparatus 100, the reliability of the electronic component can be improved.

  As described above, the test apparatus according to one aspect of the present invention is a test apparatus that tests the load under test DUT with the AC voltage VAC, the AC power supply AC that outputs the AC voltage VAC to the load under test, and the AC voltage. A zero-cross trigger generator ZX that outputs a zero-cross trigger signal ZCT that is inverted when the VAC is input and the AC voltage VAC becomes zero, and the peak voltage of the AC voltage VAC is preset in synchronization with the zero-cross trigger signal ZCT. The reference voltage (peak reference value) Vref is compared, it is determined whether or not the peak voltage is in the reference voltage range VrefX defined by the reference voltage Vref, and the peak determination signal PD based on this determination result is output. It is determined whether the cycle of the sequential check unit PX and the zero cross trigger signal ZCT is within a preset reference cycle range BF. The cycle sequential check unit SX that outputs a cycle determination signal SD based on the determination result, and the output voltage VOUT output by the load under test in response to the input of the AC voltage VAC are measured, and the voltage value of the output voltage VOUT is output. A voltmeter VX that controls the AC power supply, applies an AC voltage VAC to the load under test, and executes a test of the load under test based on the voltage value of the output voltage VOUT of the load under test measured by the voltmeter And a control device CPU for determining whether or not the AC voltage VAC is normally applied to the load under test during the test of the load under test based on the peak determination signal PD and the cycle determination signal SD.

  As described above, in the test apparatus of the present invention, each of the peak and cycle of the AC voltage output from the AC power supply is sequentially monitored while the test of the load under test is performed with the AC voltage output from the AC power supply. It is determined whether or not there is an abnormality in the AC voltage output by.

  Thereby, when there is no abnormality in the AC voltage output from the AC power source, it is proved that the test is effective.

  That is, according to the test apparatus of the present invention, it is possible to improve the reliability of the test of the load under test performed with the AC voltage output from the AC power supply.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

100 Test Equipment AC AC Power Supply ZX Zero Cross Trigger Generation Unit PX Peak Sequential Checking Unit VX Voltmeter CPU Controller OX Output Device DUT Tested Load (Electronic Component)
DX Periodic distributor SA1 First cycle determination unit SA2 Second cycle determination unit RC Logic circuit PH Peak hold unit COMP Peak level comparison unit PK Peak determination unit

Claims (15)

A test apparatus for testing a load under test with an alternating voltage,
An AC power supply for outputting the AC voltage to the load under test;
A zero-cross trigger generator that outputs a zero-cross trigger signal that is input when the AC voltage is input and is inverted when the AC voltage becomes zero;
In synchronization with the zero-cross trigger signal, the peak voltage of the AC voltage is compared with a preset reference voltage to determine whether the peak voltage is within a reference voltage range defined by the reference voltage, A peak sequential check unit that outputs a peak determination signal based on the determination result;
A cycle sequential check unit that determines whether or not the cycle of the zero-cross trigger signal is within a preset reference cycle range and outputs a cycle determination signal based on the determination result;
Measure the output voltage output by the load under test according to the input of the AC voltage, and output a voltage value of the output voltage; and
Controlling the AC power supply, applying the AC voltage to the load under test, and executing the test of the load under test based on the voltage value of the output voltage of the load under test measured by the voltmeter, A controller for determining whether or not the AC voltage is normally applied to the load under test during the test of the load under test based on the peak determination signal and the cycle determination signal. To test equipment. The control device includes:
When the peak determination signal indicates that the peak voltage is not in the reference voltage range, or when the cycle determination signal indicates that the period of the zero cross trigger signal is not in the reference period range, the load under test The test apparatus according to claim 1, wherein it is determined that the AC voltage is not normally applied to the load under test during the test. The control device includes:
When the peak determination signal indicates that the peak voltage is in the reference voltage range, and the cycle determination signal indicates that the period of the zero cross trigger signal is in the reference period range, The test apparatus according to claim 2, wherein it is determined that the AC voltage is normally applied to the load under test during a test. 4. The output device according to claim 3, further comprising: an output device that outputs a determination result as to whether or not the AC voltage is normally applied to the load under test during the test of the load under test. Test equipment. The peak sequential check unit
A peak hold unit that holds the peak voltage of the AC voltage in synchronization with the zero-cross trigger signal;
A peak level comparison unit that compares the peak voltage held by the peak hold unit with the reference voltage and outputs a comparison result signal according to the comparison result;
A peak determination unit that determines whether or not the peak of the AC voltage is in the reference voltage range based on the comparison result signal and outputs the peak determination signal based on the determination result. The test apparatus according to claim 3. The cycle sequential check unit includes:
A periodic distributor for distributing the zero-cross trigger signal to a first distribution signal and a second distribution signal having the same period and frequency as the first distribution signal;
It is determined whether or not the first pulse period from when the pulse of the zero cross trigger signal rises until the pulse of the first distribution signal falls is within a preset reference pulse period. A first cycle determination unit that outputs a first cycle determination signal based on
It is determined whether or not the second pulse period from when the pulse of the zero cross trigger signal rises until the pulse of the second distribution signal falls is within the reference pulse period, and based on this determination result A second cycle determination unit that outputs a second cycle determination signal;
A logic circuit that receives the first and second cycle determination signals and outputs a signal obtained by calculating the first and second cycle determination signals as the cycle determination signal. The test apparatus according to claim 5. The logic circuit is:
The test apparatus according to claim 6, wherein the test apparatus is an OR circuit that performs an OR operation on the first and second cycle determination signals and outputs a signal obtained by the OR operation as the cycle determination signal. The control device includes:
The test according to claim 6, wherein the reference pulse period corresponding to the AC voltage applied to the load under test by controlling the AC power supply is set in the first and second cycle determination units. apparatus. The control device includes:
The test apparatus according to claim 5, wherein the reference voltage corresponding to the AC voltage applied to the load under test by controlling the AC power supply is supplied to the peak sequential check unit. 7. The test apparatus according to claim 6, wherein a circuit configuration and a function of the first cycle determination unit are the same as a circuit configuration and a function of the second cycle determination unit. The control device includes:
The test apparatus according to claim 8, wherein the determination operation of the peak determination unit is started by outputting a chip select signal to the peak determination unit. The peak determination unit
Cancel the reset of the peak voltage hold of the peak hold unit at the first level of the zero cross trigger signal,
Determining whether the peak of the AC voltage is within the reference voltage range based on the comparison result signal at the second level of the zero-cross trigger signal;
Thereafter, the hold of the peak voltage of the peak hold unit is reset. The test apparatus according to claim 11. A test apparatus for testing a load under test with an AC voltage, the AC power source outputting the AC voltage to the load under test, and a zero cross trigger that reverses when the AC voltage is input and the AC voltage becomes zero A zero-cross trigger generator that outputs a signal, a peak voltage of the AC voltage is compared with a preset reference voltage in synchronization with the zero-cross trigger signal, and the peak voltage is defined by the reference voltage A peak sequential check unit that outputs a peak determination signal based on the determination result, and determines whether or not the period of the zero cross trigger signal is within a preset reference period range. The cycle sequential check unit that outputs a cycle determination signal based on the determination result, and the load under test outputs according to the input of the AC voltage A force voltage is measured, a method of controlling a test apparatus including a voltage meter for outputting a voltage value of the output voltage, and a control unit, a
The control device controls the AC power supply, applies the AC voltage to the load under test, and tests the load under test based on the voltage value of the output voltage of the load under test measured by the voltmeter. And determining whether or not the AC voltage is normally applied to the load under test during the test of the load under test based on the peak determination signal and the cycle determination signal. Control method of test equipment. Manufacturing electronic components;
Testing the electronic component being a load under test with an alternating voltage by the test apparatus according to claim 1;
A step of performing processing according to the result of testing the electronic component,
It is determined whether or not the AC voltage is normally applied to the electronic component during the testing of the electronic component by the test apparatus.   The processing according to the result of testing the electronic component includes determining whether the result of testing the electronic component is good or changing manufacturing conditions of a manufacturing apparatus for manufacturing the electronic component. The method for manufacturing an electronic component according to claim 14.

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